Slave End Vertical Interconnect ------------------------------------ Original Rev. 28-AUG-1998 Most Recent Rev. 29-SEP-2000 Setup of the slave end Vertical Interconnect for use in the Run II Trigger Framework. The idea is to have all of them setup in a standard way. No MC68153 installed at U25 ! need only if the master is going to cause the slave VI to generate interrupts in the slave crate. I have seen a jumper installed between pins 6 and 7 of this IC's socket. This jumpers IACKIN to IACKOUT which would let you pass the VME IACK signal through the crate slot occupied by the Vertical Interconnect when the Vertical Interconnect does not have a MC68153 installed. No chip installed at U38 ! standard for slave end No MIZAR needs to be installed at U20 unless you have other potential bus masters in the crate and need the slot 1 arbiter. Does the MIZAR also supply BERR timeout for the slave crate ? TAXI chips installed only at U21 and U31, not installed at U22, U23, U24, U32, U33, U34. The 3 quad PALs (U13, U37, and U39) plus the 5 dip PALs (U40, U41, U46, U48, and U49) are all installed. Switch SW1 The standard setup that we have seen is, All keys are closed ON except for key #2 which is open. I believe that this puts the 512 bytes of of BIM and master interrupt control in the address range $8000 through $8100 J1 through J8 are all open ! Cable Shield not grounded at slave end J9 jump pin 1 to 16, junp pin 2 to 15, jump pin 9 to 10, jump pin 11 to 12, jump pin 13 to 14, all others open ! This is the VME Bus Priority Grant Level This set of jumpers puts it at level 3. This setup (9 to 10, 11 to 12, 13 to 14) is correct and is not what is in the manual. J10 jump ! SYSCLK Enable If the arbiter is enabled (J15) then J10 enables the SYSCLK onto the VME Bus jump --> emable J11 jump ! BERR Enable Enable BERR onto the Module (if not slot 1 controller) or onto the VME Bus (if slot 1 controller) jump --> enable J12 jump pin 4 to pin 5, all others open ! This is the VME Bus Requester Priority Level. Jump 4 to 5 implies request the VME Bus at Priority Level 3. J13 open ! Enable this card to be the VI master end. With proper PALs installed then this jumper makes this card a VI master. J14 jump ! Enable Priority If the arbiter is enabled (J15) then J14 picks the type of arbitration jump --> priority open --> round robin. J15 jump ! Enable the arbiter and other slot 1 functions. jump --> enable J16 open ! Enable transmission violations to halt the on going cycle in the slave crate jump --> enable. See the file MSUTRGROOT_II:[HARDWARE.COMM_CRATE]VME_COMMUNICATION_CRATE.TXT for background information. When tested on 21-SEPT-1999 the Slave Vertical Interconnect was producing Supervisor Data Mode cycles in the target crate, i.e. AM value $3d. The timing of a read cycle in the target crate (reading from an FM card running on a 50 MHz clock) typically looks like: | | -->| |<--- 75 to 80 nsec | | ------------- ---------------------------- AS | | - ------------------------------- ------- ---------------------------- AM | | - ------------------------------------- ------------------------------------- -------- DTack | | - --------------------------- | | | | | 135 nsec --->| |<--- | | | | | | | | |<----- 470 nsec ------>|<------- 410 nsec ------>| | | | 29-SEPT-2000 The URL for the Vertical Interconnect document is: http://www-linac.fnal.gov/LINAC/hardware/vmesys/boards/vi/viInfo.html