Beam Crossing History Shift Register Programming ------------------------------------------------ Original: 6-MAY-1998 Latest: 6-MAY-1998 As shown in the L1 Framework System Level Timing diagram, if the data is presented to the TRM in Tick 1, the Capture Data signal arrives during Tick 6. This means that the data is captured at the end of Tick 6/ the beginning of Tick 7. The following table then describes which Ticks will be read out from the various different FPGAs as a function of the Beam Crossing History Shift Register programming. First Half of the Framework --------------------------- BXHSR Stage 1 FPGA Delay Ticks Read Out ---- ------------- -------------- Miguel 0 TT+4, TT+3, TT+2, TT+1 1 TT+3, TT+2, TT+1, Triggered Tick 2 TT+2, TT+1, Triggered Tick, TT-1 3 TT+1, Triggered Tick, TT-1, TT-2 4 Triggered Tick, TT-1, TT-2, TT-3 AONM/FOM 0 TT+1, TT+2, TT+3 1 Triggered Tick, TT+1, TT+2 2 TT-1, Triggered Tick, TT+1 3 TT-2, TT-1, Triggered Tick 4 TT-3, TT-2, TT-1 PBS 0 TT+2 1 TT+1 2 Triggered Tick 3 TT-1 4 TT-2 GS 0 TT+2 1 TT+1 2 Triggered Tick 3 TT-1 4 TT-2 TDM 0 TT+1, TT+2, TT+3 1 Triggered Tick, TT+1, TT+2 2 TT-1, Triggered Tick, TT+1 3 TT-2, TT-1, Triggered Tick 4 TT-3, TT-2, TT-1 Second Half of the Framework --------------------------- BXHSR Stage 1 FPGA Delay Ticks Read Out ---- ------------- -------------- Miguel 0 TT+3, TT+3, TT+1, Triggered Tick 1 TT+2, TT+1, Triggered Tick, TT-1 2 TT+1, Triggered Tick, TT-1, TT-2 3 Triggered Tick, TT-1, TT-2, TT-3 4 TT-1, TT-2, TT-3, TT-4 AONM/FOM 0 Triggered Tick, TT+1, TT+2 1 TT-1, Triggered Tick, TT+1 2 TT-2, TT-1, Triggered Tick 3 TT-3, TT-2, TT-1 4 TT-4, TT-3, TT-2 PBS 0 TT+1 1 Triggered Tick 2 TT-1 3 TT-2 4 TT-3 GS 0 TT+1 1 Triggered Tick 2 TT-1 3 TT-2 4 TT-3 TDM 0 Triggered Tick, TT+1, TT+2 1 TT-1, Triggered Tick, TT+1 2 TT-2, TT-1, Triggered Tick 3 TT-3, TT-2, TT-1 4 TT-4, TT-3, TT-2