Draft: 24-MAR-1997 High Speed Readout Data Block Format A. Specific Trigger Fired Mask Specific Trigger Fired Mask 128 bits = 4 longwords support (from Trigger Qualifier/SpTrg Group FOM?) B. Absolute Time (?) a few longwords Low resolution (e.g. 15 Hz) date/time stamp C. Trigger Number(s) Level 1 Trigger Accept Number 32 bits = 1 longword support This is a sequential number counting the number of L1 Trigger Accepts. Beam Crossing number(s) Turn Count 32 bits = 1 longword support Bunch ID 8 bits = 1 longword support Level 1 Geographic Section Trigger Number 24 bits = 1 longword This is a composite 16 bit turn and 8 bit bunch number and may not be available for inclusion in data block. It will more likely be available instead as its two separate pieces: Turn Count 32 bits = 1 longword support Bunch ID 8 bits = 1 longword support The Level 1 Trigger Framework maintains2 sets of scalers (or "2 sets of books"), for the Beam Crossing Number. The first set of scalers provides the "Detector time" Beam crossing Number that is broadcasted for every Beam Crossing to all Geographic Sections. Additionally, for every L1 Trigger Accept, the Level 1 Framework will send to all Geographic Sections a "Level 1 Geographic Section Trigger Number" that identifies the (earlier) Beam Crossing for which the detector information must be saved. There is a fixed delay, and thus a fixed number of Beam Crossings between a given Beam Crossing and the time its correponding Level 1 Trigger Accept Decision is received by the Geographic Section. This means that there is a constant difference between the current "Detector Time" Beam Crossing Number and the "Level 1 Geographic Section Trigger Number". The Level 1 Trigger Framework maintains the two sets of scalers whith counts separated by a constant difference corresponding to the processing time of the trigger information through the Level 1 Trigger System. For every Level 1 Trigger Accept received by the Front-Ends, all Geographic Sections check that the Level 1 Geographic Section Trigger Number correctly match the Beam Crossing Number that was captured with the detector data. This cross-check will detect any sudden de-synchronization of the Level 1 Framework scalers or any de-synchronization of the Front-End FIFO stages used to buffer the Detector Data during the Level 1 Trigger processing. The communication protocol of the Geographic Sections allows the Front-Ends to notify the Level 1 Trigger Framework of the detected error. D. Level 1 Qualifiers generated by a FOM same 16 Qualifiers to all Geographic Sections ------------------ 1 Longword total Level 1 Trigger Accept Qualifier State 16 bits for Qualfier #n [n=0:16] ------------------ 1 Longword total E. And-Or Input Terms 64 And-Or Terms serviced per TRM Card 4 And-Or Terms serviced per TRM Card FPGA And-Or Term Input State for Terms #8n:8n+7 [n=0:32] longword#=constant+n And-Or Input Term 8n+p [p=0:7]: Pre-Previous Crossing Bit #4*p+0 or 2nd Next instead? Previous Crossing Bit #4*p+1 Current Crossing Bit #4*p+2 Next Crossing Bit #4*p+3 ------------------ 8 Longwords per TRM 32 Longwords for all And-Or Terms F. Specific Trigger 8 Specific Triggers serviced per TDM Card Specific Trigger States for Sptrg #n [n=0:127] Longword # constant+3*n+0 Specific Trigger Fired State ? Previous Crossing Bit # Current Crossing Bit #0 ? Next Crossing (or would be firing?) Bit # Specific Trigger Exposed State Previous Crossing Bit #2 Current Crossing Bit #3 Next Crossing Bit #4 SpTrg Physics And-Or Fired State Previous Crossing Bit #5 Current Crossing Bit #6 Next Crossing Bit #7 Current Crossing Lower And-Or Terms Bit #8 Current Crossing Upper And-Or Terms Bit #9 SpTrg And-Or Exposure Group Enable State Previous Crossing Bit #10 Current Crossing Bit #11 Next Crossing Bit #12 Current Crossing Lower And-Or E.G.E.S Bit #13 Current Crossing Upper And-Or E.G.E.S Bit #14 SpTrg DAQ Enable State Previous Crossing Bit #15 Current Crossing Bit #16 Next Crossing Bit #17 Specific Trigger Disable Mask Front-End Busy Disable Bit #18 Prescaler Disable Bit #19 COOR Disable Bit #20 Auto-Disable Bit #21 Gated Individual Disable #0 Bit #22 Gated Individual Disable #1 Bit #23 Gated Internal Global Disable #0 Bit #24 Gated Internal Global Disable #1 Bit #25 Gated Internal Global Disable #2 Bit #26 Gated Internal Global Disable #3 Bit #27 Gated External Global Disable #0 Bit #28 Gated External Global Disable #1 Bit #29 Gated External Global Disable #2 Bit #30 Gated External Global Disable #3 Bit #31 ------------- 1 longword Specific Trigger Fired Scaler Count Longword # constant+3*n+1 Specific Trigger Exposed Scaler Count Longword # constant+3*n+2 ------------------ 24 Longwords per TDM 384 Longwords for all SpTrg G. Geographic Section 64 Geographic Sections serviced by a FOM Card 4 Geographic Sections serviced per FOM FPGA Geographic Section L1 Accept State for Sections #8n:8n+7 [n=0:15] longword#=constant+n Geographic Section 8n+p [p=0:7]: Pre-Previous Crossing Bit #4*p+0 or 2nd Next instead? Previous Crossing Bit #4*p+1 Current Crossing Bit #4*p+2 Next Crossing Bit #4*p+3 ------------------ 8 Longwords per FOM 16 Longwords for all GeoSect 64 Geographic Sections serviced by a TRM Card 4 Geographic Sections serviced per TRM FPGA Geographic Section Front-End Busy State for Sections #8n:8n+7 [n=0:15] longword#=constant+n Geographic Section 8n+p [p=0:7]: Pre-Previous Crossing Bit #4*p+0 or 2nd Next instead? Previous Crossing Bit #4*p+1 Current Crossing Bit #4*p+2 Next Crossing Bit #4*p+3 ------------------ 8 Longwords per TRM 16 Longwords for all GeoSect H. "Foreign Scalers" yes/no? e.g. time since something last happened. scalers on the qualifiers? I. Luminosity = per bunch scalers NO ------------------- Grand Total 468 longwords + more Summary: -------- card per-card system-wide type quantities totals ------ ---------- ----------- C. TQ-FOM 16 w 16 w L1 Accept Qualifiers E. AO-TRM 16 w 64 w And-Or Terms F. TDM 48 w 768 w Trigger Decision Module G. GS-FOM 16 w 32 w Geographic Section Start Digitize G. GS-TRM 16 w 32 w Geographic Section Front-End Busy Questions: ---------- 1_ should this Description be in bytes/word/longwords? 16 bit word matches transfer size. 32 bit is probably the better choice for machine independence. 2_ Is the Turn count 32 or 64 bits? 3_ This does not include the "Individual" and "Global" SpTrg Signals as read at the receiving TRM card, but they are included (after being gated) at the TDM. - saves 80 Words of readout - more logical place in TDM? This does not include the SpTrg And-Or Exposure Group Enable State as generated on the And-Or Cards, but only as read at the TDM 4_ What is missing? Really "no" scalers besides TDM? This means absolutely counting on monitor readout of per-bunch scalers + run database. Are we ready to sign up for that? 5_ Run I had a Gated Beam Crossing Number 6_ Do we need to readout scalers for the Trigger Qualifiers? 7_ Do we need/want to readout current/previous information for the Trigger Qualifiers? One reason is to use the same FOM FPGA programming for the Geographic Section FOMs and the Trigger Qualifier FOM. Notes: ------ missing: 1_ Recall: 16 FPGAs/card 16-bit readout path 4 High Speed Link per VRB 2_ This does not yet include the Card Level Header Longword Not yet fully specified, e.g.: Most Significant Byte Card ID assigned by TCC e.g. 8 crates (3 bits) * 32 slots (5 bits) or 16 card types (4 bits) * 16 card instance (4 bits) Upper Middle Byte Card Status e.g. standard readout 1 bit special test 1 bit header only; no data 1 bit Lower Middle Byte Spare e.g. number of 16 bit words read out or checksum/CRC Least Significant Byte Readout Count (for synch checking purpose) Rolls over quickly, but glitches will appear as mismatches between cards for subsequent events. 3_ Here are included all the "Not-essential-but-sometimes-convenient" items that we had listed; all except for the prescale ratio. If we change our mind and want the prescale ratios, these fixed programmed values can copied by TCC and read out elsewhere. 5_ Assume 8 us available for data transfer. Reading out the "necessary" data is ZERO problem. 8 us / 16 words = 500 us/word. Worst case is TDM w/ all "optional" stuff at a max of 64 words 8 us / 64 words = 125 ns/word ===> tantalizingly close to 132 8 us / 56 words = 143 ns/word ==> could read out at 132 ns -> technical possibility of 132 ns not yet clear though! Readout clock at 132us is a big advantage, it lets us use the main "do it" timing signal on each card as a readout clock (probably). Recall that the "do it" clock will be phase-shifted between the 2 cards in a single "tick" pipeline stage. Can this phase shift be lived with (may need to have 2 flavors of "data valid" to Finisar module)? Recall that each row of FPGA's only has 4 timing signals. Also related to this phase difference, may need different versions of L1 Accept (out of BSF FPGA) for the 2 halves of the "tick". 6_ Start on Timing Signal usage: 0: 53.104 MHz accelerator clock 1: Pipeline stage 1, 3 "do it" clock (TRM, TDM) 2: Pipeline stage 2, 4 "do it" clock (AONM, FOM) 3: Pipeline stage 1, 3 L1 Accept/Capture Monitor Data clock 4: Pipeline stage 2, 4 L1 Accept/Caputre Monitor Data clock 5: Capture Monitor Data Gate 6: Scaler reset? Initialize? 7: