Notes on HSRO Timing
                   ------------------------

                                             Original Version  10-JULY-00
                                             Current Version   26-SEPT-00


The purpose of this file is to describe the timing of the HSRO data
as it is Captured and then Pushed out from a THE-Card.

Time Structure of High-Speed Readout on a single card, assuming 2 words
of data from each of the 16 main array FPGA's and 4 words of data from 
the BSF FPGA.   Thus there are a total pf 40 words coming from a THE-Card:

2W Header  +  32W from Main Array FPGA's  +  4W data from BSF  +  2W Trailer




     Time      Action
     ----      ------
    -264 ns    Receive Capture High Speed Readout Data via P1

       0 ns    Receive Transport High Speed Data via P1

     132 ns    BSF internally addresses Header Word 0

     264 ns    BSF sends Header Word 0 to HSROCB
               BSF internally addresses Header Word 1

     396 ns    BSF sends Header Word 1 to HSROCB
               BSF asserts DCE Out to MSA FPGA 1

     528 ns    MSA FPGA 1 internally addresses Data Word 0
  
     660 ns    MSA FPGA 1 sends Data Word 0 to HSROCB
               MSA FPGA 1 internally addresses Data Word 1
               MSA FPGA 1 asserts DCE out to MSA FPGA 2

     792 ns    MSA FPGA 1 Sends Data Word 1 to HSROCB
               MSA FPGA 2 internally addresses Data Word 0

     924 ns    MSA FPGA 2 sends Data Word 0 to HSROCB
               MSA FPGA 2 internally addresses Data Word 1
               MSA FPGA 2 asserts DCE out to MSA FPGA 3
       .           .
       .           .
       .           .
       .           .

     4620 ns   MSA FPGA 16 sends Data Word 0 to HSROCB
               MSA FPGA 16 internally addresses Data Word 1
               MSA FPGA 16 asserts DCE Out to BSF FPGA   

     4752 ns   MSA FPGA 16 sends Data Word 1 to HSROCB
               BSF FPGA internally addresses BSF Data Word 0

     4884 ns   BSF FPGA sends BSF Data Word 0 to HSROCB
               BSF FPGA internally addresses BSF Data Word 1

     5016 ns   BSF FPGA sends BSF Data Word 1 to HSROCB
               BSF FPGA internally addresses BSF Data Word 2

     5148 ns   BSF FPGA sends BSF Data Word 2 to HSROCB
               BSF FPGA internally addresses BSF Data Word 3

     5280 ns   BSF FPGA sends BSF Data Word 3 to HSROCB
               BSF FPGA internally addresses Trailer Word 0
              
     5412 ns   BSF FPGA sends Trailer Word 0 to HSROCB
               BSF FPGA internally addresses Trailer Word 1
               
     5544 ns   BSF FPGA sends Trailer Word 1 to HSROCB
               BSF FPGA drops DCE Out to MSA FPGA 1
               (this propagates asynchronously through all MSA FPGA's



Notes:  At time point 528 nsec there is no data sent to the HSROCB
        and thus we get a gap between the 2nd Header word and the 1st
        word from Main Array FPGA #1.  We see this 132 nsec gap on
        the logic analyzer.

        From the first data to the HSROCB to the last data to the 
        HSROCB is about 5.3 usec which is what we see on the logic
        analyzer.




The Readout Order is therefore:

    BSF Header - MSA 1 - MSA 2 - ... - MSA 16 - BSF Data - BSF Trailer


Note that the readout order is not changeable, but any MSA FPGA may 
optionally provide more or less than 2 Data Words.  Note that if any
MSA FPGA provides 0 data words, that FPGA still requires 132 ns to
pass the DCE In to DCE Out.  During this 132 ns, the HSROCB sends 7
Fill Frames.  




Timing diagram of 132-ns ticks:

               18.8 ns            132 ns
                |---|   |---------------------------|

                 5   6   0   1   2   3   4   5   6   0   1   2   3   4  
                 _   _   _   _   _   _   _   _   _   _   _   _   _   _  
    Acc Clock  _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

    Tick Clock     ___                         ___
    (Carmen)   ___|   |_______________________|   |_____________________
                           ___                         ___
    BX Clock   ___________|   |_______________________|   |_____________
    (BSF Int)
                                       ___                         ___
    DAV Marker _______________________|   |_______________________|   |_
    (BSF Int)
                           ___                         ___
    Tick Clock ___________|   |_______________________|   |_____________
    (HQ TS)
               _________________________   _________________________   _
    DAV*                                |_|                         |_|
    (to HSROCB)
               ___________ ___________________________ _________________
    HSRO Data  ___________X___________________________X_________________
 
    G-Link      FF  FF  FF  FF  FF  FF  DF  FF  FF  FF  FF  FF  FF  DF     
                
                (FF = Fill Frame        DF = Data Frame)





Questions:  Does this mean that the data from the Main Array FPGA's
            only has 56 nsec to settle before it is used by the G-Link
            Transmitter ?




Old Obsolete Notes
------------------

From when the VRB had >N fill frames == End of Event

Therefore, with the "16 Fill Frames = End of Event" logic
in the VRB, we cannot have more than 2 "0 Data Word" FPGA's on a single
card.  In the worst case, we could have up to 16 "0 Data Word" FPGA's on
a single card (i.e. send only Header and Trailer from BSF, skip readout
of all 16 MSA's).  This corresponds to 16*7 = 112 Fill Frames corresponding
to DCE propagation, plus some additional FF's which naturally occur as part
of the actual data transfer (7 or so FF's).  To guarantee that we never
bump into this problem, I would like to see something like "150 Fill Frames
= End of Event."