L1 Framework Data Block Readout ------------------------------- Original: 5-AUG-1999 Revised: 9-MAR-2001 High-Level View --------------- First simply define the elements that are read out from the L1 Framework via High-Speed Readout (i.e. through the VRB): 1. 256 And-Or Input Terms - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x256 = 1024 bits = 128 bytes = 64 words - source: (4) And-Or Input TRM's - in simulator? yes 2. 256 And-Or Input Terms - read out for: Triggered Tick, TT-2, TT-3 - data quantity: 3x256 = 768 bits = 96 bytes = 48 words - source: (2) EG AONM cards (2 sets of 4 Miguel FPGA's per card) - in simulator? ???????? 3. 16 Partial Exposure Group Enables - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x16 = 64 bits= 8 bytes = 4 words - source: (2) EG AONM cards (only 2 FPGA's per card) - in simulator? ???????? 4. 256 Partial And-Or Fired Terms - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x256 = 1024 bits = 128 bytes = 64 words - source: (4) PAOF AONM cards - in simulator? ?????????? 5. 128 Geographic Sections L1 Front End Busy Signals - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x128 = 512 bits = 64 bytes = 32 words - source: (2) L1 Busy per Geo Section TRM's - in simulator? no??? 6. 128 Geographic Sections L1 Front End Busy Signals - read out for: Triggered Tick, TT-2, TT-3 - data quantity: 3x256 = 768 bits = 96 bytes = 48 words - source: (1) FEBZ FOM card (2 sets of 4 Miguel FPGA's) - in simulator? ???????? 7. L1 Busy for each of the 8 Exposure Groups - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x8 = 32 bits = 4 bytes = 2 words - source: (1) L1 Busy per Exposure Group FOM (only 2 FPGA's) - in simulator? only if item 5 is in simulator 8. 8 L1 Specific Trigger Global Disables - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x8 = 32 bits = 4 bytes = 2 words - source: (1) L1 Global Disable TRM (only 2 FPGA's) - in simulator? no??? 9. 2 Individual Disables for each of the 128 Specific Triggers - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x2x128 = 1024 bits = 128 bytes = 64 words - source: (4) L1 Individual Disable TRM's - in simulator? no??? 10. 32 Status Signals for each of the 128 Specific Triggers - see the "TDM" section below for details on these status signals - data quantity: 32x128 = 4096 bits = 512 bytes = 256 words - source: (8) L1 Accept TDM's - in simulator? some yes, some no 11. L1 Accept for each of the 128 Geographic Sections - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x128 = 512 bits = 64 bytes = 32 words - source: (2) L1 Accept per Geographic Section FOM's - in simulator? ?????????? 12. 128 Specific Trigger Fired Signals - read out for: Triggered Tick - data quantity: 1x128 = 128 bits = 16 bytes = 8 words - source: (1) FOM++ card (4 Miguel FPGA's) - in simulator? ?????????? 13. 2 Sets of 16 L1 Qualifier Bits - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x16x2 = 128 bits = 16 bytes = 8 words - source: (1) FOM++ (2 sets of 4 FPGA's) - in simulator? yes 14. 16 Other signals associated with Global L1 Accept - data: 4 copies of Global L1 Accept 4 copies of Skip Next Tick 4 (different) "Skip Next Ticks" 4 (different) Diagnostic Scaler Control outputs - read out for: Triggered Tick, TT-1, TT+1, TT+2 - data quantity: 4x16 = 64 bits = 8 bytes = 4 words - source: (1) FOM++ (only 4 FPGA's) - in simulator? Global L1 Accept yes Skip Next Tick yes??? Skip Ticks no??? Diagnostic Scaler Cont no??? 15. Up to 6 different Tick (8-bit) and Turn (32-bit) Scalers - data: L1 Accept Beam X Number: FW Time Zone (Tick and Turn) L1 Accept Beam X Number: FE Time Zone (Tick and Turn) Never Reset L1 Accept Beam X Number (FE Time Zone) others as yet undefined - read out for: Triggered Tick only - data quantity: up to 6*32 = 192 bits = 24 bytes = 12 words - source: (1) TTS - in simulator? no??? 16. Up to 16 different 32-bit Gated Scalers - data: L1 Accept Number L2 Accept Number L2 Decision Number Number of events with L1A awaiting L2 Decision others as yet undefined - read out for: Triggered Tick only - data quantity: up to 16*32 = 512 bits = 64 bytes = 32 words - source: (1) Gated Scaler Card (with 1 L1AL2 FPGA) - in simulator? no??? 17. FIFO Error States, Read and Write Counters (not yet available) - read out for: Triggered Tick - data quantity: 4 error states, 5 bits for read counter, 5 bits for write counter, 1 bit for each read and write counter reset = 16 bits - source: TRM's (4 AOIT, 2 FEBZ, 1 Global Disable, 4 Individual Disable, 2 STF Mask to L2) - in simulator? ???????????? Note that the FIFO Error States are not yet available in the readout. 18. Hardware Qualifiers - read out for: Triggered Tick? - data quantity: ? - source: BSF on (1) FOM++, or where generated if possible - in simulator? ????????????? - comments: Right now, none of the Hardware Qualifiers are used. For any we generate internally the preferance is to read out at the source as we do with the Mark and Force Pass Flags. This is the only chance to get the information on a per Specific Trigger basis. On the BSF of the FOM++ the Qualifiers have already been ORed so that all you know is that at least one of 16 Specific Triggers had its Qualifier asserted. For Qualifiers which are generated externally the FOM++ BSF is the only place we can read them out. In this case the spare Header or Trailer word will be used. NB This means that the Header and/or Trailer information may be different coming from different cards. 19. Static Words - data quantity: up to 24 16-bit words - source: up to 12 SHED's FPGA on (1) Global Disable TRM - in simulator? no? - comments: This is the place where any static or slowly changing information can be inserted into the data stream. The information is stored in 8 registers accessible via TCC; any number of the registers may be included in the readout. Note that some of the information is included in HSRO twice (e.g. the And-Or Input Terms and L1 Front End Busies). Although this isn't necessary for physics, it may be useful in terms of doing some online verification of the cables, etc. Low Level View -------------- The following cards are read out from the L1 Framework (note: here we also define the mapping to VRB's): Card Type Card Description Output Location ID(3) VRB Linkk --------- ---------------- ------ -------- --- -------------------- TRM AOIT 63:0 M123T-10 $8a A-0 (Slot#19-ch#0/1) TRM AOIT 127:64 M123T-9 $89 A-1 (Slot#19-ch#2/3) TRM AOIT 191:128 M123T-3 $83 A-2 (Slot#19-ch#4/5) TRM AOIT 255:192 M123T-2 $82 A-3 (Slot#19-ch#6/7) AONM PAOF L 63:0 M123T-14 $8e B-0 (Slot#9-ch#0/1) AONM PAOF L 127:64 M123T-13 $8d B-1 (Slot#9-ch#2/3) AONM PAOF U 63:0 M123T-7 $87 B-2 (Slot#9-ch#4/5) AONM PAOF U 127:64 M123T-6 $86 B-3 (Slot#9-ch#6/7) AONM (1) EG L 7:0 M123T-12 $8c C-0 (Slot#10-ch#0/1) AONM (1) EG U 7:0 M123T-5 $85 C-1 (Slot#10-ch#2/3) TRM (2) Global Disable 7:0 M123T-20 $94 C-2 (Slot#10-ch#3/4) TRM L1Bz Geo Sect 63:0 M123T-17 $91 D-0 (Slot#11-ch#0/1) TRM L1Bz Geo Sect 127:64 M123T-16 $90 D-1 (Slot#11-ch#2/3) FOM (1) L1Bz Exposure Group 7:0 M123T-19 $93 D-2 (Slot#11-ch#4/5) TDM L1 Accept SpecTrig 15:0 M123M-11 $ab E-0 (Slot#12-ch#0/1) TDM L1 Accept SpecTrig 31:16 M123M-10 $aa E-1 (Slot#12-ch#2/3) TDM L1 Accept SpecTrig 47:32 M123M-9 $a9 E-2 (Slot#12-ch#4/5) TDM L1 Accept SpecTrig 63:48 M123M-8 $a8 E-3 (Slot#12-ch#6/7) TDM L1 Accept SpecTrig 79:64 M123M-7 $a7 F-0 (Slot#13-ch#0/1) TDM L1 Accept SpecTrig 95:80 M123M-6 $a6 F-1 (Slot#13-ch#2/3) TDM L1 Accept SpecTrig 111:96 M123M-5 $a5 F-2 (Slot#13-ch#4/5) TDM L1 Accept SpecTrig 127:112 M123M-4 $a4 F-3 (Slot#13-ch#6/7) FOM L1 Accept Geo Sect 63:0 M123M-15 $af G-0 (Slot#16-ch#0/1) FOM L1 Accept Geo Sect 127:64 M123M-14 $ae G-1 (Slot#16-ch#2/3) FOM++ Multiple Functions M123M-16 $b0 G-2 (Slot#16-ch#4/5) TRM Indiv Dsbl 0 SpTrg 63:0 M123B-6 $c6 H-0 (Slot#17-ch#0/1) TRM Indiv Dsbl 0 SpTrg 127:64 M123B-5 $c5 H-1 (Slot#17-ch#2/3) TRM Indiv Dsbl 1 SpTrg 63:0 M123B-3 $c3 H-2 (Slot#17-ch#4/5) TRM Indiv Dsbl 1 SpTrg 127:64 M123B-2 $c2 H-3 (Slot#17-ch#6/7) TTS Tick and Turn Scaler M123B-21 $d5 I-0 (Slot#18-ch#0/1) GS Gated Scaler with L1AL2 M123B-19 $d3 I-1 (Slot#18-ch#2/3) Notes: (1,2) The readout for these cards is somewhat different; see notes in the individual card sections below. (3) Card ID Byte in HSRO THE-Card Header Bit 7 Vertical Master Number (0 = M122, 1 = M123) Bit 6:5 Vertical Slave Number (0 = Top, 1 = Mid, 2 = Bot) Bit 4:0 THE-Card Slot Number (2:21) The L2 Framework is specifically NOT included in the above tally. As the L1 Framework evolves, one or two additional cards may be added to the readout tally, but the above tally is substantially correct as of the date of this document. Also note that there are spare links available on VRB's C, D, G and I. Also note for reference that the VBD reads out out the VRB's in the following slot order: 19, 9, 10, 11, 12, 13, 16, 17, 18 i.e. in the order of the above list. The reason for this funny VBD readout order is to skip using slot #8 because it does not work reliably. Now examine each card type in detail to understand what data comes from each card. Note that the Header and Trailer formats are only described in detail for the TRM; they are identical for all card types (but see the Hardware Qualifier section above). Again, there may be minor modifications in the following data, but it is substantially correct as of the date of writing. Also note that not all cards currently provide 2 guaranteed sensible words from each FPGA, e.g. the AONM modules provide only 1 word per FPGA and the second word read out may be 0x0000 or 0xffff or..... 0. Common Word Formats Found on All Cards (Words Sourced by BSF): Word Bits Description ---- ---- ----------- Header Word 0 7:0 Reserved 15:8 Event Number (same on all cards) Header Word 1 15:0 all '0' (reserved for expansion) BSF Data Word 0 15:0 Board Global I/O 15:0 BSF Data Word 1 0 Board Global I/O 16 15:1 all '0' (reserved for expansion) BSF Data Word 2 15:0 P5 I/O 15:0 BSF Data Word 3 0 P5 I/O 16 15:1 all '0' (reserved for expansion) Trailer Word 0 15:0 all '0' (reserved for expansion) Trailer Word 1 7:0 Event Number (same as in Hdr Wd 0) 8 Data Captured 9 Transporting Data 10 Unexpected 2nd Cap w/o Prev Trans 11 Unexpected Transport w/o Capture 12 Unexpected Capture during Transport 13 Unexpected Transport during Transport 14 '0' (reserved for expansion) 15 '0' (reserved for expansion) 1. TRM Readout Structure ----------------- Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 (Rel) Chan 3:0 Output States TRM MSA 1 3 (Rel) Chan 3:0 FIFO Error States TRM MSA 1 4 (Rel) Chan 19:16 Output States TRM MSA 2 5 (Rel) Chan 19:16 FIFO Error States TRM MSA 2 6 (Rel) Chan 35:32 Output States TRM MSA 3 7 (Rel) Chan 35:32 FIFO Error States TRM MSA 3 8 (Rel) Chan 51:48 Output States TRM MSA 4 9 (Rel) Chan 51:48 FIFO Error States TRM MSA 4 10 (Rel) Chan 7:4 Output States TRM MSA 5 11 (Rel) Chan 7:4 FIFO Error States TRM MSA 5 12 (Rel) Chan 23:20 Output States TRM MSA 6 13 (Rel) Chan 23:20 FIFO Error States TRM MSA 6 14 (Rel) Chan 39:36 Output States TRM MSA 7 15 (Rel) Chan 39:36 FIFO Error States TRM MSA 7 16 (Rel) Chan 55:52 Output States TRM MSA 8 17 (Rel) Chan 55:52 FIFO Error States TRM MSA 8 18 (Rel) Chan 11:8 Output States TRM MSA 9 19 (Rel) Chan 11:8 FIFO Error States TRM MSA 9 20 (Rel) Chan 27:24 Output States TRM MSA 10 21 (Rel) Chan 27:24 FIFO Error States TRM MSA 10 22 (Rel) Chan 43:40 Output States TRM MSA 11 23 (Rel) Chan 43:40 FIFO Error States TRM MSA 11 24 (Rel) Chan 59:56 Output States TRM MSA 12 25 (Rel) Chan 59:56 FIFO Error States TRM MSA 12 26 (Rel) Chan 15:12 Output States TRM MSA 13 27 (Rel) Chan 15:12 FIFO Error States TRM MSA 13 28 (Rel) Chan 31:28 Output States TRM MSA 14 29 (Rel) Chan 31:28 FIFO Error States TRM MSA 14 30 (Rel) Chan 47:44 Output States TRM MSA 15 31 (Rel) Chan 47:44 FIFO Error States TRM MSA 15 32 (Rel) Chan 63:60 Output States TRM MSA 16 33 (Rel) Chan 63:60 FIFO Error States TRM MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes ----------------- Word Bits Description ---- ---- ----------- Chan Output States 3:0 Chan 3:0 TT - 1 7:4 Chan 3:0 TT 11:8 Chan 3:0 TT + 1 15:12 Chan 3:0 TT + 2 (TT = Triggered Tick) FIFO Error States 0 FIFO Full Error 1 FIFO Empty Error 2 Missing Subsystem Gap Error 3 Unexpected Subsystem Gap Error 8:4 Write Counter 9 Write Counter Resest 14:10 Read Counter 15 Read Counter Reset Note that the FIFO Error States are not yet available in the readout, and this word currently hold a copy of the Channel Output States Word. In other words, the same word is read twice for each FPGA. Additional notes ---------------- The TRM noted with a (2) above performs a slightly different readout: Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 Decorrelated Glb Dsbl 3:0 to TDM TRM MSA 1 3 FIFO Error States for above inputs* TRM MSA 1 4 Decorrelated Glb Dsbl 3:0 to PBS TRM MSA 2 5 FIFO Error States for above inputs* TRM MSA 2 6 Correlated Glb Dsbl 2:0 to TDM TRM MSA 5 7 FIFO Error States for above inputs* TRM MSA 5 8 Correlated Glb Dsbl 2:0 to PBS TRM MSA 6 9 FIFO Error States for above inputs* TRM MSA 6 * FIFO Errors States meaningless, as FIFO not used in this application 10 Static Word 0 TRM MSA 9 11 Static Word 1 TRM MSA 9 12 Static Word 2 TRM MSA 9 13 Static Word 3 TRM MSA 9 14 Static Word 4 TRM MSA 9 15 Static Word 5 TRM MSA 9 16 Static Word 6 TRM MSA 9 17 Static Word 7 TRM MSA 9 18 unused TRM MSA 10 19 unused TRM MSA 10 20 unused TRM MSA 10 21 unused TRM MSA 10 22 unused TRM MSA 10 23 unused TRM MSA 10 24 unused TRM MSA 10 25 unused TRM MSA 10 26 unused TRM MSA 11 27 unused TRM MSA 11 28 unused TRM MSA 11 29 unused TRM MSA 11 30 unused TRM MSA 11 31 unused TRM MSA 11 32 unused TRM MSA 11 33 unused TRM MSA 11 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF 2. TDM Readout Structure ----------------- Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 (Rel) ST 0 States Word 0 TDM MSA 1 3 (Rel) ST 0 States Word 1 TDM MSA 1 4 (Rel) ST 4 States Word 0 TDM MSA 2 5 (Rel) ST 4 States Word 1 TDM MSA 2 6 (Rel) ST 8 States Word 0 TDM MSA 3 7 (Rel) ST 8 States Word 1 TDM MSA 3 8 (Rel) ST 12 States Word 0 TDM MSA 4 9 (Rel) ST 12 States Word 1 TDM MSA 4 10 (Rel) ST 1 States Word 0 TDM MSA 5 11 (Rel) ST 1 States Word 1 TDM MSA 5 12 (Rel) ST 5 States Word 0 TDM MSA 6 13 (Rel) ST 5 States Word 1 TDM MSA 6 14 (Rel) ST 9 States Word 0 TDM MSA 7 15 (Rel) ST 9 States Word 1 TDM MSA 7 16 (Rel) ST 13 States Word 0 TDM MSA 8 17 (Rel) ST 13 States Word 1 TDM MSA 8 18 (Rel) ST 2 States Word 0 TDM MSA 9 19 (Rel) ST 2 States Word 1 TDM MSA 9 20 (Rel) ST 6 States Word 0 TDM MSA 10 21 (Rel) ST 6 States Word 1 TDM MSA 10 22 (Rel) ST 10 States Word 0 TDM MSA 11 23 (Rel) ST 10 States Word 1 TDM MSA 11 24 (Rel) ST 14 States Word 0 TDM MSA 12 25 (Rel) ST 14 States Word 1 TDM MSA 12 26 (Rel) ST 3 States Word 0 TDM MSA 13 27 (Rel) ST 3 States Word 1 TDM MSA 13 28 (Rel) ST 7 States Word 0 TDM MSA 14 29 (Rel) ST 7 States Word 1 TDM MSA 14 30 (Rel) ST 11 States Word 0 TDM MSA 15 31 (Rel) ST 11 States Word 1 TDM MSA 15 32 (Rel) ST 15 States Word 0 TDM MSA 16 33 (Rel) ST 15 States Word 1 TDM MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes (see "Common" section for BSF-sourced word formats) ----------------- Word Bits Description ---- ---- ----------- State Word 0 0 ST Fired TT 1 ST Exposed TT - 1 2 ST Exposed TT + 1 3 And-Or Fired TT - 1 4 And-Or Fired TT + 1 5 Partial AOF Lower TT 6 Partial AOF Upper TT 7 Sel ExpGrp Enb TT - 1 8 Sel ExpGrp Enb TT + 1 9 ExpGrp Part Enb Lower TT 10 ExpGrp Part Enb Upper TT 11 Decorr DAQ Enable TT - 1 12 Decorr DAQ Enable TT 13 Decorr DAQ Enable TT + 1 14 Correl DAQ Enable TT 15 Prescaler Disable TT State Word 1 0 COOR Disable TT 1 Auto Disable TT 3:2 Individual Disable 1:0 TT 4 Sel ExpGrp L1Bz Disbl TT 8:5 Decorr Glb Dsbl 3:0 TT 12:9 Correl Glb Dsbl 3:0 TT 13 Skip Next Tick TT+1 14 Mark and Force Pass TT 15 '0' (reserved for expansion) 3. AONM and FOM Readout Structure ----------------- Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 (Rel) Chan 3:0 Output States AONM/FOM MSA 1 3 Reserved AONM/FOM MSA 1 4 (Rel) Chan 7:4 Output States AONM/FOM MSA 2 5 Reserved AONM/FOM MSA 2 6 (Rel) Chan 11:8 Output States AONM/FOM MSA 3 7 Reserved AONM/FOM MSA 3 8 (Rel) Chan 15:12 Output States AONM/FOM MSA 4 9 Reserved AONM/FOM MSA 4 10 (Rel) Chan 19:16 Output States AONM/FOM MSA 5 11 Reserved AONM/FOM MSA 5 12 (Rel) Chan 23:20 Output States AONM/FOM MSA 6 13 Reserved AONM/FOM MSA 6 14 (Rel) Chan 27:24 Output States AONM/FOM MSA 7 15 Reserved AONM/FOM MSA 7 16 (Rel) Chan 31:28 Output States AONM/FOM MSA 8 17 Reserved AONM/FOM MSA 8 18 (Rel) Chan 35:32 Output States AONM/FOM MSA 9 19 Reserved AONM/FOM MSA 9 20 (Rel) Chan 39:36 Output States AONM/FOM MSA 10 21 Reserved AONM/FOM MSA 10 22 (Rel) Chan 43:40 Output States AONM/FOM MSA 11 23 Reserved AONM/FOM MSA 11 24 (Rel) Chan 47:43 Output States AONM/FOM MSA 12 25 Reserved AONM/FOM MSA 12 26 (Rel) Chan 51:48 Output States AONM/FOM MSA 13 27 Reserved AONM/FOM MSA 13 28 (Rel) Chan 55:52 Output States AONM/FOM MSA 14 29 Reserved AONM/FOM MSA 14 30 (Rel) Chan 59:56 Output States AONM/FOM MSA 15 31 Reserved AONM/FOM MSA 15 32 (Rel) Chan 63:60 Output States AONM/FOM MSA 16 33 Reserved AONM/FOM MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes (see "Common" section for BSF-sourced Word Formats) ----------------- Word Bits Description ---- ---- ----------- Chan Output States 3:0 Chan 3:0 TT - 1 7:4 Chan 3:0 TT 11:8 Chan 3:0 TT + 1 15:12 Chan 3:0 TT + 2 Each odd-numbered "Reserved" word is currently a copy of the preceding even-numbered Output States word. Additional notes ---------------- The AONM's and FOM's noted with a (1) above perform a slightly different readout: Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 Exp Group 3:0 Output States to TDM AONM/FOM MSA 1 3 Reserved AONM/FOM MSA 1 4 Exp Group 7:4 Output States to TDM AONM/FOM MSA 2 5 Reserved AONM/FOM MSA 2 6 Exp Group 3:0 Output States to PBS AONM/FOM MSA 5 7 Reserved AONM/FOM MSA 5 8 Exp Group 7:4 Output States to PBS AONM/FOM MSA 6 9 Reserved AONM/FOM MSA 6 10 (Rel) Input States 15:0 TT-3 Miguel MSA 9 11 (Rel) Input States 31:16 TT-3 Miguel MSA 9 12 (Rel) Input States 15:0 TT-2 Miguel MSA 9 13 (Rel) Input States 31:16 TT-2 Miguel MSA 9 14 (Rel) Input States 47:32 TT-3 Miguel MSA 10 15 (Rel) Input States 63:48 TT-3 Miguel MSA 10 16 (Rel) Input States 47:32 TT-2 Miguel MSA 10 17 (Rel) Input States 63:48 TT-2 Miguel MSA 10 18 (Rel) Input States 79:64 TT-3 Miguel MSA 11 19 (Rel) Input States 95:80 TT-3 Miguel MSA 11 20 (Rel) Input States 79:64 TT-2 Miguel MSA 11 21 (Rel) Input States 95:80 TT-2 Miguel MSA 11 22 (Rel) Input States 111:96 TT-3 Miguel MSA 12 23 (Rel) Input States 127:112 TT-3 Miguel MSA 12 24 (Rel) Input States 111:96 TT-2 Miguel MSA 12 25 (Rel) Input States 127:112 TT-2 Miguel MSA 12 26 (Rel) Input States 15:0 TT Miguel MSA 13 27 (Rel) Input States 31:16 TT Miguel MSA 13 28 (Rel) Input States 47:32 TT Miguel MSA 14 29 (Rel) Input States 63:48 TT Miguel MSA 14 30 (Rel) Input States 79:64 TT Miguel MSA 15 31 (Rel) Input States 95:80 TT Miguel MSA 15 32 (Rel) Input States 111:96 TT Miguel MSA 16 33 (Rel) Input States 127:112 TT Miguel MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF 4. FOM++ Readout Structure ----------------- Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 L1 Qualifier Bits Set 0 3:0 FOMPP MSA 1 3 Reserved FOMPP MSA 1 4 L1 Qualifier Bits Set 0 7:4 FOMPP MSA 2 5 Reserved FOMPP MSA 2 6 L1 Qualifier Bits Set 0 11:8 FOMPP MSA 3 7 Reserved FOMPP MSA 3 8 L1 Qualifier Bits Set 0 15:12 FOMPP MSA 4 9 Reserved FOMPP MSA 4 10 L1 Qualifier Bits Set 1 3:0 FOMPP MSA 5 11 Reserved FOMPP MSA 5 12 L1 Qualifier Bits Set 1 7:4 FOMPP MSA 6 13 Reserved FOMPP MSA 6 14 L1 Qualifier Bits Set 1 11:8 FOMPP MSA 7 15 Reserved FOMPP MSA 7 16 L1 Qualifier Bits Set 1 15:12 FOMPP MSA 8 17 Reserved FOMPP MSA 8 18 Skip Next Tick Output States FOMPP MSA 9 19 Reserved FOMPP MSA 9 20 L1 Accept Strobe Output States FOMPP MSA 10 21 Reserved FOMPP MSA 10 22 Skip Next N Ticks Output States FOMPP MSA 11 23 Reserved FOMPP MSA 11 24 Diag Scal Cont Out States 3:0 FOMPP MSA 12 25 Reserved FOMPP MSA 12 26 ST Fired 15:0 TT Miguel MSA 13 27 ST Fired 31:16 TT Miguel MSA 13 28 ST Fired 47:32 TT Miguel MSA 14 29 ST Fired 63:48 TT Miguel MSA 14 30 ST Fired 79:64 TT Miguel MSA 15 31 ST Fired 95:80 TT Miguel MSA 15 32 ST Fired 111:96 TT Miguel MSA 16 33 ST Fired 127:112 TT Miguel MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes (see "Common" Section for BSF-sourced Word Formats) ----------------- Word Bits Description ---- ---- ----------- Chan Output States 3:0 Chan 3:0 TT - 1 7:4 Chan 3:0 TT 11:8 Chan 3:0 TT + 1 15:12 Chan 3:0 TT + 2 5. GS and TTS Readout Structure ----------------- Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 LSWord for L1 Accept Scaler GS MSA 1 3 MSWord for L1 Accept Scaler GS MSA 1 4 LSWord for L2 Accept Scaler GS MSA 2 5 MSWord for L2 Accept Scaler GS MSA 2 6 LSWord for L2 Decision Scaler GS MSA 3 7 MSWord for L2 Decision Scaler GS MSA 3 8 LSWord for Readout Scaler # 3 GS MSA 4 9 MSWord for Readout Scaler # 3 GS MSA 4 10 LSWord for Readout Scaler # 4 GS MSA 5 11 MSWord for Readout Scaler # 4 GS MSA 5 12 LSWord for Readout Scaler # 5 GS MSA 6 13 MSWord for Readout Scaler # 5 GS MSA 6 14 LSWord for Readout Scaler # 6 GS MSA 7 15 MSWord for Readout Scaler # 6 GS MSA 7 16 LSWord for Readout Scaler # 7 GS MSA 8 17 MSWord for Readout Scaler # 7 GS MSA 8 18 LSWord for Readout Scaler # 8 GS MSA 9 19 MSWord for Readout Scaler # 8 GS MSA 9 20 LSWord for Readout Scaler # 9 GS MSA 10 21 MSWord for Readout Scaler # 9 GS MSA 10 22 LSWord for Readout Scaler #10 GS MSA 11 23 MSWord for Readout Scaler #10 GS MSA 11 24 LSWord for Readout Scaler #11 GS MSA 12 25 MSWord for Readout Scaler #11 GS MSA 12 26 LSWord for Readout Scaler #12 GS MSA 13 27 MSWord for Readout Scaler #12 GS MSA 13 28 LSWord for Readout Scaler #13 GS MSA 14 29 MSWord for Readout Scaler #13 GS MSA 14 30 LSWord for Readout Scaler #14 GS MSA 15 31 MSWord for Readout Scaler #14 GS MSA 15 32 L1AL2 Scaler L1AL2 MSA 16 33 unused L1AL2 MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes (see "Common" Section for BSF-sourced Word Formats) ----------------- Word Bits Description ---- ---- ----------- L1AL2 Scaler 5:0 Number of events with L1A awaiting L2 Decision 15:6 all '0' Additional notes ---------------- The GS FPGA actually has 4x scaler Channels per FPGA, and the GS Card can thus have up to 64 scaler channels (if all sites are populated with GS FPGA). However only one scaler Channel per FPGA is readout. These Channels are thus re-numbered as "Readout Scaler" #0-15 (or in fact #0-14 since site 16 uses a L1AL2 FPGA) The TTS caler Card performs a somewhat different readout: Word (16b) Description Source FPGA ---------- ----------- ----------- 0 Header Word 0 BSF 1 Header Word 1 BSF 2 Unused (Beam X Turn 15:0) TTS MSA 3 3 Unused (Beam X Turn 15:0) TTS MSA 4 4 Unused (Beam X Turn 15:0) TTS MSA 5 5 Unused (Beam X Turn 15:0) TTS MSA 6 6 Unused (Beam X Turn 15:0) TTS MSA 7 7 Unused (Beam X Turn 15:0) TTS MSA 8 8 Unused (Beam X Turn 15:0) TTS MSA 9 9 Unused (Beam X Turn 15:0) TTS MSA 10 10 Beam X Turn 15:0 \ TTS MSA 11 11 Beam X Turn 31:16 | not allocated TTS MSA 11 12 Beam X Tick Num / TTS MSA 11 13 Unused (0x0000) TTS MSA 11 14 Beam X Turn 15:0 \ TTS MSA 12 15 Beam X Turn 31:16 | not allocated TTS MSA 12 16 Beam X Tick Num / TTS MSA 12 17 Unused (0x0000) TTS MSA 12 18 Beam X Turn 15:0 \ TTS MSA 13 19 Beam X Turn 31:16 | not allocated TTS MSA 13 20 Beam X Tick Num / TTS MSA 13 21 Unused (0x0000) TTS MSA 13 22 Beam X Turn 15:0 \ Current BeamX TTS MSA 14 23 Beam X Turn 31:16 | Not Reset TTS MSA 14 24 Beam X Tick Num / By SCL Init TTS MSA 14 25 Unused (0x0000) TTS MSA 14 26 Beam X Turn 15:0 \ Current BeamX TTS MSA 15 27 Beam X Turn 31:16 | Reset TTS MSA 15 28 Beam X Tick Num / By SCL Init TTS MSA 15 29 Unused (0x0000) TTS MSA 15 30 Beam X Turn 15:0 \ L1Accept BeamX TTS MSA 16 31 Beam X Turn 31:16 | Reset TTS MSA 16 32 Beam X Tick Num / By SCL Init TTS MSA 16 33 Unused (0x0000) TTS MSA 16 34 BSF Data Word 0 BSF 35 BSF Data Word 1 BSF 36 BSF Data Word 2 BSF 37 BSF Data Word 3 BSF 38 Trailer Word 0 BSF 39 Trailer Word 1 BSF Word Format Notes (see "Common" Section for BSF-sourced Word Formats) ----------------- Word Bits Description ---- ---- ----------- Tick Number 7:0 Current/Level 1 Tick Number 15:8 all '0' 6. VRB Header Data What the VRB does to the data is moderately complicated, but essentially unimportant for defining unpacked data chunks. It is, however, important for defining the packing and unpacking routine, and for defining raw data chunks. Recall that a VRB services 4 of our cards, but internally it splits each card's 16-bit data up into two 8-bit channels, which are stored SEPARATELY. Recall also that the VRB produces 32-bit wide output (not 16-bits as found in e.g. THE Card. The VRB also adds its own headers and may pad various records with unpredictable data (see the VRB documentation for more details on these aspects of the VRB). The output data stream from the VRB looks like: 8 longwords of VRB header. According to the 8/28/00 spec: 31 24 23 16 15 8 7 0 ----------------------------------------------------------------- 0: | Total Byte Count | ----------------------------------------------------------------- 1: | User Info | Slot Number | Event Number | ----------------------------------------------------------------- 2: | Firmware Version Number | bit 1 = Trig Mode | ----------------------------------------------------------------- 3: | Status Word 1 (TBD) | ----------------------------------------------------------------- 4: | Channel 0 Byte Count | Channel 1 Byte Count | ----------------------------------------------------------------- 5: | Channel 2 Byte Count | Channel 3 Byte Count | ----------------------------------------------------------------- 6: | Channel 4 Byte Count | Channel 5 Byte Count | ----------------------------------------------------------------- 7: | Channel 6 Byte Count | Channel 7 Byte Count | ----------------------------------------------------------------- longwords of Channel 0 event data (i.e. the LSByte of the data from the card on Link 0, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 1 event data (i.e. the MSByte of the data from the card on Link 0, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 2 event data (i.e. the LSByte of the data from the card on Link 1, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 3 event data (i.e. the MSByte of the data from the card on Link 1, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 4 event data (i.e. the LSByte of the data from the card on Link 2, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 5 event data (i.e. the MSByte of the data from the card on Link 2, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 6 event data (i.e. the LSByte of the data from the card on Link 3, 4 bytes packed per word, padded to a TWO LONGWORD boundary) longwords of Channel 7 event data (i.e. the MSByte of the data from the card on Link 3, 4 bytes packed per word, padded to a TWO LONGWORD boundary) 7. Current draft collection of special TCC-controlled information Data Types ---------- All VBD Header Trailer data and all VRB Header data is defined in terms of 32 bit longwords as are described in the documents for these two cards. All THE-Card data is described in terms of 16 bit words, i.e. after this data has been put back together from the shuffling it receives going through the VRB cards. All THE-Cards produce a total of 40 words, a 2 word BSF Header, 32 words from the Main Array FPGA's, 4 BSF Data words, and a 2 word BSF Trailer. Types of Fixed Data ------------------- There are three different types of locations where TCC loaded event to event fixed data can be transported in the Trigger Framework Data Block. These are: The SHED's - one instance for the whole Data Block VRB User Info - an instance for each of the 9 VRB's BSF Header/Trailer - an instance for each THE-Card readout by a VRB Of these three locations you can only find the VRB User Info without knowing the detailed structure of the data block. Only the VRB User Info from the first VRB (normally VRB in slot #19) is guaranteed to be in a fixed location. SHED Data --------- The SHED data should be information that pertains to the whole Trig FW Data Block. It must not be information that is needed to decode the Data Block (i.e. navigate to the SHED data) SHED's will be located on the Global Disable TRM card. We could have up to 12 SHED's in the Main Array FPGA area of this card but this is not the most useful way to use the FPGA resources on this card. Each SHED can provide up to 8 words of HSRO readout - so we could have as few as 3 SHED FPGA's on this card and provide the maximum amount of data that we can transport. To keep things a bit more symmetric 4 SHED's will be used in the initial implementation. The 4 TRM FPGA sites that are used on the Global Disable TRM are FPGA sites: 1, 2, 5, 6. The 4 SHED's used in this initial implementation will be located at the FPGA sites that have the hardest to access electrical connections. These are Main Array Sites: 3, 4, 7, 8. Each of these "official" SHED's will produce 2 words of data. For now the remaining 8 sites (9:16) will also be loaded with SHED's. This is being done just for convienience and to prevent skipping any FPGA's during readout. In a future implementation some of these FPGA sites could be loaded with something other than SHED's. Most likely if we need some different functionality we would start at site 16 and work backwards. If we need more SHED data then we will start at site 9 and work forwards. We will read 2 words from each of the 16 main array FPGA's on this card. "SHED Info 1st Word" comes from FPGA site 3 SHED Data Register 0 "SHED Info 2nd Word" comes from FPGA site 3 SHED Data Register 1 "SHED Info 3rd Word" comes from FPGA site 4 SHED Data Register 0 "SHED Info 4th Word" comes from FPGA site 4 SHED Data Register 1 "SHED Info 5th Word" comes from FPGA site 7 SHED Data Register 0 "SHED Info 6th Word" comes from FPGA site 7 SHED Data Register 1 "SHED Info 7th Word" comes from FPGA site 8 SHED Data Register 0 "SHED Info 8th Word" comes from FPGA site 8 SHED Data Register 1 SHED Info 1st Word MSByte TRICS Version compound of two fields MSNibble Major Version ID (0:15) MSNibble Minor Version ID (0:15) LSByte TRICS Revision ID (0:255) The Revision ID is typically expressed as an uppercase letter (0=A, 1=B,... 25=Z) SHED Info 2nd Word Word of "Operating State Information" e.g. Is L2 FW in bypass mode, ... SHED Info 3rd & 4th Words 32 bit long "Luminosity Index" SHED Info 5th Word version - revision of the BSF FPGA used by the 4028XL's SHED Info 6th Word version - revision of the BSF FPGA used by the 4036XLA's SHED Info 7th Word reserved currently not used SHED Info 8th Word reserved currently not used VRB User Info Data ------------------ The VRB User Information is in the upper 16 bits of the 2nd long word of the VRB Header. The 16 bits of data presented in the header is just an echo of what is written by TCC in the VRB's User Info register. MSNibble - Slot Number that this VRB is in. The value written here is the actual slot number minus 8. Nibble - Trig FW Data Block Version 0:15 LSByte - Trig FW Data Block Revision 0:255 The VRB slot number is repeated in the VRB User Info Data just to verify that TCC is programming the proper VRB. As an example decimal slot 18 will appear in the MSNibble of the User Info as $A. Upon readout the VRB hardware provides its slot number in bits 15:8 of the 2nd longword of the VRB Header. The VRB hardware provides the slot number as a 2 digit hex number. So for example decimal slot 18 appears in readout as $12. The Trig FW Data Block version.revision is provided in the VRB User Info so that it can be found without needing to decode any data from THE-Cards. Once you have the Trig FW Data Block version.revision then this can help you to decode data from THE-Cards. It is repeated in each VRB but that was the price that had to be paid to get this information into a fixed known location. In general the Trig FW Data Block version number will change only when something major changes, e.g. the number of VRB's or the number of THE-Cards sending data to a VRB. The revision number will change when the meaning of existing data in the Data Block changes. The other very useful piece of information that we considered putting in the VRB User Info was the number of THE-Cards that are sending data to this VRB. Knowledge of how many THE-Cards send data to this VRB instead comes from knowing the Trig Data Block version.revision number. BSF Header/Trailer Data ----------------------- Each THE-Card that provides HSRO data provides BSF Header Trailer data. We use the TCC writable sections of the BSF Header Trailer to provide information about the specific THE-Card that this data comes from. BSF Header Word 0 LSByte The information stored here by TCC tells us which THE-Card this data comes from. This can be used to verify that the fiber optic cables are plugged into the correct places. The format for this data is: Bit 7 Vertical Master Number (0 = M122, 1 = M123) Bit 6:5 Vertical Slave Number (0 = Top, 1 = Middle, 2 = Bottom) Bit 4:0 THE-Card Slot Number (2:21) BSF Header Word 1 Most prominent Main Array FPGA Version.Revision readout on this THE-Card. MSByte - Version 0:255 LSByte - Revision 0:255 BSF Trailer Word 0 Two ideas: Reserved for future use or Next to Most prominent Main Array FPGA Version.Revision readout on this THE-Card. MSByte - Version 0:255 LSByte - Revision 0:255 None of our current uses of THE-Card have more than two types of FPGA's in their Main Array. Let's start with the latter, and leave the option open of reclaiming this field later on.