VRB Notes ------------- Initial Version: 24-AUG-1998 Most Recent Version: 11-SEP-2000 This file is our notes from working with the VRB and its G-Link Transition Module. As we received it: S1 is all ON S2 is all OFF S3 is all ON EXCEPT for key #3 which is OFF Front panel RJ? connector - estimate of its pin out: Think pin #1 is closest to the top pin #1 n.c. pin #2 goes to pin 5 on U103 MAX233CPP this is output from the VRB pin #3 GND pin #4 GND pin #5 goes to pin 4 on U103 MAX233CPP this is input to the VRB pin #6 n.c. How the Geographic Addressing works: Slot Number GA0* GA1* GA2* GA3* GA4* ------ ---- ---- ---- ---- ---- 1 gnd 2 gnd 3 gnd gnd 4 gnd 5 gnd gnd So with the VRB in Slot #18 it appears in the address range $0012 0000 through $0012 3FFF In Slot #19, the address range starts at $ 0013 0000. Recall that the MVME-133-A20 VME CPU module does not see VME address space below $0010 0000 Getting It To Work ------------------ According to the VRB documentation, S3 should actually be set differently: S3-8 off, S3-7 on, S3-6 on, S3-5 on, and the remainder of S3 should be off. NOTE - when a switch is OFF the corresponding bit in the VME register is HIGH. Also according to the documentation, Gray code enable should be off by default. This does not appear to be the case. However, the other registers do seem to agree with their described default states. The initial state of the status registers is 0x0043. Since all of these signals are active low, that corresponds to VRB Error, Format Error, ID Error, Frame Error, and Synch Error. In the documentation, it is unclear exactly how many of these signals are actually connected properly; Synch Error, Scan Busy, and Readout Busy are the only signals which are definitely implemented at the moment. IMPORTANT NOTES: In contradiction to the documentation, Synch Error is active high. When the module is synchronized, the status register typically reads 0x43. When synchronization is lost, the register typically reads 0x47. Also note that for each channel, C0 to CF are viewed as an end of record signals. To initialize the module, clear the Gray code enable and enable the desired channels by writing to the appropriate registers. Emulation mode may also be activated at this time. In emulation mode, a 256 byte incrementing pattern is generated in place of the input data. The pattern increments from 00 to 7f and is the same in both halves of each 16 bit data word. After generation, the emulated data seems to follow the same path through the VRB as the real inputs so this is useful for testing. The VRB must be reset before any of these changes to the configuration will be implemented. Writing a 0 to the reset register is sufficient. To get the data from the input FIFO to the buffer: write the buffer number (at which point the Readout Busy flag should go low) write the beam crossing number (at which point the readout actually happens) When the readout busy flag goes low, the Scan Busy flag and Controller Error appear to follow. This is not expected and is not understood. Furthermore, the latched version of the status bits doesn't seem to pick up either the Readout Busy flag or the Scan Busy flag. To get the data from the buffer to the output FIFO: write the buffer number (the Scan Busy flag goes low) write the event number (the scan actually happens) The Readout Busy flag remains high throughout the scan as expected. Once the event is in the output FIFO, the Scan Byte Count can be read from the register and the event can be readout from the FIFO via VME. Block transfers from the FIFO are not necessary, and the FIFO can be read using single 16 or 32 bit transfers. It is important, however, that only the data from the FIFO is read. (By default the debugger reads 8 words from consecutive addresses, and this may confuse the VRB.) Step-By-Step Readout -------------------- 1. disable Gray code register 0x74 write 0x0000 2. enable channel(s) register 0x70 write 0x01 to 0xff 3. reset VRB register 0x3c write 0x0 or 0x1 (1 to reset VTM also) 4. begin HSRO readout 5. move data from input register 0x22 write buffer number FIFO to buffer register 0x26 write BX number 6. move data from buffer register 0x28 write buffer number to output FIFO register 0x2a write event number ( check byte count register 0x30 read 16 bit word) 7. read output FIFO register 0x10 read 32 bit long word Notes about G-link receiver (on VTM) ------------------------------------ The G-link receiver has several outputs associated with the current status of the Rx State Machine Controller. They are: ERROR: Goes HIGH when an invalid C-field is detected. I assume "invalid C-field" means "master transition not in the correct place" although there may be other invalid C-fields with a correct master transition. Also when FLAGSEL is low, ERROR indicates that the FLAG bit was seen in the wrong state (must alternate HIGH/LOW on successive DATA frames) ERROR is NOT latched, but only indicates the status of the current frame. So, let's take ERROR to mean "this frame did not have a master transition in the correct place." This signal is passed from the VTM to the VRB. It may be used in making the SYNC_ERROR* (stat2) signal in the VRB Current Status Register. STAT1: Goes LOW at either RESET (SMCRST0* or SMCRST1* LOW) or on loss of frame sync. NOTE: loss of frame sync = "ERROR" asserted for TWO CONSECUTIVE FRAMES. Goes HIGH after Rx SMC has "frequency locked" to the FF0 pattern. NOTE: once STAT1 goes LOW, it stays LOW for at least 128 CONSECUTIVE FRAMES. This signal is therefore LOW when Rx SMC is in State 0, HIGH when Rx SMC is in State 1 or State 2. This signal is NOT passed from the VTM to the VRB. STAT0: Goes LOW at either RESET or loss of frame sync (see above note) Goes HIGH after Rx SMC has "phase locked" to the FF1 pattern (see above note). This signal is LOW when Rx SMC is in State 0 or State 1, HIGH when Rx SMC is in State 2. This signal is NOT passed from the VTM to the VRB. LNKRDY*: Active LOW. Goes HIGH when Rx SMC is in State 0, goes LOW when Rx SMC is in State 1 or 2. Note the "low pass filter" effect between ERROR and LNKRDY*. This signal is passed from the VTM to the VRB. It may be used in making the SYNC_ERROR* (stat2) signal in the VRB Current Status Register. The G-link receiver only receives a single input from the VRB: SMCRST1*: Take this signal LOW to force the Rx SMC to State 0. Take this signal HIGH to allow the Rx SMC to operate. (note: on the prototype VTM, we have added an additional RESET in the form of a pushbutton switch. This switch does not interfere with the RESET input from the VRB: +5V | 10K pullup | RESET* from VRB ------------+------------ SMCRST1* | momentary switch | GND Additionally, three inputs are set by jumpers on the VTM (jumper IN = LOGIC 0 [corresponding LED will be OFF]): DIV0/DIV1: Set the input data rate. With our 50 or 53 MHz accelerator clock, we want DIV0 and DIV1 both LOW (sets HIGHEST data rate). M20SEL: Choose 16/20 bit data. We want 16 bit data, so M20SEL should be LOW i.e. ALL jumpers should be IN (all LED's should be OFF). Note that the VTM uses the TTL I/O version of the G-link receiver (HDMP-1024). Note also that the VTM schematic we have does not match the VTM we have (specifically, no PIC chip). Notes from VRB testing: ---------------------- 0. The VRB handles the 2 8-bit halves of our 16-bit data as separate channels. This complicates our readout, as our 16-bit values are split up in the output FIFO. 1. If the (8-bit) data for any VRB channel contains the data Cx (x = 0-f), that VRB channel will quit filling its input FIFO. The other channel on the same G-link media will NOT quit filling its input FIFO. For now, our "counter data" wraps (each half) at BF. 2. If we send an odd number of 16-bit words to the VRB, the byte count for each channel is rounded to the next higher even number, and the last byte for each channel is repeated in the output FIFO. 3. The FIRST 32-bit longword in the output FIFO for each channel (which reflects the first 4 bytes of data for that channel) look funny in the readout. The funniness is correlated with the word count, the data you see is nearly (but not quite) OR-ed with the word count. This doesn't always appear to happen. Only the FIRST longword for each channel appears to be affected. Looking at the data on the VTM with the logic analyzer, it looks OK. 4. It is OK to provide the BX/buffer number for moving data into the readout buffer before providing data to the input FIFO. 5. In the output FIFO, the data for each channel is padded to an 8-byte boundary. The "channel byte count" does NOT reflect this padding. The "overall word count" does reflect this padding. 1-DEC-1998 Working with the VRB since Ted Zmuda repaired it and updated its firmware. It wakes up OK, i.e. yellow LED next to the top came ON and a terminal connected to the front port said VRB Ready, but we have no VME access to it. Find that we now need to have S3 key #8 set ON. So the setup of all three switches is: S1 all ON, S2 all OFF, S3 keys 1,2,3,4 OFF, and S3 keys 5,6,7,8 ON. 9-DEC-1998 The VRB that we have been using since summer was returned to us today. Ted had it to look at a "timing problem" that they had discovered on another one of the proto-type VRB's. We think/hope that this will fix the errors in VRB channels 0,1,2 i.e. G-Link channels 0 (and 1?). As returned to us switch S3 is set: 1,2 ON, 3,4 OFF, 5,6,7,8 ON. I was surprised to find keys #1,2 ON. But looking at the documentation it is not clear which way these should be set to protect the Flash Memory. In some places S3 keys #1,2 are called write protect and some places they are called write enable. 3-March-1999 Changes that we need/that we would like --------------------------------------- 1) we need some other way to indicate the end of event it must be out of band and on the same optical cable - we would prefer some pattern of bits with CAV* (rather than DAV*) 2) since we do not send two channels on the same optical cable, we would prefer that the VRB not separate the data 3) maybe we care about the extra padding: o even number of bytes for a channel (last byte repeated in output FIFO if necessary) although if the data is no longer separated into two 8 bit channels, we will always be sending an even number of bytes so this goes away o channel data increased to the next 8 byte boundary this is reflected only in the overall word count and not in channel byte count 12-April-1999 After temporarily switching S3-1,2 off, the VRB ceased to function. Possibly the flash memory was erased. It seems that S3-1,2 ON is the preferred setting at this point. 19-APR-1999 From Ted Zmuda, clarification of the Flash RAM Write Enable switches: The settings for S3-1,2 are as follows: write enable = 1 = switch is off, write protect = 0 = switch is on. And also from Ted, the D0 header format has changed. The info on the web as of 19-Apr-1999 (dated 12/10/98) is now incorrect. The new header format is as follows: 31 24 23 16 15 8 7 0 0000000000000000 total byte count 0000000000000000 00000000 event number status word 0 (TBD) status word 1 (TBD) channel 0 byte count channel 1 byte count channel 2 byte count channel 3 byte count channel 4 byte count channel 5 byte count channel 6 byte count channel 7 byte count Note that the first longword has been divided into two longwords, and the total header length has increased to 8 (rather than 7) longwords. ........................................................................ 30-JUNE-2000 DRAFT This section describes how we will need to setup and operate the G-Link on our THE-Cards for them to function correctly with the FIC and the D-Zero Trigger mode VRB's. Currently this is just a draft version of this specification. This section will be updated as needed. Background material for this comes from: For the FIC http://www.pa.msu.edu/hep/d0/ftp/l2/data_transfer/fic_specs_draft2.pdf Which is from 15-JAN-1999. For the FIC G-Link is setup to transport 20 bit frames of user data (24 bit G-Link symbols). Quoting from the FIC Document (page 9) Bit 16 is used to signal the beginning of the event data. It should be present with the first data word of an event. Bit 17 is used to signal the end of the event data. It should be present with the last data word of the current event. This appears to match what Manual Martin has on page 10 of his protocol stuff. This is from July 1999 and is labeled final version after the 1999 workshop. d0Server1.fnal.gov/users/manuel/Protocols/final_general.pdf Executive Summary of how we need to setup and operate G-Link on THE-Card. The G-Link is setup for 20 bits of user data (24 bit G-Link symbols). All of our data that will be readout from the VRB is sent to it on G-Link Bits D15:D0. The first word of each event needs to have bit D16 asserted and bits D19, D18, D17 negated. This is used only by FIC. All of the words that we send out except for the first word of each event and the last word of each event need to have bit D18 asserted and bits D19, D17, D16 negated. This is used only by FIC. The last word of each event needs to have bit D17 asserted and bits D19, D18, D16 negated. This is used by both FIC and the VRB. --> Still under discussion is whether we will need to mark the last word of each event with bits D19, D17 asserted and bits D18, D16 negated. This would be to allow both VRB Channels that service a G-Link to see the end of event marker. --> Still under discussion is whether we will need to send an even number of words in each event, or some mod 4 number to pack the VME readout to an integer number of 32 bit long words. --> The VRB will split our 16 bit data into byte wide Channels and then on VME first readout all the low bytes and then readout all the high bytes. Slot Arrangement 6-July-2000 ---------------- No written documentation, but according to Daniel Mendoza: Bus Arbitrator Slot 1 VRB Slots 13:10, 20:15 plus 8, 9 and 21 if needed VRBC Slot 14 VBD Slot 4 Repeater any slot, ours is in Slot 5 (takes data from VBD to L3) Useful URLs 6-July-2000 ----------- www-ese.fnal.gov/SVX/Production/SVX_Web/VRB/VRBsystem.html links for VRB, VFO, VTM which include the schematics www-ese.fnal.gov/eseproj/index/svxii/svxii_family.htm a link to the VRB Module Specification (the text documentation)