!  This is the  Test 1  version of the Default Init  for Dave FPGA

!                                             Rev. Date 11-APR-2002

Register_Address: 0
     Write_Value: 0x0000        ! Chip CSR 0


Register_Address: 10            ! Test Data Register
     Write_Value: 0x0000        ! Load zero into Test Data Register

Register_Address: 11            ! Input Data Selector Control
     Write_Value: 0x0100        ! Select the Test Data Register


Register_Address: 31            ! Output Control Register
     Write_Value: 0x0000        !   Select the Individual Disable signals for output
                                !   Do not assert any of the 4 Individual Disables
                                !   Do not allow the Global Disable to "OR" into
                                !   any of the 4 Individual Disables.


Register_Address: 40            ! Control Section #0 Control Register
     Write_Value: 0x0000        !   Disable: everything

Register_Address: 41            ! Control Section #1 Control Register
     Write_Value: 0x0040        !   Set Reference to the FIFO Almost-Full
                                !   Comparator to $40.  Do not allow the
                                !   FIFO Almost-Full Comparator to assert
                                !   Glb_L3_Disable.  Do not assert 
                                !   Glb_L3_Dis.

Register_Address: 42            ! Control Section #2 Control Register
     Write_Value: 0x0050        !   Set Reference to the FIFO Too-Full
                                !   Comparator to $50.  Do not allow the
                                !   FIFO Too-Full Comparator to assert
                                !