DAVE FPGA L3 <-> TFW Control Path Interface ----------------------------------- Original Rev. 23-JAN-2002 Current Rev. 8-APR-2002 The current version of this document is in the directory: http://www.pa.msu.edu/hep/d0/ftp/l1/framework/l3_interface/ The DAVE FPGA is unsed to implement the L3 <-> TFW Control Path Interface. The Control Path Interface allows the L3 RM processor to: Set the L3_Disable signals, that go to the TFW, by writting to VME register locations and to Read the Mask of L1 Fired AND L2 Accepted Triggers along with its associated L3 Transfer Number by reading from VME registers on the L3 side of a 128 location deep FIFO. Event data is written into the FIFO by the TFW. The DAVE FPGA is used in the 16 MSA locations of "Build A" AONM module THE_Cards (4013L in the MSA) along with a standard BSF (now 4036XLA on Build A AONM's) to implement the L3 <-> TFW Control Path Interface. Each Control Path Interface FPGA consists of 4 main sections: Input Data Selector (multiplexer) Section Input Data FIFO Section to obtain the Trigger Mask and L3 Transfer Number Output Section i.e. registers and logic to control the L3_Disable signals Control and Error Detection sections #1 and #2. As is normal with our FPGA design, each DAVE FPGA will contain all of these sections but the Control and Error Detection sections will only be activated on two of the DAVE FPGA's. Input Data Selector Section is a multiplexer that allows you to select the 16 bit wide source of data that is the input to the FIFO on a given FPGA. You can also select a test data register as the input to the FIFO. The Input Data FIFO on each DAVE FPGA, FIFO's the selected 16 bits of input data to a depth of 128 locations, and makes the output of the FIFO available in a read register. Thus only 8 of the 16 MSA FPGA's on a AONM will need to use this section. To receive both the Trigger Mask and its associated L3 Transfer Number 2 AONM cards are used. The Output Section on each DAVE can only drive 4 MSA_Out lines (the AONM card is what we have available for use in the Control Path Interface). So all MSA locations on 2 AONM cards are required to generate the 128 L3_Disable signal. The Control and Error Detection section is activated on only two DAVE FPGA's on the AONM card in slot 5. The first of these two "Control DAVE's", instead of having 4 L3_Disable outputs will have 4 control signal outputs. These are wrapped around from the MSA_Output of this AONM card to the P1_Timing_Signal inputs of the TOM card in slot 1 from where they are driven onto the backplane bus that goes to all slots and thus these signal are made available to all DAVE FPGA's. These 4 control signals are: Reset_Write_Pointer, FIFO_Write_Enable, Increment_Read_Pointer, and Reset_Read_Pointer. The second of the two "Control DAVE's", instead of having 4 L3_Disable outputs will have the Global_L3_Disable output which is wrapped around from the MSA_Output of this AONM card to the P1_Timing_Signal input of the TOM card in slot 1 and thus made available to all DAVE FPGA's. On the cards in slots 7 and 9, this Global_L3_ Disable signal can be controllably "ORed" with the Individual L3 Disable signals that are generated by the DAVE FPGA's on these cards. The only other P1_Timing_Signals that are used by any of the DAVE's is P1_TS_1 the Tick_Clk (132 nsec). This is the basic clock for sequencing the operation of the DAVE. Function of the DAVE FPGA's in slot 5 MSA Slot FPGA Number Number MSA_FPGA Functions ------ ------ ------------------------------------ 5 1 Front Panel outputs 4 Control Signals 5 2 Front Panel outputs 4 Control Signals 5 3:16 not used. Function of the DAVE FPGA's in slot 7 MSA MSA_FPGA Functions Slot FPGA --------------------------------------------------- Number Number Read from FIFO Output Register ------ ------ --------------------------- ------------------- 7 1 Read Trigger Mask 15:0 L3 Disable 3:0 2 Read Trigger Mask 31:16 L3 Disable 7:4 3 Read Trigger Mask 47:32 L3 Disable 11:8 4 Read Trigger Mask 63:48 L3 Disable 15:12 5 Read Trigger Mask 79:64 L3 Disable 19:16 6 Read Trigger Mask 95:80 L3 Disable 23:20 7 Read Trigger Mask 111:96 L3 Disable 27:24 8 Read Trigger Mask 127:112 L3 Disable 31:28 9 Read - not used - L3 Disable 35:32 10 Read - not used - L3 Disable 39:36 11 Read - not used - L3 Disable 43:40 12 Read - not used - L3 Disable 47:44 13 Read - not used - L3 Disable 51:48 14 Read - not used - L3 Disable 55:52 15 Read - not used - L3 Disable 59:56 16 Read - not used - L3 Disable 63:60 Function of the DAVE FPGA's in slot 9 MSA MSA_FPGA Functions Slot FPGA --------------------------------------------------- Number Number Read from FIFO Output Register ------ ------ --------------------------- ------------------- 9 1 Level 3 Transfer Number 15:0 L3 Disable 67:64 2 Read - not used - L3 Disable 71:68 3 Read - not used - L3 Disable 75:72 4 Read - not used - L3 Disable 79:76 5 Read - not used - L3 Disable 83:80 6 Read - not used - L3 Disable 87:84 7 Read - not used - L3 Disable 91:88 8 Read - not used - L3 Disable 95:92 9 Read - not used - L3 Disable 99:96 10 Read - not used - L3 Disable 103:100 11 Read - not used - L3 Disable 107:104 12 Read - not used - L3 Disable 111:108 13 Read - not used - L3 Disable 115:112 14 Read - not used - L3 Disable 119:116 15 Read - not used - L3 Disable 123:120 16 Read - not used - L3 Disable 127:124 Operation of the Control Path Interface --------------------------------------- Configuring Configuration refers to loading the logic into the FPGA's. For now this will be taken care of by TCC. In the near future information will be included in the document about how to do this. Code will be made available to do this. Configuration is only required after power up. We have not problems about configuration being lost once the FPGA's have been configured. The same DAVE FPGA design is configured into all 16 Main_Signal_Array FPGA's on each of the 3 AONM THE_Cards. The MSA FPGA's are FPGA number 1:16. A different FPGA design called Board_Support_Functions is configured into FPGA number 17 on each of the cards. Initialization Initializing refers to loading values into the various control registers that exist in the DAVE FPGA's once they are configured. This process is done in a specific order so that no matter what state the system has gotten into by the end of the Initialization process it is: recovered, in a known state, and ready for use. Different DAVE FPGA's typically have different values loaded into some of their registers, e.g. to select which block of input signals a given FPGA will FIFO, or to select the DAVE FPGA's that will generate the Control signals and do the error detection. FIFO Write Operation A FIFO Write can be caused by setting a bit in a register or by setting a different bit in a control register that enables the New Event Data Strobe signal from the Trigger Framework to cause a FIFO Write. In either case the input data is written into the FIFO location currently being pointed to and then the Write Pointer is incremented. FIFO Read Service Routine To make things rational the sequence for reading from this system need to be: look to see how many reads to make (i.e. read the Pointer Difference Register) then repeat for the required number of times: Read FIFO output registers Increment the FIFO Read Pointer It sounds funny, but the last step is Incrementing the FIFO Read Pointer to get it ready for the next time you want to read from the FIFO. Doing things in this order (i.e. Read FIFO data and then Increment the Read Pointer) makes the read operation match the write operation so that you do not need to do anything special to get started or to get the last piece of data out of the FIFO. Generation and Use of the Global_L3_Disable Signal The only disable signals that are carried on the Control Path from L3 to the TFW are the 128 Individual Trigger Disables. But in the logic in the DAVE FPGA that generates the Individual_L3_Disables you may select to "OR in" a Global_L3_Disable signal. Recall that these Individua_L3_Disable signals stop the TFW from issuing L1_Accepts - they do not directly stop it from issuing L2_Decisions that are already in the pipeline. A given Individual_L3_Disable can be asserted either: because you have set a bit in a control register that forces it asserted or because you have set a different bit in a control register that enables the Global_L3_Disable signal to "OR into" this Individual_ L3_Disable AND the Global_L3_Disable is currently asserted. The Global_L3_Disable can be asserted either: because you have set a bit in a control regester that forces it asserted or because you have set a different bit in a control register that enables the FIFO_Almost_Full_Comparator's output to assert Global_L3_Disable AND currently this Comparator's output is asserted. The FIFO_Almost_Full_Comparator looks at how many locations in the Input FIFO are currently holding data that has not been readout and if this value exceeds some reference value then this Comparator's output is asserted. The reference value for this comparator can be set by a register. In normal operation the Individual_L3_Disables will be setup so that when Global_L3_Disable is asserted then they are asserted. Global_L3_Disable will be setup so that when the FIFO_Almost_Full_ Comparator output is asseted then Global_L3_Disable is asserted. The reference value for the FIFO_Almost_Full_Comparator will be something like 100, i.e. up to 100 events may be written into the FIFO before this Comparator's output is asseted and thus all 128 of the Individual_L3_Disables are asseted. The instant that the Individual_L3_Disables are asserted the TFW will stop issuing L1_Accepts. But recall that there could still be up to 16 L2_Decisions in the pipeline and thus even though the TFW has stopped issuing L1_Accepts there could still be up to 16 additional Writes into the FIFO (if all the L2_Decisions were L2_Acpt's). But that is OK because we chose to assert Global_L3 Disable when we still had room in the FIFO for 27 more events. In this example with a FIFO_Almost_Full_Comparator reference value of 100, Writes to the FIFO are guaranteed to stop with room in the FIFO for 10 more events. This is the primary mechanism that is used to prevent the Input Data FIFO's from overflowing. Detection of Error Conditions The primary error condition that can be detected is that the Input FIFO is getting "Too-Full". This condition is detected in MSA FPGA #1 on the card in slot #5. It is detected by a comparator that looks at how many FIFO locations have been written that have not yet been read. If this value exceeds the reference value for the FIFO Too-Full Comparator then the FIFO Too-Full Flag will be set. The FIFO Too-Full Flag can only be cleared by cycling a bit in Register 42 from low to hi and back to low. When the FIFO Too-Full Flag is asserted, it can be used to block all further writes to the Input FIFO. The details about how this works are given in the Control and Error Detection Section description below. During normal operation, with proper reference values for the FIFO Almost-Full and FIFO Too-Full Comparators, the FIFO Too-Full Flag should never be set. Generation of Interrupts During normal operation, when the Read and Write FIFO Pointers are not equal, this means that data has been written into the Input FIFO that has not been readout. The condition of the FIFO Pointers not being equal can be enabled to set a VME Interrupt. Normally when exiting the FIFO Read Data Service Routing the FIFO Pointers will once again be equal (i.e. the routine will have read all the data that had been written into the Input FIFO). Details about how to operate this interrupt facility will be added soon. Summary of the Registers in the DAVE FPGA ----------------------------------------- Register Address Function -------- ------------------------------------------------------------ 0 Chip Control Status Reg Control Interrupt R/W, R-Only 10 Input Data Selector Test Data R/W 11 Input Data Selector Selector Control R/W 12 Input Data Selector Read Selected Data R-Only 20 Input Data FIFO Section Read FIFO Output Data R-Only 21 Input Data FIFO Section Read FIFO Pointers R-Only 22 Input Data FIFO Section Read Pointer Difference R-Only 30 Output Section Output Data Readback R-Only 31 Output Section Output Control Register R/W 40 Control - Error Reg 0 Control FIFO Pointer Counters R/W 41 Control - Error Reg 1 FIFO Almost-Full, L3_Glb_Dis R/W 42 Control - Error Reg 2 FIFO Too-Full, Blk FIFO Wrt R/W,R-Only Note the convention that all numbers are in decimal unless marked with 0x or $ for hex. Typically Register Addresses and bits with in a register are identified in decimal. The contesnts of a register are typically represented in hex. Details of the Input Data Selector Section ------------------------------------------ This section selects which 16 bits of the 128 bits input by each THE-Card a given FPGA will use as the input to its 16 bit wide 128 step long FIFO. There is also the option of selecting the contents of a Test Data Register as the input to the FIFO. There are three registers in the Input Data Selector Section. Test Data Register Read/Write Register Address = 10 Bits Function ----- --------------------------------------------- 15:0 Test Data bits 15:0 that can be selected as the input to the FIFO. During testing this register can be used to load known data into the FIFO. For normal operation this register is not used and can be loaded with "0's". Input Selector Control Register Read/Write Register Address = 11 Bit Function --- --------------------------------------------- 2:0 These three bits control which 16 bits of the 128 bits MSA_Input data is available for input to the FIFO on this Dave FPGA. The ordering is the straight obvious order. Bits 2:0 Selects MSA_Input Block --- ------------------------- 000 MSA_Input_15:0 001 MSA_Input_31:16 010 MSA_Input_47:32 011 MSA_Input_63:48 100 MSA_Input_79:64 101 MSA_Input_95:64 110 MSA_Input_111:80 111 MSA_Input_127:112 3 not used - readback as written 4 not used - readback as written 5 not used - readback as written 6 not used - readback as written 7 not used - readback as written 8 A "1" selects the current contents of the Test Data Register as the input to the FIFO. A "0" selects the MSA_Input data. 9 not used - readback as written 10 not used - readback as written 11 not used - readback as written 12 not used - readback as written 13 not used - readback as written 14 not used - readback as written 15 not used - readback as written For the 32 Dave FPGA's in slots 7 and 9, their Input Data Selector Control Register bits 2:0 are set equal to their FPGA Site Number. Bit 8 is set to "0" for normal operation and can be set to "1" for loading data from the Test Data Register into the FIFO. For the 2 Dave FPGA's in slot 5 the Input Data Selector Section is not really used and both of these registers can be loaded with "0's". Read Selected Data Register Read Only Register Address = 12 Bits Function ----- --------------------------------------------- 15:0 Show the 16 bits (15:0) that are currently being sent to the FIFO's input. This register shows the 16 bits that are currently being sent to the FIFO's data input. If this data is stable, and the FIFO is given a Write_Enable, then this is the data that will be written into the FIFO. Details of the Input Data FIFO Section -------------------------------------- The Input Data FIFO Section contains the 16 bit wide by 128 step long FIFO and the register to read the FIFO output data. The FIFO is implemented as 7 bit Write and Read Pointer Counters which address a 16 bit wide 128 location Dual Port Static Memory. Each of the Pointer Counters can respond to two commands, i.e. the command reset to zero and the command increment. You can read the current value of both Pointer Counters. The value of the Read Pointer Counter is the FIFO location whose data can currently be read via the Read FIFO Data Regester. The value of the Write Pointer Counter is the FIFO location that will be written into with the next FIFO Write. That is, after a FIFO Write, the Write Pointer Counter is automatically incremented to get it ready for the next FIFO Write. The other function in this section is calculating the difference between the Read Pointer and the Write Pointer. This is done with an 8 bit adder that forms the sum: Write_Pointer_Value + complement of Read_Pointer_Value + 1 The output of this adder 8 bits plus a Carry_Out bit and an Over_Flow bit. If you look at just the low order 7 bits of the sum then you see the difference (without sign) between the two pointers. External logic can watch this difference and can watch which pointer incremented when the difference goes to zero in order to determine if one pointer "lapped" the other. Read FIFO Output Data Register Read Only Register Address = 20 Bits Function ----- --------------------------------------------- 15:0 Show the 16 bits (15:0) that are currently stored in the FIFO at the location being pointed to the the Read Pointer. Read FIFO Pointers Register Read Only Register Address = 21 Bits Function ----- -------------------------------------------------- 6:0 Shows the current value of the 7 bit Read Pointer. This is the location that you are currently reading from. 7 Always reads "0". 14:8 Shows the current value of the 7 bit Write Pointer. This is the next location that will be written to. The FIFO Write operation sequence is Write and then Increment the Write Pointer. 15 Always reads "0". Read Pointer Difference Register Read Only Register Address = 22 Bits Function ----- -------------------------------------------------- 6:0 Shows the 7 low order output bits from the 8 bit adder that forms the sum: Write_Pointer + complement of Read_Pointer + 1 7 Always reads zero 10:8 Always read "0". 11 The 8th i.e. MSBit from the the 8 bit adder that forms the sum: Write_Pointer + complement of Read_Pointer + 1 12 OverFlow output from the Adder 13 Carry Out output from the Adder 14 Shows the 8th bit from the Read Pointer Counter. This signal from the Read Pointer Counter is not used as an address to the FIFO. 15 Shows the 8th bit from the Write Pointer Counter. This signal from the Write Pointer Counter is not used as an address to the FIFO. If you read the low order byte of Register 22 it will show you the Pointer Difference, i.e. number of entries in the FIFO, i.e. the number of times that you need to increment the Read Pointer to make it equal to the Write Pointer. This lower byte is protected in hardware against changing during the VME Read access. From VME you will never read some of the bits representing the current value of the Pointer Different and some of the bits representing this value after an asynchronous Write Pointer increment that is currently taking place. Only this Pointer Difference value is protected in hardware this way. All the bits in the high order byte of Register 22 are just for diagnostic work. They have no use during normal FIFO operation. Details of the Output Section ----------------------------- There are two registers in the Output Registers and Buffers Section. Output Data Readback Register Read Only Register Address = 30 Bit Function --- -------------------------------------------------------- 0 State of the MSA_Out_0 siganal 1 State of the MSA_Out_1 siganal 2 State of the MSA_Out_2 siganal 3 State of the MSA_Out_3 siganal 4 State of Global_L3_Disable coming into the Output Section 5 not used always reads "0" 6 not used always reads "0" 7 not used always reads "0" 8 State of Src_Reset_Write_Pointer coming into the Output Section 9 State of Src_FIFO_Write_Enable coming into the Output Section 10 State of Src_Increment_Read_Pointer coming into the Output Section 11 State of Src_Reset_Read_Pointer coming into the Output Section 12 State of Src_L3_Global_Disable coming into the Output Section 13 State of Src_spare_ctrl_1 coming into the Output Section 14 State of Src_spare_ctrl_1 coming into the Output Section 15 State of Src_spare_ctrl_1 coming into the Output Section For the 32 Dave FPGA's in slots 7 and 9, the first 4 bits of this register are showing you the state of the 4 per Specific Trigger L3 Disable signals that this FPGA sends to the TFW. For the 32 Dave FPGA's in slots 7 and 9, bit 4 of this register shows you the state of the Global_L3_Disable signal that comes into the Output Section and that can be used to force asserted the 4 per Specific Trigger L3 Disable signals that are sourced from one of these FPGA's. For the 2 Dave FPGA's in slot 5, the MS 8 bits have meaning. Bits 11:8 are the 4 Control #1 signals that are generated by FPGA Site #1 in slot 5. This register shows you the state of these signals as they come into the Output Section. After one tick of 132 nsec, this data will come out of the output setction and would also appear in the low order 4 bits of this register. Bits 15:12 are the 4 Control #2 signals that are generated by FPGA Site #2 in slot 5. This register shows you the state of these signals as they come into the Output Section. After one tick of 132 nsec, this data will come out of the output setction and would also appear in the low order 4 bits of this register. Output Section Control Register Read/Write Register Address = 31 Bit Function --- ---------------------------------------------------------------- 0 If this FPGA is sourcing L3_Disables then Assert L3_Disable_N+0 1 If this FPGA is sourcing L3_Disables then Assert L3_Disable_N+1 2 If this FPGA is sourcing L3_Disables then Assert L3_Disable_N+2 3 If this FPGA is sourcing L3_Disables then Assert L3_Disable_N+3 4 not used - readback as written 5 not used - readback as written 6 not used - readback as written 7 not used - readback as written 8 When this FPGA is sourcing L3_Disables then a "1" enables the incomming Global_L3_Disable to assert the 4 L3 Disables sourced by this FPGA. 9 not used - readback as written 10 not used - readback as written 11 not used - readback as written 13,12 These two bits control what signals are sourced by the MSA_Output lines from this FPGA. 0,0 L3 Disables 0,1 Control #1 signals 1,0 Control #2 signals 1,1 not used - undefined 14 not used - readback as written 15 not used - readback as written For the 32 Dave FPGA's in slots 7 and 9, bits 13,12 will be set to 0,0 so that these FPGA's will source Individual Specific Trigger L3 Disables which go to the TFW. In this case: Bits 3:0 are used to cause a given one of these Individual Specific Trigger L3 Disables to be asserted. A "1" implies assert the signal. Bit 8 is used to enable the Global_L3_Disable signal, that comes into the Output Section, to force assert the 4 Individual L3 Disables sourced by this FPGA. A "1" in bit 4 enables the Global_L3_Disable to force the individual L3 Disables asserted. So a given Individual L3 Disable is asserted if either: Its bit in the range 3:0 is a "1" or Bit 8 is a "1" AND the Global L3 Disable signal is asserted. For the 32 Dave FPGA's in slots 7 and 9, I belive that during normal triggers are running operation: bits 13,12 will be set to 0,0, bit 8 will be a "1" (to allow Global_L3_Disable control of these Individual L3 Disable signals), and bit 3:0 will all be "0" (unless L3 wants to block an individual L1 Trigger) For the 2 Dave FPGA's in slot 5 the setup is quite different. These two FPGA's are sources the control signals that are used by slots 7 and 9. Slot 5 FPGA 1 bits 13,12 will be set to 0,1 (i.e. source the Control #1 signals) all other bits should be "0". Slot 5 FPGA 2 bits 13,12 will be set to 1,0 (i.e. source the Control #2 signals) all other bits should be "0". Function of the Output Signals --------------------------------------- MSA Site When Used as Net Name Pin Num a L3_Disable ----------------- -------- -------------- MSA_Output_PAD(0) 31 L3_Disable_n MSA_Output_PAD(1) 32 L3_Disable_n+1 MSA_Output_PAD(2) 33 L3_Disable_n+2 MSA_Output_PAD(3) 34 L3_Disable_n+3 Function of the Output Signals --------------------------------------- MSA Site When Used as a Net Name Pin Num Control Function #1 ----------------- -------- ------------------- MSA_Output_PAD(0) 31 Reset_Write_Pointer MSA_Output_PAD(1) 32 FIFO_Write_Enable MSA_Output_PAD(2) 33 Increment_Read_Pointer MSA_Output_PAD(3) 34 Reset_Read_Pointer Function of the Output Signals --------------------------------------- MSA Site When Used as a Net Name Pin Num Control Function #2 ----------------- -------- ------------------- MSA_Output_PAD(0) 31 Global_L3_Disable MSA_Output_PAD(1) 32 spare-1 MSA_Output_PAD(2) 33 spare-2 MSA_Output_PAD(3) 34 spare-3 Details of the Control and Error Detection Section -------------------------------------------------- Note that the Control and Error Detection Sections are only used in MSA FPGA's #1 and #2 of the card in slot #5. Registers 40 and 42 are used to control the Control & Error Detection functions of the MSA FPGA #1. Register 41 is used to control the Control & Error Detection functions of the MSA FPGA #2. Not all functions of the Control and Error Detection Section have yet been implemented. The following is a description of what has been inplemented. Currently there are two control status registers in the Control and Error Detection Section. Control and Error Detection Register 0, CEDR_0, is used to control the generation of the signals that control the FIFO Read and Write Pointer Counters and the FIFO Write Enable. Control and Error Detection Register 1, CEDR_1, is used to control the FIFO Almost-Full Comparator and to control the generation of the Global L3 Disable Signal. The Global L3 Disable Signal is generated in the Control and Error Detection Section and then sent to the Output Section of all the DAVE fpga's in slots 7 and 9 where it can be selectively "ORed" with the Individual l3 Diable signals (one for each of the 128 L1 Triggers). Control and Error Detection Register 2, CEDR_2, is used to control the FIFO Too-Full Comparator Control and Error Detection Register 0 Read/Write Register Adrs = 40 Bit Function --- ---------------------------------------------------------------- 0 Resets the FIFO Read Pointer to zero while asserted 1 Resets the FIFO Write Pointer to zero while asserted. 3:2 not used - readback as written 4 Increments the FIFO Read Pointer on the 0 to 1 transition 7:5 not used - readback as written 8 Enable the bit 9 initiated FIFO Write followed by Increment of the FIFO Write Pointer (see bit 5) 9 If enabled by bit 8 of this register, then on the "0" to "1" transition of this bit, write to the FIFO, and then Increment the FIFO Write Pointer. 10 Enable the Strobe signal on the Control Path from the Trigger Framework to cause a FIFO Write followed by an Increment of the FIFO Write Pointer. 11 not used - readback as written 12 Enable the FIFO "Too-Full" flag to block writing to the FIFO. If enabled to block FIFO writes, the Too-Full flag will block all FIFO writes, i.e. both FIFO writes initiated by bit 9 of this register and FIFO writes initiated by the Strobe signal on the Control Path from the Trigger Framework. 15:13 not used - readback as written Note: Except for setting default quiescent values at initialization, Register 40 is used only on MSA FPGA #1 on the card in slot #5. Typically when initializing in preparation for normal operation, both bits 0 and 1 will be asserted at the same time to reset both Read and Write FIFO Pointers to zero. When both of these FIFO Pointer Resets are asserted at the same time, the FIFO direction read-only bits in register 42 are initialized to show that Write Leads Read, i.e. the condition that will exist durning normal operation. Control and Error Detection Register 1 Read/Write Register Adrs = 41 Bit Function --- ---------------------------------------------------------------- 7:0 These bits specify the Reference Value for the FIFO Almost-Full Comparator. If the number of events that have been written into the FIFO but have not yet been readout exceeds this Reference Value then the FIFO Almost-Full Comparator's output is asserted. The FIFO Almost-Full Comparator's output can be enabled to assert the Global_L3_Disable and thus assert all 128 Intividual_L3_ Disables signals and thus stop the L1_Accepts and thus stop the Writes to the FIFO and thus prevent the FIFO from overflowing. A typically value to set in these bits for the Reference Value to the FIFO Almost-Full Comparator is about 100. I.E. once 100 events have been written into the FIFO that have not been readout the FIFO Almost-Full Comparator's output will be asserted. 9:8 not used - readback as written 10 Enable assertion of the Global L3 Disable to be caused by the FIFO Almost-Full Comparator's output being asserted. Note that for this to result in actually sending a Disable to the TFW you also need to enable the Global L3 Disable to be "ORed" into the Individual L3 Disables in the DAVE fpga's in slots 7 and 9. This is the primary method for preventing FIFO overwrites. 11 Setting this bit to "1" asserts the Global L3 Disable Signal. Note that for this to result in actually sending a Disable to the TFW you also need to enable the Global L3 Disable to be "ORed" into the Individual L3 Disables in the DAVE fpga's in slots 7 and 9. 15:12 not used - readback as written Note: Except for setting default quiescent values at initialization, Register 41 is used only on MSA FPGA #2 on the card in slot #5. Control and Error Detection Reg 2 Read/Write - Read-Only Reg Adrs = 42 Bit Function --- ---------------------------------------------------------------- 7:0 These bits specify the Reference Value for the FIFO Too-Full Comparator. If the number of events that have been written into the FIFO, but have not yet been readout, exceeds this Reference Value then the FIFO Too-Full Comparator's output is asserted. The FIFO Too-Full Comparator's output when asserted can be enabled to block all further Writes to the FIFO and thus prevent the FIFO from overflowing. When FIFO overflow is blocked in this way, the data from any attempted writes to the FIFO is lost. A typically value to set in these bits for the Reference Value to the FIFO Too-Full Comparator is about 125. I.E. once 125 events have been written into the FIFO that have not been readout the FIFO Too-Full Comparator's output will be asserted. 9,8 not used - readback as written 10 When asserted, this bit Clears the FIFO Too-Full Flag. See the description of bit 12 in this register. This is the only way to clear the FIFO Too-Full Flag. Normally this bit should be left in the low state so that a FIFO Too-Full condition can be latched by the FIFO Too-Full Flag. 11 not used - readback as written 12 Read-Only This bit shows the state of the FIFO Too-Full Flag. If when you read this register you find this bit asserted it means that at some point the FIFO Too-Full Comparator output was asserted. If enabled by bit 12 in Register 40, an asserted FIFO Too-Full Flag will block all further writes to the FIFO. The only way to clear this flag is by pulsing bit 10 of this register to a high state. Note that finding the FIFO Too-Full Flag asserted does not mean that FIFO Writes have actually been Blocked (and thus data lost). It just means that so much data has been written into the FIFO, that has not yet been readout, that any additional FIFO Writes would be Blocked. In normal operation, with the reference values for the FIFO Almost-Full and FIFO Too-Full Comparators correctly set, the FIFO Too-Full Flag should NEVER be set. This is because L1_Accepts will be disabled and thus FIFO Writes stopped well before the FIFO Too-Full limit is reached. 13 Read-Only This bit shows the state of the Write Leads Read Flag. This is for diagnostics only. It is asserted either by: Resetting both the Read and Write FIFO Pointer Counters at the same time, or when both the Read and Write Pointers are Equal and the next action is a Write Pointer Increment. 14 Read-Only This bit shows the state of the Read Leads Write Flag. This is for diagnostics only. It is asserted when: both the Read and Write Pointers are Equal and the next action is a Read Pointer Increment. 15 Read-Only This bit shows the state of the output of the Read and Write Pointers are Equal Comparator. When the Pointers are NOT equal, the FIFO_Not_Empty signal is asserted and thus this bit is asserted. You can also read the state of the FIFO_Not_Empty signal on bit 4 of the Chip Control Status Register (Reg Adrs 0). It is the FIFO_Not_Empty signal that can be used in MSA FPGA #1 of the card in slot #5 to send "Status" to the VME Interface on the card in slot #5 and thus (if enabled) cause a VME Interrupt. Note: Except for setting default quiescent values at initialization, Register 42 is used only on MSA FPGA #1 on the card in slot #5. Bits 11:0 of Register 42 are Read/Write. Bits 15:12 of this register are Read-Only. The control signals that are generated by the slot 5 MSA FPGA numbers 1 and 2 loop out from the front panel connector and into the back of the slot 1 TOM card. The following table describes this cabling. Control Distribution Signal TOM, P1_TS, THE-Card HQ_TS Source ------------------------------------ ---------- Enters MSA MSA Control Signal Slot #1 Distribution FPGA Out Name -Function TOM_PB Is Carried On To ---- --- ---------------------- -------- ------------------------ Tick_Clock J2-3,4 P1_TS_1 HQ(0) 1 0 Reset_Write_Pointer J4-11,12 P1_TS_11 HQ(1) 1 1 FIFO_Write_Enable J4-19,20 P1_TS_13 HQ(2) 1 2 Increment_Read_Pointer J5-15,16 P1_TS_15 HQ(3) 1 3 Reset Read_Pointer * J4-3,4 P1_TS_9 Cap_HSRO_Data 2 0 Global_L3_Disable * J4-7,8 P1_TS_10 Cap_Mon_Data * --> Just these 2 signals need to be inverted on thier way from the slot 5 front panel to the slot 1 TOM_PB. (just these two surrers an inversion in the BSF). Routing of the Control Signals through the BSF FPGA --------------------------------------------------- The Control Path Interface AONM cards use a standard BSF. Its P1_TS to HQ_TS mapping control register is setup to implement the following: (Reg 16 loaded with $2220) P1 THE_Card MSA Site Timing Signal Net Function Pin Number ------------- ------------- -------------------- ---------- P1(1) HQ(0) Tick_Clock 2 PGCK P1(11) HQ(1) Reset_Write_Pointer 63 PGCK P1(13) HQ(2) FIFO_Write_Enable 124 PGCK P1(15) HQ(3) Increment_Read_Pointer 184 PGCK P1(9) Cap_HSRO_Data * Reset Read_Pointer 133 I/O P1(10) Cap_Mon_Data * Global_L3_Disable 134 I/O * --> surrers an inversion Chip Control Status Register ---------------------------- Each Main Signal Processing Array FPGA in the L1/L2 Framework has a Chip Status Control Register to manage some chip wide functions. One of the things that is managed is whether or not a particular chip can assert its "Status" signal to the VME Interface on THE-Card. The various bits in the Chip Control Status Register in the DAVE FPGA provide control of the "Status" signal in the following ways: Provide a way to enable, under certain conditions, the generation of an asserted "Status" signal, or else to absolutely block the generation of asserted "Status". Provide a way to manually assert "Status" (assuming that asserted "Status" has not been blocked by the first item in this list). Provide a way to see the state of the "Status" signal that is being sent to the VME Interface. Provide a way to enable FIFO_Not_Empty to generate an asserted "Status" (assuming that asserted "Status" has not been blocked by the first item in this list). Provide a way to see the state of the FIFO_Not_Empty signal. Chip Control Status Register Read/Write & Read-Only Register Adrs = 0 Bit Function --- ---------------------------------------------------------------- 0 R/W A "1" enables this chip to send asserted "Status" to the VME Interface Chip where it may be enabled to generate a VME Interrupt Request. 1 R/W If enabled by bit 0, a "1" in this bit will cause "Status" to be asserted to the VME Interface. 2 R-Only This bit shows the state of the "Status" line that runs from this chip to the VME Interface. 3 R/W If enabled by bit 0, a "1" in this bit will enable an asserted FIFO_Not_Empty signal to cause the "Status" signal to be asserted to the VME Interface. 4 R-Only This bit show the state of the FIFO_Not_Empty signal. 15:5 R-Only Always read "0". Recall the Layout of VME Addressing ----------------------------------- The details for the VME Addressing of for THE-Card is presented in www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/the_card/ the_card_vme_interface.txt All VME access to THE-Card is A24-D16. The 24-bit VME address space is subdivided into Card, Chip, and Register Addresses as follows: A A A A A A A A A A A A A A A A A A A A A A A A 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ----------------------------------------------- | Card | Chip | | Register | 0 0 0| Address | Addres |*| Address |+ Notes: * : 9th Register Address bit. This bit must be held LOW. It is reserved for future possible expansion of the Register Address space. + : VME A00 must be held LOW. THE Card only supports word-aligned 16-bit transfers. Chip Address: 0 is the VME Interface FPGA 16:1 is the 16 Main Signal Processing Array FPGA's 17 is the Board Support Function "BSF" FPGA. The mapping of Backplane slots to Card Base Addresses is as follows: Card Card Addr Addr Card Base Slot Dec Hex Address Comment ---- ---- ---- --------- ------- 1 1 $ 01 $008000 typically a Vert Inter, not a THE Card 2 4 $ 04 $020000 3 7 $ 07 $038000 4 10 $ 0A $050000 5 13 $ 0D $068000 6 16 $ 10 $080000 7 19 $ 13 $098000 8 22 $ 16 $0b0000 9 25 $ 19 $0c8000 10 28 $ 1C $0e0000 11 31 $ 1F $0f8000 12 34 $ 22 $110000 13 37 $ 25 $128000 14 40 $ 28 $140000 15 43 $ 2B $158000 16 46 $ 2E $170000 17 49 $ 31 $188000 18 52 $ 34 $1a0000 19 55 $ 37 $1b8000 20 58 $ 3A $1d0000 21 61 $ 3D $1e8000 Initial Test Programs --------------------- Verify that you can control the FIFO Read and Write Pointers Configure Initialize Loop Make some number of FIFO Writes Make some number of FIFO Reads Check that slot 5 DAVE #1 shows the correct "Pointer Difference" Check the 16 copies of the FIFO Pointer Register in slots 5, 7, and 9 to verify that they all say the same and correct numbers. Report errors or stop One_More_Time Check the Individual L3 Disables and the Global L3 Disable Use the Test Data register to write data into the FIFO and read it back in the normal way. Interrupt test Enable Interrupts Manually cause the Interrupt to be asserted (assert Status) Verify that you field an interrupt. '"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'"'" All stuff below here is development stuff