! Setup the DAVE L3 <-> TFW Interface for Normal Operation. ! Created 23-APR-02 D.E. ! This is the basic routine that you would execute to initialize the ! system when you first bring it up. You could also use this when ! you want to "reset" the system, i.e. remove all events from this FIFO ! that you do not want to readout and process normally. ! This program will first setup the Board Support Functions on each of the ! three THE-Cards in this system. That part is not very interesting. For ! now they are all setup the same. When we use interrupts, the Slot 5 BSF ! will have a slightly different setup. All that we are using the BSF for ! is the routing of some common control signals - all the rest of its functions ! are just parked in a quiescent state. ! The main part of this program sets up the 16 DAVE FPGA's on each of the 3 ! THE-Cards. Yes, even the 14 DAVE FPGA's on the Slot 5 card that are not ! used need to be setup so that they do not cause trouble. The first step ! in setting up each DAVE FPGA is to use the Dave_Init_Norm_Op_Include.rii ! file on it. This puts nominal quiescent data into all the control registers ! in the DAVE FPGA. Then any special configurate for a particular DAVE FPGA ! is done. Finally the Control & Error Detection FPGA's in slot 5 are used ! to set the Read and Write pointers to zero and to enable the Control Path ! to write into the FIFO. ! The setup that is specific to a give DAVE FPGA includes: ! ! All DAVE FPGA's that source Individual_L3_Disable signals are setup ! so that the Global_L3_Disable signal is "ORed" into the Individual_ ! L3_Disable signals that they generate. ! ! We use the Input FIFO in a number of DAVE FPGA's. For each one of these ! we setup which block of 16 bits of MSA_Input data that DAVE will FIFO. ! ! Setup the Control & Error Detection FPGA's (DAVE FPGA's #1 and #2 in ! slot 5 so that they: ! ! DAVE #1 in slot 5 outputs the group 1 control signals ! Dave #2 in slot 5 outputs the group 2 control signals ! ! Set the Almost-Full reference value to 104 decimal, i.e. when ! 104 entries have been written into the FIFO that have not yet been ! readout, then the Almost-Full threshold will be exceeded. ! ! Enable assertion of Almost-Full to cause the assertion of the ! Global_L3_Disable signal and thus the assertion of all 128 ! Individual_L3_Disable signals and thus block new L1 Triggers. ! ! Set the Too-Full reference value to 124 decimal, i.e. when ! 124 entries have been written into the FIFO that have not yet been ! readout, then the Too-Full threshold will be exceeded. ! ! Enable the assertion of Too-Full to block any further writes to the FIFO. ! ! Except for using interrupts this is the basic setup that would be used for ! normal data taking operation. ! Setup the Board Support Functions FPGA (BSF) on each card. ! They are all setup the same way. Vertical_Master: 3 Vertical_Slave: 2 ! First setup the BSF in slot 5 Card_Slot: 5 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! Now setup the BSF in slot 7 Card_Slot: 7 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! Finally setup the BSF in slot 9 Card_Slot: 9 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! Now initialize all the DAVE MSA FPGA's on the 3 cards. ! Use an rii file to bring them to the following state: ! Chip CSR0 to $0000. ! Input Multiplexer set to select the Test Data Register. ! Test Data Register loaded with $0000. ! Output Control Register set for: ! Select the Individual Disable signals as the output. ! Do not assert any of the Individual Disable signals. ! Do not enable the Global Disable to "OR" into the Individual Disables. ! Control & Error Detection Register 0 all disabled. ! Control & Error Detection Register 1 all disabled. ! Control & Error Detection Register 2 all disabled. ! After the rii, do any configuration that is fpga site specific and then ! move to the next site. Card_Slot: 5 ! Start with the 16 MSA FPGA's in slot 5 ! DAVE's #1 and #2 on this card are the Control & Error ! Detections parts. The other 14 DAVE's are not used ! on this card. Chip_Address: 1 ! This is the Control Error Detection #1 FPGA Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Control Register Write_Value: 0x1000 ! Select the Control Signals Group #1 to output. Chip_Address: 2 ! This is the Control Error Detection #2 FPGA Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Control Register Write_Value: 0x2000 ! Select the Control Signals Group #2 to output. Chip_Address: 3 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 4 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 5 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 6 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 7 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 8 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 9 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 10 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 11 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 12 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 13 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 14 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 15 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Chip_Address: 16 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Card_Slot: 7 ! And now the 16 MSA FPGA's in slot 7 ! Slot 7 FIFO's the Fired Mask and ! sources Individual_L3_Disables 63:0 Chip_Address: 1 ! Input FIFO Mask 15:0 Disables 3:0 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0000 ! Select MSA_In_(15:0) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 2 ! Input FIFO Mask 31:16 Disables 7:4 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0001 ! Select MSA_In_(31:16) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 3 ! Input FIFO Mask 47:32 Disables 11:8 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0002 ! Select MSA_In_(47:32) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 4 ! Input FIFO Mask 63:48 Disables 15:12 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0003 ! Select MSA_In_(63:48) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 5 ! Input FIFO Mask 79:64 Disables 19:16 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0004 ! Select MSA_In_(79:64) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 6 ! Input FIFO Mask 95:80 Disables 23:20 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0005 ! Select MSA_In_(95:80) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 7 ! Input FIFO Mask 111:96 Disables 27:24 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0006 ! Select MSA_In_(111:96) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 8 ! Input FIFO Mask 127:112 Disables 31:28 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0007 ! Select MSA_In_(127:112) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 9 ! Input FIFO not used Disables 35:32 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 10 ! Input FIFO not used Disables 39:36 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 11 ! Input FIFO not used Disables 43:40 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 12 ! Input FIFO not used Disables 47:44 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 13 ! Input FIFO not used Disables 51:48 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 14 ! Input FIFO not used Disables 55:52 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 15 ! Input FIFO not used Disables 59:56 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 16 ! Input FIFO not used Disables 63:60 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Card_Slot: 9 ! And finally the 16 MSA FPGA's in slot 9 ! Slot 9 FIFO's the L3_Transfer_Number and ! sources Individual_L3_Disables 127:64 Chip_Address: 1 ! Input FIFO L3_Trans_Num 15:0 Disables 67:64 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 11 ! Input Data Selection Control Register Write_Value: 0x0000 ! Select MSA_In_(15:0) Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 2 ! Input FIFO not used Disables 71:68 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 3 ! Input FIFO not used Disables 75:72 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 4 ! Input FIFO not used Disables 79:76 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 5 ! Input FIFO not used Disables 83:80 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 6 ! Input FIFO not used Disables 87:84 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 7 ! Input FIFO not used Disables 91:88 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 8 ! Input FIFO not used Disables 95:92 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 9 ! Input FIFO not used Disables 99:96 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 10 ! Input FIFO not used Disables 103:100 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 11 ! Input FIFO not used Disables 107:104 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 12 ! Input FIFO not used Disables 111:108 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 13 ! Input FIFO not used Disables 115:112 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 14 ! Input FIFO not used Disables 119:116 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 15 ! Input FIFO not used Disables 123:120 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga Chip_Address: 16 ! Input FIFO not used Disables 127:124 Call_File: %TRICS%\Scratch\Dave_Init_Norm_Op_Include.rii Register_Address: 31 ! Output Section Control Register Write_Value: 0x0100 ! "OR" the Glb_L3_Disable into the 4 ! Individual_L3_Disable signals sourced by this fpga ! Now that everyone is awake and rational and paying attention you can ! reset to zero all the Read and Write Pointer Counters and setup the ! other aspects of normal operation, e.g. the Almost-Full and Too-Full ! reference values and finally enable the Control Path to write into the FIFO. Card_Slot: 5 ! Slot 5 has the DAVE's with the active Control ! Error Detection sections. Chip_Address: 1 ! This is the Control Error Detection #1 FPGA Register_Address: 40 ! Control Section #1 Control Register #0 Write_Value: 0x0000 ! Disable: everything Write_Value: 0x0003 ! Reset both the Read Pointer Write_Value: 0x0000 ! and the Write Pointer. Register_Address: 42 ! Control Section #1 Control Register #2 Write_Value: 0x047C ! Too-Full Reference = 124 decimal = $007C ! Clear the Too-Full has happened flag, ! i.e. assert bit 10 = $0400 Write_Value: 0x007C ! Too-Full Reference = 124 decimal = $007C ! Stop clearing the Too-Full has happened flag. Chip_Address: 2 ! This is the Control Error Detection #2 FPGA Register_Address: 41 ! Control Section #2 Control Register #1 Write_Value: 0x0468 ! Almost-Full Reference = 104 decimal = $0068 ! Enable Almost-Full to cause assertion of Glb_L3_Disable ! which is bit 10 i.e. $0400 ! Note that if you wanted to force the Glb_L3_Disable ! to be asserted here is where you can do it. ! Asserting bit 11 = $0800 will force Glb_L3_Disable ! asserted. So if you wanted to set an Almost-Full ! threshold of 104 = $0068, enable Almost-Full to ! cause Glb_L3_Dis, and force Glb_L3_Dis enabled to ! stop all new L1 Triggers you would write $0C68 ! to this register. Chip_Address: 1 ! This is the Control Error Detection #1 FPGA Register_Address: 40 ! Control Section #1 Control Register #0 Write_Value: 0x0000 ! Disable: everything Write_Value: 0x0003 ! Reset both the Read Pointer Write_Value: 0x0000 ! and the Write Pointer. Write_Value: 0x1400 ! Enable Control Path Strobe to cause a FIFO Write ! this is bit 10 = $0400 ! Enable Too-Full to block all FIFO Writes ! this is bit 12 = $1000