! Initial attempt at setting up the DAVE L3 <-> TFW Interface ! Created 11-APR-02 D.E. in the scratch directory ! Setup the Board Support Functions FPGA (BSF) on each card. ! They are all setup the same way. Vertical_Master: 3 Vertical_Slave: 2 ! First setup the BSF in slot 5 Card_Slot: 5 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! First setup the BSF in slot 7 Card_Slot: 7 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! First setup the BSF in slot 9 Card_Slot: 9 Chip_Address: 17 Register_Address: 0 Write_Value: 0x0000 ! chip csr interrupts off Register_Address: 1 Write_Value: 0x0001 ! chip csr LED is on Register_Address: 2 Write_Value: 0x0000 ! Disable TS based scaler resets Register_Address: 3 Write_Value: 0x0000 ! Do not hold scalers in reset Register_Address: 4 Write_Value: 0x0000 ! All P5 I/O is disables Register_Address: 5 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 6 Write_Value: 0x0000 ! BG I/O 16:0 are all inputs to BSF Register_Address: 8 Write_Value: 0x0247 ! Final in sequence of G-Link setup Register_Address: 16 Write_Value: 0x2220 ! P1_TS to HQ map Register_Address: 32 Write_Value: 0x0008 ! HSRO Header Word 0 Register_Address: 34 Write_Value: 0x0000 ! HSRO Header Word 1 Register_Address: 35 Write_Value: 0x0000 ! HSRO Trailer Word 0 Register_Address: 36 Write_Value: 0x0000 ! Tick History Shift Register Control ! Now initialize all the DAVE MSA FPGA's on the 3 cards. ! Use an rii file to bring them to the following state: ! Chip CSR0 to $0000. ! Input Multiplexer set to select the Test Data Register. ! Test Data Register loaded with $0000. ! Output Control Register set for: ! Select the Individual Disable signals as the output. ! Do not assert any of the Individual Disable signals. ! Do not enable the Global Disable to "OR" into the Individual Disables. ! Control Section #1 all disabled. ! Control Section #2 do not assert Glb_L3_Disable. ! After the rii, do any configuration that is fpga site specific and then ! move to the next site. Card_Slot: 5 ! Start with the 16 MSA FPGA's in slot 5 Chip_Address: 1 ! This is the Control Error Detection #1 FPGA Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Register_Address: 31 ! Output Control Register Write_Value: 0x1000 ! Select the Control Signals Group #1 to output. Chip_Address: 2 ! This is the Control Error Detection #2 FPGA Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Register_Address: 31 ! Output Control Register Write_Value: 0x2000 ! Select the Control Signals Group #2 to output. Chip_Address: 3 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 4 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 5 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 6 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 7 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 8 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 9 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 10 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 11 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 12 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 13 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 14 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 15 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 16 ! This is a spare Dave fpga. Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Card_Slot: 7 ! And now the 16 MSA FPGA's in slot 7 Chip_Address: 1 ! Input FIFO Mask 15:0 Disables 3:0 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 2 ! Input FIFO Mask 31:16 Disables 7:4 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 3 ! Input FIFO Mask 47:32 Disables 11:8 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 4 ! Input FIFO Mask 63:48 Disables 15:12 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 5 ! Input FIFO Mask 79:64 Disables 19:16 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 6 ! Input FIFO Mask 95:80 Disables 23:20 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 7 ! Input FIFO Mask 111:96 Disables 27:24 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 8 ! Input FIFO Mask 127:112 Disables 31:28 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 9 ! Input FIFO not used Disables 35:32 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 10 ! Input FIFO not used Disables 39:36 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 11 ! Input FIFO not used Disables 43:40 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 12 ! Input FIFO not used Disables 47:44 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 13 ! Input FIFO not used Disables 51:48 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 14 ! Input FIFO not used Disables 55:52 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 15 ! Input FIFO not used Disables 59:56 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 16 ! Input FIFO not used Disables 63:60 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Card_Slot: 9 ! And finally the 16 MSA FPGA's in slot 9 Chip_Address: 1 ! Input FIFO L3_Trans_Num 15:0 Disables 67:64 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 2 ! Input FIFO not used Disables 71:68 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 3 ! Input FIFO not used Disables 75:72 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 4 ! Input FIFO not used Disables 79:76 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 5 ! Input FIFO not used Disables 83:80 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 6 ! Input FIFO not used Disables 87:84 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 7 ! Input FIFO not used Disables 91:88 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 8 ! Input FIFO not used Disables 95:92 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 9 ! Input FIFO not used Disables 99:96 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 10 ! Input FIFO not used Disables 103:100 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 11 ! Input FIFO not used Disables 107:104 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 12 ! Input FIFO not used Disables 111:108 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 13 ! Input FIFO not used Disables 115:112 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 14 ! Input FIFO not used Disables 119:116 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 15 ! Input FIFO not used Disables 123:120 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii Chip_Address: 16 ! Input FIFO not used Disables 127:124 Call_File: %TRICS%\Scratch\Dave_Default_Init_Test_1.rii ! Now that everyone is awake and rational and paying attention you can ! reset to zero all the Read and Write Pointer Counters by issuing commands ! to the control and error detections section #1. Card_Slot: 5 ! Slot 5 has the DAVE's with the active Control ! Error Detection sections. Chip_Address: 1 ! This is the Control Error Detection #1 FPGA Register_Address: 40 ! Control Section #1 Control Register Write_Value: 0x0000 ! Disable: everything Write_Value: 0x0003 ! Reset both the Read Pointer Write_Value: 0x0000 ! and the Write Pointer.