!  Dave   Read FIFO

!  This program will:
!    read the FIFO Pointer Register
!    read the FIFO Pointer Difference Register
!    read Control and Error Detection Register #2
!    read the Output Data Readback Register
!    read the 8 FIFO Output Registers in Slot 7, i.e. read the Fired Mask
!    read the 1 FIFO output Register in Slot 9, i.e. read the L3_Transfer_Num
!    and finally increment the FIFO Read Pointer so that the FIFO is ready
!      to read the next time.
!
!  It does all of this whether or not there is a new entry in the
!  FIFO for it to read.

!  Created 23-APR-02  D.E.


!  Let's talk with the correct crate

Vertical_Master: 3
 Vertical_Slave: 2
 
! First read the current value of the FIFO Pointer Register and then Read
! the FIFO Pointer Difference Register and finally the Control & Error
! Detection Register #2   all of this is from FPGA 1 on card slot 5.

   Card_Slot: 5
      
   Chip_Address: 1

   Read_Register:     21     ! Read the FIFO Pointer Register
                             !  The low byte is the Read Pointer Address
                             !  The hi byte is the Write Pointer Address

   Read_Register:     22     ! Read the FIFO Pointer Difference Register
                             !   The low byte is how many entries have been written
                             !   into the FIFO that have not yet been readout.
 
   Read_Register:     42     ! Read the Control & Error Detection Register #2
                             !   Bit #12 (=$1000)  if set shows that at some time the
                             !   FIFO was too-full and may have blocked writes to the FIFO.
    Chip_Address: 2

   Read_Register:     30     ! Read the Output Data Readback Register
                             !   Bit #4 (=$0010)  if set shows that Global_L3_Disable
                             !   is asserted,  i.e. the FIFO has reached Almost-Full
                             !   and is stopping new L1 triggers.




! Now Read the FIFO Output Registers from the first 8 FPGA's in slot 7

   Card_Slot: 7
      
   Chip_Address: 1
   Read_Register:     20     ! Read the FIFO Output Register   Mask 0:15

   Chip_Address: 2
   Read_Register:     20     ! Read the FIFO Output Register   Mask 16:31

   Chip_Address: 3
   Read_Register:     20     ! Read the FIFO Output Register   Mask 32:47

   Chip_Address: 4
   Read_Register:     20     ! Read the FIFO Output Register   Mask 48:63

   Chip_Address: 5
   Read_Register:     20     ! Read the FIFO Output Register   Mask 64:79

   Chip_Address: 6
   Read_Register:     20     ! Read the FIFO Output Register   Mask 80:95

   Chip_Address: 7
   Read_Register:     20     ! Read the FIFO Output Register   Mask 96:111

   Chip_Address: 8
   Read_Register:     20     ! Read the FIFO Output Register   Mask 112:127


! Now Read the FIFO Output Registers from the first FPGA in slot 9

   Card_Slot: 9
      
   Chip_Address: 1
   Read_Register:     20     ! Read the FIFO Output Register   L3_Trans_Num


!  Now Increment the FIFO Read Pointer

   Card_Slot: 5 
   Chip_Address: 1
   
      Register_Address: 40     ! Control Error Detection Section Register #1
      Write_Value: 0x1410      ! Increment the Read Pointer
                               ! Assert:  Inc Read Pointer,  Enable Control
                               ! Path Strobe to do a FIFO Write, and
                               ! Enable Too-Full to block FIFO Writes.

      Register_Address: 40     ! Control Error Detection Section Register
      Write_Value: 0x1400      ! Default Value
                               ! Assert:  Enable Control Path Strobe to do a
                               ! FIFO Write,  and Enable Too-Full to block
                               ! FIFO Writes.