D-Zero Hall Log Book -------------------- The most current version of this file is on the web - Dirac's version may be out of date. Spin.py should be used to update this file. The most recent entries are near the beginning of this file. This file goes back to March 1998. Earlier D-Zero Hall Log Books are on the web at http://www.pa.msu.edu:80/hep/d0/ftp/run1/l1/inventory_logs. DATE: At: Fermi TOPICS: DATE: At: Fermi TOPICS: DATE: 20-DEC-1999 At: MSU TOPICS: Boris Baldin running Trig FW tests Geo Sect L1 Trig BX Num on the SCL. Boris called to say that when they watch the Logic Analyser on the SCL Receiver they capture the same Geo Sect L1 BX Num as they do on their Muon Controller that is a number that is 4 less than what we capture in the T&T Scaler. So it looks like the T&T SM is capturing the Geo Sect L1 Trig Num 4 ticks after the tick that had the L1 Accept. I think that this had all been tested when we had the SCL Receiver in the MCH on the SCL Receiver Tester board and were looking at its output on the logic analyser. But I could be wrong and this may never have been tested. DATE: 20-DEC-1999 At: MSU TOPICS: Boris Baldin running Trig Framework Boris Baldin powers up the Trig FW so that he can have a stream of SCL data. The problem is that power was off over the weekend and thus the Master Clock was not running. Steve spots the problem by looking in the log file and sees that none of the FPGA's loaded. DATE: 15,16,17-DEC-1999 At: Fermi TOPICS: Work on SCL with Muon, Meeting with Ted and Neal Hand Monitoring: A good way to watch the Spec Trig #1 run is to do register reads Mst 1 Slv 1 Slt 11 Chip 1 Reg 40,41. To read the Geo Sect Current BX Num: Mst 1 Slv 2 Slot 21 Chip 15 To read the Geo Sect L1 Trigger Num: Mst 1 Slv 2 Slot 21 Chip 16 reg 36 is the Tick Num reg is the Turn Num LSB reg 38 is Turn MSB Tick and Turn Scaler: I can not find this information about the Tick & Turn Scaler anywhere else so I wanted to record it here. Tick & Turn is in M123 Bot crate slot 21 i.e. Master 1, Slave 2, Slot 21 Tick and Turn Number Electrical Outputs: Geo Sect Current BX Number is on MSA(31:0) (Chip 15) MSA_Out(7:0): Tick MSA_Out(15:8): reserved for And-Or "Selected Tick Gate" inputs MSA_Out(31:16): Turn Geo Sect L1 Trigger Number is on MSA(63:32) (Chip 16) MSA_Out(39:32) Tick MSA_Out(47:40) unused, may be used for And-Or Tick Gate inputs MSA_Out(63:48) Turn The Tick & Turn Scaler ingests the SCL Initialize signal on its MSA_In_1 input. That is the only single signal connection to the Tick & Turn Scaler. All this from a 9-SEP-1999 Steve email. Brought to Fermi and installed the crate and backplane C9 for the middle M101 crate and a 9U Card file without backplane for the card storage rack. Paddle boards currently at Fermi: 5x R-PB with resistors but with only 2 34 pin connectors Global Disable TRM and L1 Front-End Busy TRM inputs 3x R-PB without resistors and with 4 34 pin connectors Rev B L1 Accept per Geo Section to SCL Hub-End and ? 1x R-PB with resistors and with 4 34 pin connectors Rev A 1x TOM PB 2x Front PB 2x Carmen PB Meeting with Ted and Neal: They do not have a vendor for the 26 conductor 25 mil twist-n-flat cable that keeps it all laminated. Ted has a new description of the Receiver Card written, and ready to proof read and then distribute. They are doing a long 6 channel run over the holidays. There are/were only ever two versions of the Receiver pcb. The one that sticks out where the MCX connector is located is the 2nd version. Dean things that the front panel clearance on the 2nd version of the Receiver pcb is "almost OK". The alternative is to go to a SMB type connector which does stick out further but is hard to push on. It uses the same package foot print as the MCX. The other big point is that it is going to be very hard to install 128 of these Times Microwave cables and MCX connectors at the Hub-End. The cables are stiff and have no rotational flex. They would cross over adjacent Fan-Out cards so to pull one Fan-Out you would have to un-cable others. Their proposed solution is to take the Fan-Out signals through smaller diameter cable with straight connectors to a patch panel where it would switch to the LMR-200 cable. If we need to move to the SMB series connector on the Receiver Mezzanine Card then the Johnson part numbers are 131-3407-101 for the cable and 131-1701-371 for the square pcb mount connector. Default MCX connector for the Receiver MCX right angle jack receptacle pcb through hole mount Johnson 133-3701-321 stands 0.213" above the pcb center line of the nose is 0.118" above the pcb nose sticks out 0.256" from the center of the connector body Example SMB connector for the Receiver that I picked up on Friday (too tall) SMB right angle jack receptacle - die cast pcb through hole mount Johnson 131-1701-371 stands 0.375" above the pcb centerline of the nose is 0.218" above the pcb nose sticks out 0.430" from the center of the connector body Other SMB connectors (height is OK but centerline of nose is different from MCX) SMB right angle bulkhead jack receptacle pcb through hole mount Johnson 131-3701-341 stands 0.302" above the pcb centerline of the nose is 0.177" above the pcb threaded nose sticks out 0.656" from the center of the connector body SMB right angle bulkhead jack receptacle pcb through hole mount Johnson 131-3701-501 stands 0.302" above the pcb centerline of the nose is 0.177" above the pcb threaded nose sticks out 0.656" from the center of the connector body All use the same pcb through hole foot print. Made up a 75 ft and a 125 ft LMR-200 MCX cable. The MCX connectors use the Kings KTH-1000 tool with the KTH-2001 jaws. Work trying to get SCL going with the Muon system. The instructions that they should use to get SCL going are in: http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/rack_crate/ scl_startup.txt Kistern made an RIO file so that we can use the Auto Disable to send them one trigger at a time. Need to bring a new soldering iron tip to Fermi for the Weller Iron. Kirsten and I got accounds on d0ola. This is necessary (both in general) and because the boot host for the 68k that runs the Master Clock is changing from what ever it is now to d0ola /online/ioc/m68k/mv162/d0olctl06 We got the accounts through Jim Fitzmaurice who takes care on the online side of things. When you log in you need to change your password using yppasswd. Ran >60k loops of SCT. Date: 24, 29-30-NOV At: Fermi TOPICS: TRM Clock offset +2 30-Nov-1999 Steve: The Xilinx simulator says that the current AONM FPGA (4036XLA) does its processing in ~24 ns (compared to ~56 ns for the same design in the 4013L). After making measurements, I determined that the 56 ns number was very pessimistic, actual FPGA speeds were about 2X that (but of course the Xilinx simulator doesn't include delays on the PCB...when these are included in the measurements, the measured board in-to-out speed ends up almost identical to the FPGA in-to-out speed advertised by the simulator). Assuming that the Xilinx simulator is equally pessimistic for 4036XLA's (i.e. actual 4036XLA speed is 2X the advertised number), and that the board-induced delays remain the same for the 2 runs of AONM, I calculate a board in-to-out delay for the new AONM of ~38 ns (I haven't measured this number). This is a gain of 18 ns compared to the old AONM. This is just slightly less than the amount by which we have moved the TRM Clock. So if it was just barely working before, it is plausible that it is just barely *not* working now (with new FPGA and new timing). I have moved a new, marginally faster version of this FPGA onto D0TCC and MSUL1A (aonm_32_4.exo). Note that the P-Term enabled version of this FPGA is reported by the Xilinx simulator to run at ~51 ns, so using the same assumptions as above it should still be OK (recall that the old version ran with the later TRM Clock with no errors), but we will need to check it carefully. We should be ready for the possibility that we can't move TRM Clock to the desired location. The only group negatively impacted by this is muon, and I don't think they are in a position to understand whether this is a problem or not. We should keep in mind that once muon knows their situation, we may be able to run TRM Clock exactly in phase with Tick Clock, which would make our lives somewhat simpler. One interesting point to note is that the FE Busy's currently seem to be OK. Recall that these are latched in the FE Busy FOM. I wonder if we should consider latching the Exposure Group outputs in the AONM as well? What would be the ramifications of moving the wall of latches at the TDM input to the outputs of *all* of the cards that feed TDM's? Recall that we have relatively more time available in the 2nd half of the FW pipeline than in the first half, because we aren't "losing" the delay between the TRM Clock and the Tick Clock in the 2nd half. Is this a way to take advantage of that mismatch (by essentially "moving" the wall between the 2 halves)? Is there another way to take advantage of this fact? We could define a special TDM Clock but that is not very attractive. The new, faster AONM is in the EG cards (slots 5 and 12) but we still have the same problem. It typically runs for several thousand loops and then one of the EG signals fails to turn off in time. It seems that it does now take longer to generate an error (it sometimes makes it for ~10,000 loops or more before there's an error), but there is still definitely a problem with both EG U and EG L. 29-Nov-1999 More work with SCT and TRM clock offset at +2 The errors seem to be related to EG Partial Enable Upper and Lower: Loop ST Slot/Chip read expect ---- -- --------- ---- ------ 635 79 7/6 0x17f8 0x15f8 6270 127 4/16 0x0278 0x0078 2293 105 5/7 0x6ffe 0x6bfe 4579 109 5/8 0x1678 0x1278 1752 85 6/6 0x4478 0x4078 3186 119 4/14 0x0278 0x0078 44 110 5/12 0x4260 0x4060 3258 126 4/12 0x6fa0 0x6ba0 Then a couple of times, this is a whole string of errors, 1951 11 11/5 0x3e60 0x3c60 31 10/16 0x0660 0x0460 75 17/15 0x57f9 0x55f8 Not a typo, 2 errors here 112 4/1 0x6e78 0x6c78 7816 111 5/16 0x57f9 0x55f8 Not a typo, 2 errors here plus the 2 FOMs and FOM++ (and some scaler problems as well in the last case). Philippe: It seems that the exposure group decision doesn't make it on time to be latched at the TDM. Most of the time it doesn't change the outcome of the trigger decision (= 1 bit error) and sometimes it does (= 2 bit errors). Steve: This error only apparently affects the EGPE, not the FE Busy or the AO Fired. Recall that the EGPE is fed to all TDM's, while each AO Fired goes to a single TDM (i.e. the EGPE sees a higher load). 24-Nov-1999 Testing the framework with the TRM Clock at Tick Clock + 2 (up until now we have been running with TRM Clock = Tick Clock + 1).... It doesn't quite work. Specifically, loop 313 TDM ST 99 (Slot 5, chip 13, reg 36) read 0x6e78 and 0x00a4 expected 0x6c78 0x00a4 reinitialize, loop 2131 TDM ST 107 read 0x4660 and 0x00e0 expected 0x4460 and 0x00e0 DATE: 18,19-NOV-1999 At: Fermi TOPICS: Work on installing L2 FW Cards brought to Fermi for the L2 FW: FM 05, 08, 09 TRM 03, 16, 24 AONM 16_B, 17_B, 18_B, 19_B, 20_B FOM 21_B, 22_B, 23_B, 24_B 500 ft of the Times Microwave Cable The 3 Pass-Through cards for the L2 FW are at Fermi but they need the clamp boards. AONM-19B is coming back to MSU. The Card Species LSN rotor switch is soldered on up side down. So this leaves as "spares" at Fermi: FOM-09B, and Gated SM 1, 52, 55, 57. All 5 of these cards have HSROCB's installed. These 4 gated SM had been in the bottom of M122 where the Foreign Scalers were originally going to be. Last trip was the fix the Fermi TCC PC Power Supply adventure. Cable in the And-Or Input Terms and the Individual Disables. Pull all of the Run 1 FW type cards out of the spare card storage cabinet and bring them back to MSU. This includes 4 TLM's for the Run II L1 Cal Trig timing signal distribution. Also pull the lower (i.e. one of the two 20 slot card files out of the spare card storage cabinet so that there will now be room for a 9U storage section. The newest version of SCT "TRICS V6.2 After" does work OK with the version 18 of the TDM FPGA. This TDM FPGA does not latch the Correlated Global Disable number 3 signal and this version of SCT never allows the TDM to obey this disable. Tested download from power up and 10k's of loops of SCT and all is OK. In the scratch directory Kirsten made a DCT file to put a configuration into each of the cards in M122 Bot, i.e. the L2 FW. This was just to prove that these cards were still alive after their trip to Fermi and that all the address switches were setup OK. DATE: 3,4,5-NOV-1999 At: Fermi Topics: Install Build B AONM's, Talk with Reiner about L1 Cal Trig Analog stuff, Talk with Marvin. Trip to Fermi to install the AONM Build B cards and the HSROCB cards on all the necessary boards. To add interest the Fermi TCC had its power supply die (probably related to a power outage at Fermi). Still need to measure the setup time of the signals that we send to the SCL Hub Controller with respect to the SCL Frame Clock used by the Hub Controller. Brought the label maker to Fermi and will leave it here for now. In my haste at MSU to get the Build B cards ready to bring to Fermi I installed HSROCB's on all the AONM's as well as the FOM's. The current version the the rack layout drwaings does not show that the 6 AONM's in the top rack of M123 actually need HSROCB's but because they are installed I will leave them on. With the Build B AONM's in the top crate in M123 we no longer have the long wait after DC power on before the LED's on the TOM indicate that all of the FPGA's are configured. So the assumption is that one of the 7 Build A AOMN's pulled from Top M123 was the source of this slow FPGA configuration. Need to bring alcohol and Q-Tips to Fermi. After the new Build B AONM's and all the HSROCB's were installed make a sweep of the power supplies checking voltages at the TOM front panel test points. The previous check of this is in the 19,20-MAY-1999 log book entry. Everything was on and configured for this test. M123 Top +5.021 +3.318 -1.999 -4.493 Mid +5.018 +3.321 -2.003 -4.500 Bot +5.029 +3.355 -1.997 -4.495 M122 Top +4.996 +3.332 -1.893 -4.366 Mid +5.017 +3.318 -2.019 -4.519 Bot +5.033 +3.303 -1.997 -4.526 Had trouble with Build B AONM SN# 05_B when used at the location for Spec Trigs 127:64 And-Or Input Terms 255:128. It had Scaler Increment Errors for Spec Trig's 112,113,114,115. For these 4 Spec Trigs the read back Scaler Increment value was different for each one and not the expected value. A guess is that this is another example of a scaler problem in a specific single FPGA. OK replace Build B AONM SN# 05_B with SN# 01_B in M123 Top AONM for Spec Trig 127:64 Input Terms 255:128. This AONM (01_B) is working just fine but there is the possibility that 05_B is also OK and that we were just having other software problems. When pulling the Top Crate in M123 apart it goes pretty easy if you start at the right hand (slot 21) side of the crate. Summary of tests on Friday morning: Config via TRICS 6.2 and then try to FW Init via TRICS 6.2 and Init blows up at M1 Slv 0 Slt 10 Chp 1 Rg 32, and 25 followed by the other 17 chips on this card. Config via 4036 capable TRICS 6.1 FW Init via 6.1 Run SCT under 6.1 on everything but the TRM for Glb Disables. This is all OK. Power off and then back on and Config via Trics 6.2 and verify that registers exist at M1 Slv 0 Slt 10 Chip 17 Reg 8 and Chip 1 Reg 25 & 32. All these registers exist. Then try FW Init via TRICS 6.2 and it blows up as described above; the registers are gone. Config under 4036 capable Trics 6.1 using TDM exo 19.1 FW Init under this 6.1 Run SCT on all cards under 6.1 Run 1 Hz trigger under 6.1 All is OK. We did this from power up to prove that things would be OK on Monday. We will stay this way. A good way to watch the Spec Trig #1 run is to do register reads Mst 1 Slv 1 Slt 11 Chip 1 Reg 40,41. Run the SCL cable up to the 3rd floor Fixed counting house to Daniel Mendoza's lab space. He is working on the VRB controller. Will bring the Build B AONM SN# 05_B back to MSU. Will leave one spare Build B card here. It is paneled as an FOM and is SN# FOM 09_B. For now it is stored in the bottom crate in rack M101. List of FW issues that are left open: 1. Test the most recent TRICS 6.2 2. Plug back in Build B AONM SN# 05_B to see if it really has a scaler problem in one FPGA. I'm brining this card back to MSU so that we can test it there. 3. Test running with TRM Tick Clk set 2 RF buckets after FW Tick Clk. 4. Install the cabling for the "Skip Next BX" move to TDM 18.1 get the Single Signals document going in a serious way. Talked with Reiner Hauserabout the L1 Cal Trig Analog stuff. Chip's new post Doc from Canada who will work on D-Zero is named Dugan O'Neil. He was also here this week talking with Roger and Dylan Talked with Marvin. He went to the Lehmann Review close out. D-Zero will roll in in March of 2001 whether it is all finished or not. Management must decide how to best use resources to finish the most important parts of D-Zero. D-Zero is very visible at DOE (too visible). CDF would only require a 1 month shutdown to install their Si detector after roll in. D-Zero would require a 5 month shutdown to do the same. DOE does not care about 1 month shutdown but would panic at a 5 month shutdown. So the Si and Fiber detectors must be built and installed before roll in even if this requires pulling people out of the electronics and softare development for these systems. The readout electronics and solftware could always be installed later. Marvin says that the 2nd floor is about to go together fast. Work will start at end of Nov and only take a couple of months. He want the SCL cable list. Date: 20,21,22-OCT-1999 At Fermi TOPICS: Work on SCL, Meeting with Marvin, Ted, Neal, and Trigger Meeting at NIU. Last trip here I made a measurement on the Hub Controller of the difference in time between when the LSB of a Tick number changed and when the clock arrived at the receiver latches. But I never got this number written down. But order of magnitude it was 20 or 30 nsec of hold time and lots of setup time. But this meant that the Master Clock Signals that go from the FW to the SCL Hub Controller were changing right when they were being clocked in. So based on this Kirsten moved the SCL Tick Clock two RF Buckets later. Kirsten has loaded the new clock setup that fixes the missing tick in the SCL Tick Clock and moves the SCL Tick Clock to RF Buckets later. With the SCL Receiver on its Tester Board we watch Tester Board Connector #2 pins 9,10,11,15 i.e. SCL Ready, Link Error, Data Error, and Sync Loss. With both a long and a short coax we see the following: SCL Ready goes up and down with the 7 MHz either running or not. Link Error and Data Error are both low (watched for periods of greater than 5 min) unless you do something to make an error then they latch voltage high. Sync Loss appears always voltage low, even with the coax unplugged. Only time I see it high is for a glitch during power turn on and off. The guaranteed way that we can get Dean's crate to sync up is for him to assert and then remove the SCL ACK signal and then I stop and then restart the 7 MHz. This is the current official way to sync up. We are sending L1 Accepts to Dean's Controller and it is properly responding to them. He also sees the SCL Initialize message. We can see the L2 Busy coming back from Dean as bit of value 4. When we had an L1 sync problem then we could also see the L1 Sync Error signal coming back from him (bit of value 2). We always see the bit of value 16 coming back from him. This is GB Sync Error. But what is GB Sync Error. We also see the "Cable Disconnected" bit, bit of value 256 when the cable is not plugged in. Note right now I have it plugged into Channel 0 of the Concentrator card so the Status Information can be read at address $80 0700 or via the vertical interconnect bit 3 stuff this is at $1980 0700. OK questions for Ted and Neal: Need definitions of: SCL Ready, SCL Link Error, SCL Data Error, Sync Loss, and GB Sync Error (coming back to the Hub-End on a Status Line). Need to make a new measurement of the setup and hold times at the Hub-End Receiver Latches. Run for 2 hours with the FW pumping 1 Hz L1 Accepts at Dean's controller and his stuff giving L2 Accepts to all of them and reading them out of his ADC's. We watch to see that the SCL Receiver does not report and Data Errors which we believe that it will latch if it ever sees one. So on the Shea Console we are looking at the first word at 77:10FF0088 This is normally $AC90. The bits of the "A" are msb SCL Ready, SCL Link Error, Sync Loss, SCL Data Error lsb. It is reading Ready and Sync Loss. Sync Loss reads HI because of a broken trace on Dean's Controller. It is really low. After 2 hrs the two latched error signals are still low. When I turn off the Hub-End power the "A" became a 7. On the Fermi machine D0TCC1 in the rio directory fix the file tdm_1_hz.rii so that it first loads the VME registers for the precaler shift register and then loads the data into the shift register. I did not fix the old rio file trigger_1_hz.rio that is doing things in the backwards order. A good way to print from Kirsten's Sun to the HP printer by the wall between the terminal area and the control room is just to: lpr filename That is this is setup as the default printer. The explicit way to do it is: lpr -Pdab1_hp8000 filename. Meeting with Bill Haynes and Ted and Neal. We will get a new receiver card that incorporates the new AMCC parts so it will be just like the latest Arizona Muon receiver. The Fanout card is going to be changed so that AMCC bucket zero of each SCL Frame is used to send an AMCC Synch Character. This should both help hold the link in sync and help it instantly resync. Note that the reception of this AMCC Sync Character will both sync the AMCC part to its serial input and it will cause the De-Multiplexer in the receiver FPGA to move its pointer so that the next bucket of AMCC user data will go into Bucket #1 of the SCL Frame. The following are approximate definitions of what the link management signals will mean on the new receiver card: SCL Ready not latched goes up or down depending on whether the receiver is getting FW data or a continuous stream of AMCC sync characters. When the receiver is getting continuous AMCC sync characters then it does not drive its 7MHz output. SCL Link Error This is asserted if either the AMCC receiver is not locked to its serial input stream or if the receivers check sum comparison circuit has found 3 consecutive SCL frames with data errors. Note that this condition is latched. SCL Data Error Is generated frame by frame and it available at the same time as the rest of the SCL data for that frame. This is the un-latched output of the receiver check sum comparison circuit. Sync Loss input pin to the receiver mezzanine just comes back out on the RS485 Status line called GB Sync Error. I expect that this is a typo that should be GS Sync Error. Standard practice will be for people to drive this input pin with the SCL Link Error signal coming out of the SCL Receiver mezzanine. Dean is modifying his controllers FPGA to make a latched copy of SCL Data Error. Run for 4 hours with this on Thursday night and see no errors. This should be showing us single bit single frame errors. Friday morning Trigger meeting at NIU. I talked with Fred Borcherding and Marvin. Yes, they need a VRB mode that allows transport of random user data, no inband control characters. Paul Grannis asks me what can we do with cosmics for commissioning. Friday afternoon, Ted/Neal have delivered the new receiver and transmitter. This is the latest AMCC receiver stuff and the transmitter uses the Synch character in bucket zero of every SCL frame. We can now leave the 7 MHz clock running in he Hub-End Controller and Deans crate syncs up OK. Move Dean's Proto-Type Controller to the 3rd Floor and then run the string the whole way, FW, SCL, Deans STuff, VRB, L3, Examine. DATE: 20-OCT-1999 At: Fermi TOPICS: L1FW Initialization and TDM.exo Changed the downloaded version of the TDM FPGA to 17_1. This change was propagated to the D0_conf directory at MSU, but NOT the MSU_conf directory. Ran 6000 loops of SCT to verify that everything is still ok. Also modified the post initialization .mcf file to call a .vio file which enables the SCL 7 MHz clock. Again, this change is reflected by the D0_conf directory at MSU but not the MSU_conf directory. DATE: 19-OCT-1999 At: Fermi TOPICS: Repair to Master Clock Fritz implemented the new version of the clock code. The missing tick in the SCL Tick Clock has been fixed and the SCL Tick Clock has been shifted 2 RF buckets earlier (from an offset of +5 to an offset of +3). Ran 10,000 loops of SCT to confirm that everything else is still happy. Date: 6,7,8-OCT-1999 At: Fermi Topics: Trip to Fermi, Deliver Becane, Work on SCL, Meeting with Ted and Neal, Master Clock problem, work with Fritz. Brought down 5 boxes of stuff for L2, mostly Bit 3 stuff I think Work on SCL, first good transfers to Dean's Cal Controller. Worked with L3, successful L3 Transfer Number transfer to L3 Brought down becane, it becomes Host Name D0SUNMSU1 IP Adrs 131.225.224.5 Gateway 131.225.224.200 Subnet 255.255.0.0 DNS 131.225.8.120 Seconday DNS 131.225.17.150 This is in Kirsten's office with phone number x8751 Lend the readout VIPA crate Power Supply to L2. This is Power Pan SN# 8. ECB meeting, Muon has a problem with single tick Sync Gap during SCL Initialize, details not yet clear to me, sounds like single tick Sync Gap is OK with them during actual running. Recall that the outputs from the FOM++ in slot 16 go through the P3 section of the backplane at slot 20. Recall the current mapping of the Global L1 Fired Strobe out of the FOM++ MSA_Out 36 to SCL Hub-End --> SCL frame with an L1 Accept MSA_Out 37 to L1 FW Helper MSA_In_0 to generate Capture Data signals MSA_Out 38 to L1 Fired Scaler, Slot 19, FPGA 16, Ch 0 MSA_In_122 this is individual control signal 0 for this scaler. MSA_Out 39 to L3 on the 17th pair of the cable carrying 16 bits of L1 Fired Scaler, for now aka L3 Transfer Number. Meeting with Kirsten, Ted, Neal, and Dan. They will work on making the SCL Receiver so that it can sync up when its power is turned on without needing the SCL stream to stop. Fritz agrees to show Kirsten how to edit and compile the C program for loading the Master Clock. This is necessary to fix a missing Tick in the SCL_Tick Clock that happens at right about the same time as the Beginning of Turn Marker is issued. DATE: 29,30-SEP & 1-OCT-1999 At: Fermi TOPICS: Trip to Fermi, L3 Transfer Number, Get Kirstens office, Bring to Fermi a VIPA Crate Bring to Fermi a VIPA crate in a Box for L2. I delivered this VIPA crate to PREP: Carl Shirtziner and Adam Walter, in the Feyman Computer Center. The idea is to use a gated scaler to count the L1 Accepts (which are coming at 1 Hz) and provide the output to the L3 as the Transfer Number. AT FERMI config/M123_Bottom.dcf has been modified so that the scaler in Slot 19 is downloaded. Also, there is an rio file (and supporting rii file) in the Scratch directory which sets up scaler channel 0 of FPGA 16. DATE: 29-SEP-1999 At: Fermi TOPICS: SCL Clocks The Fanout module was not firmly seated. Now, without our cables plugged in, when the 7 MHz clock is enabled the gold LED on the Fanout comes on (so the 7 HMz is received) and the red LED stays off (so the Fanout is happy with the 7 MHz). The behavior when our clock cables are connected has not changed. Also tried aligning the rising edges of the 53 MHz and 7 MHz clocks. The behavior when our clock cables are connected still doesn't change. DATE: 21:22-SEP-1999 At: Fermi TOPICS: SCL VME Access and Clocks Master Clock control SCL Hub Controller now requires that the 7 MHz clock be enabled. The new version of the D0 Trigger System Description on the web includes this change. The first problem was talking to the Hub Controller. This was tracked down to a discrepency between the address modifiers the Controller would accept and those issued by the Vertical Slave. Neal modified the Controller to accept the address modifiers sent by the Vertical Slave. (The Tester Card has NOT been modified yet although the new programming in principle exists.) VME communication now seems to work most of the time. (Occassionally it still gets into a situation where the slave is transmitting but the Controller is not answering.) Now try enabling the 7 MHz clock. Power up, no clocks connected to the inputs. (It doesn't seem to matter if the 64 pin cables are connected or not at this point.) Read status register: 0x1980 0000 returns 0x00c0 this is right (see web document) Plug in clock cables Read status register: returns 0x0040 this looks wrong think it should be 0 Enable 7 MHz: 0x1980 0004 write 0x0002 Read status regsiter: returns 0x0060 think it should be 0x0020 LEDs on Fanout module to indicate that it's receiving the clock and that it is not happy with the clock are both OFF Disable 7 MHz: 0x1980 0006 write 0x0002 Read status register: returns 0x0040 | Disconnect clock cables | | Enable 7 MHz: 0x1980 0004 write 0x0002 | | Read status regsiter: returns 0x00e0 which is ok but | LEDs on Fanout module to | indicate that it's receiving the | clock and that it is not | happy with the clock are both OFF I think that when Neal downloaded the new programming to change the VME address modifiers, he also tried enabling the 7 MHz (using the on board clocks) and that it worked correctly. "Details" that Neal mentioned: 1) the front inputs haven't been tested 2) among other things, the delay between the clock and the data may have to be adjusted 3) for the clock cables, they expect the positive ECL on the center pin 4) they also expect the rising edges of the 53 MHz and the 7 MHz to be at the same time Master Clock: To kick the Master Clock 1) log on to t-d0-mch1 2) login as ioc 3) type the following: connect 16 4) type: sp clkSetup 5) repeat #4 until the clock works DATE: 15:17-SEP-1999 At: Fermi TOPICS: Work with new Master Clock Setup, New FPGA Configurations, New TRICS, and new file organization and try to get SCL working. Global L1 Spec Trig Fired (Strobe) is made by the FOM++ and is currently being sent two different places via single signals. L1 Spec Trig Fired Strobe aka Global L1 Accept Destinations ------------------------- ------------------------- FOM++ MSA_Out_36 ---> SCL Hub-End to Hub Controller Connector #1 pins 1,2 FOM++ MSA_Out_37 ---> L1_FW_Helper FM card MSA_In_0 Used as a stimulus for the generation of Capture HSRO and Capture Monitor Data Recall that the FOM++ generating this "Global L1 Accept" could be programmed like any other FOM so that its output signals is asserted just for a subset of the L1 Spec Trig's. SCL Initialize is carried via single signals to a couple of consumers of it. SCL Initialize Generated by the SCL_Helper_Function Destinations --------------------- ----------------------------------- MSA_Out_45 ---> SCL Hub-End Hub Controller Connector #1 pins 3,4 MSA_Out_47 ---> Tick&Turn SM for Current BX Num and Geo Sect L1 Trig Num MSA_In_1 From Ted and Neal: On the Hub Controller board the top Trompeter connector is for 7 Mhz and the lower Trompeter connector is for the 53 MHz. The top 64 pin connector is for the L1 Trig Num cable and the lower 64 pin connector is for the Current BX Num cable. On the Fanout Boards the Red LED (the lowest LED on the front panel I think) when it is ON it implies that the SCL Tick clock is wrong. The Yellow LED on the Fanout (next to bottom) when ON implies that the Fanout is getting 7 MHz Clock (SCL Tick Clock). The Yellow LED on the Receiver Mezzanine when ON implies that the 1 GHz serial data coming in is OK. From Fritz to run the displays for the CMC Sequencer and Phase Coherent Clock from d02ka do the following. cd /d0chb/home/room3/bartlett/work/onl_utility/scr/clock/python clock.py D0PCC D0MASTCLOCK& From Dean: A possible plan is to use the Luminosity Index Num along with the L3 Transfer Num to give events a unique event number for all of Run II. This required that the Luminosity Index Num be unique for a long period of time and that it change ofter enough that you are sure that the L3 Transfer Number has not rolled over. They talk about possibly incrementing the Luminosity Index once every 10 seconds. There is the issue that events from a given Lum Index would never span "files", and they have to change often enough that you can close a file when you want to. Phone Numbers: Fritz Bartlett x4058 Neal Wilcer x2749 Ted Zmuda x2154 Looked at the signals on the two 64 conductor flat cables that go to the Hub Controller. Things are more or less rational. For example the LSB of the Current Beam Crossing Tick Number lines up with the BOT Marker. You can tell because the LSB of the tick hangs high for two ticks. You can also trigger the scope on the BOT and then use one channel to look at the LSB of Current BX Tick and the other channel to look at the LSB of Goe Sect L1 Trig Num Tick. This lets you directly see the offset between the two numbers. We need to study things carefully with the logic analyzer. One funny thing is comparing the transition times of the "Marker" signals with the transition times of the Tick signals, the Markers appear to move about 25 or 27 nsec before the Tick bits move. I do not understand why this should be this way. Both should be updating on FW_Tick_Clk. Checked the length of the SCL Init signal going to the Hub-End. It is about 60 usec long and appears to be of a couple of different possible lengths. DATE: 26,27-AUG-1999 At: Fermi TOPICS: First Test of SCL Hub-End at D-Zero, Meeting with Dean about Trig Pick-Off signals, Talk with Dave Cutts, Run SCT and Random Register Test Neal installed the J3 backplane in the crate, checked voltages and installed their modules including the receiver test module. The first test will be to see if Bob Angstadt's test routine will work over here. Send a note to Bob about the PC to VIPA VME path and address map and such. Ran the Random Reg Test to the MVME-214 in that crate and all is well. Wrote a note for them about how to power up and turn off that crate and its safety issues. Note that they want the -4.5V to run at -5.2V. The next big push will be 15th Sept. Dean will bring his controller card at that time. Need to have control of Master Clock by that time. Dean needs us to: do the Initialize Sequence, provide crossing numbers, and provide low rate triggers. He does not need L2 Acpt/Rej right away. Send a note to Bob Angstadt about the address mapping in the SCL VIPA crate. Send a note to Neal about cable length to Dean's test setup and ask him about a new program to make a formatted display of the data from his test card. Send a note to both about power up of the M124 SCL VIPA crate. Trig Pick-Off Signals. First for the EM and separately for the HD section of each CALORIMETER Tower there is an 8 input summing amp with a gain of -X. This is followed by an EM and separate HD 4 input summing amps to put the 4 Calorimeter Towers into a Trigger Tower. So it is in the first amp that you have to properly weight the signals from the various depths of the Calorimeter. The four resistors going into the 2nd amp just pick the relative weighting of the 4 cal towers in the trigger tower. Dean has the cable length information, the Spice models, and the 50k capacitances of the calorimeter ready to hand over. There are 8 different pre-amps not counting EC EM3-4. EC EM3-4 by itself has another 8 types. Big issue of the new Run II dead material in front of the Calorimeter. What is the sampling fraction of the first part of the calorimeter. There are now 2 radiation lengths in front of the calorimeter because of the magnet and the pre-shower detector. So we run spice and do the sampling fraction thing to get the GeV deposited moved into volts out of the preamp. Then knowing the uamps to volts out of the 8 input summer and what its dynamic range is you can pick its resistors. Then the next stage but need to know how we want the signals in the transmission line to look: E or Et or somewhere in between. Remember this is AC coupled stuff. Amp-Out --> cap (10 nFd) --> series term resistor --> coax cable run --> term resistor (match to other resistor) --> capacitor (match to other capacitor) --> ground. You high impedance look at the signal at the coax to resistor node. Dean will time his stuff by doing a 3 sample readout mode (the actual tick, and one before and one after. How does trigger time in? Set a timing and make a Precision Readout vs Trigger readout scater plot. Change the timing and repeat. As expected the injection of the pulser at the Pre-Amp causes problems. The cable length (Pre-Amp to Cal Element) almost matches 132 nsec in time. So for large HD cells the line appears shorted and you have a negative reflection and thus zero net signal right at the point where the trigger wants to sample. This is a big deal because we used this a lot in Run I to find problems. Ran about 100k loops of SCT with no errors. Ran the Random Register Test with some errors: after 1.8 meg loops Read d49a Wrote d49a 2nd try fails M1 S0 Slt3 Cp3 Rg32 after 0.2 meg loops Read 4066 Wrote 4166 2nd try fails M1 S0 Slt3 Cp3 Rg32 after 10 meg loops Read ce78 Wrote cf78 2nd try fails M1 S0 Slt3 Cp3 Rg2 after 9 meg loops Read 5a10 Wrote 5b10 2nd try fails M1 S0 Slt3 Cp3 Rg16 after 1.7 meg loops Read 6ee2 Wrote 6fe2 2nd try fails M1 S0 Slt3 Cp3 Rg25 after 3.3 meg loops Read 067f Wrote 077f 2nd try fails M1 S0 Slt3 Cp3 Rg13 after 4.8 meg loops Read 28b7 Wrote 29b7 2nd try fails M1 S0 Slt3 Cp3 Rg3 In all cases doing a "verify again" still showed the error. I assume that the data was written into the register wrong. DATE: 15,16-JUL-1999 At: Fermi TOPICS: Work on installing equipment in M101, Meeting with Mike Utes, Visit Neal and Ted, Talked with Kate Frame about something to do for the next couple of months, visit with Rob. Installed the shelf supports for 2x Power Pans, 1x cable pass through (2U), installed the blower, the bottom MSU 9U crate, the MSU crate rear support brackets, and the power cable support bars. Need to bring the Greenlee punch to make the holes for the AC power cord gromets. The 3/8" lead holes for these have been drilled. Need to make and bring a 5U grill for in front of the blower in M101. It is 5U because the cable pass-through tray is currently set in the lower of the 2U that are pass-through and spare. Need to bring black paint for the cable pass-through tray and for the blowers. The TDM Paddle Board in Slot #11 of the M123 Middle crate does have terminator resistors installed in all locations. The bottom of the Air Pipe is 15" above M103. The top cable dray does not cover M103 and 1/2 of M104. Their is an Air Pipe support bar in the middle of the part of M104 that is not covered by the top cable tray. There is 13" between the top of M104 and the bottom of this air pipe support. TDM Ver 13 Rev 3 has the same problem. TCC can not reliably write to registers in it, so Single Chance Test crashes during its Initialize stage. Typical failures: Mst 1, Slv 1, Slt 9, Chip 11, Regs 80, 81, 82 and Slt 11, Chip 7, Regs 25, 32, 82. About 1/2 of the time when TCC tries to recover by writing and reading back a second time it goes OK. Talked with Mike Utes about the SCL links to the Sequencer Controllers. These will be in the center 4 racks in the center of the Platform. There are 8 of these links. This was part of the "plan" to send the same SCL information on two links: one to the Sequencer Controller and the other link to its associated VRB Controller. The only problem is that these physical links would be about 150ft long. The Sequencer Controller communicates with the Sequencers via some NRZ codes. This takes some time. As it stands Mike was going to use 806 nsec to get the L1 Accept out to the SVX-II chips. I asked him to talk with Marvin about using this much time to get the L1 Accept to the SVX chips vs the L1 Accept being issued from the FW at tick 27. In the Moving Counting House we are using LMR-200 cable. The runs are about 51ft to the 2nd floor and 67ft to the 3rd floor. To get to the Platform is 150ft. Attenuation in db/100ft ------------------- MHz LMR-400 LMR-200 Ratio ------ ------- ------- ------- 30 0.7 1.8 2.57 50 0.9 2.3 2.56 150 1.5 4.0 2.67 220 1.8 4.8 2.67 450 2.7 7.0 2.59 900 3.9 9.9 2.54 1,500 5.1 12.9 2.53 2,000 6.0 15.0 2.50 2,500 6.8 16.9 2.49 Diameter 0.405" 0.195" 2.08 $/ft $0.64 $0.37 1.73 Talked with Marvin and let him know that we wanted VRB Controllers. On Friday Kirsten and Dan visited Neal and Ted with Kirsten. They were running signals through a full chain. Visit with Rob Marting. Problems with running the Alpha above 500 MHz. It will require replacing the TriQuent phase lock loop multiplier which on the stock boards has a maximum operating frequency of 500 MHz. Big concern about poking at the working L2 cards. If this test is important it may be better to do it to a DEC alpha board. DATE: 24,25-JUN-1999 At: Fermi TOPICS: Meeting with Fritz, See French G-Link tests & L2 test location, Meeting with Andrew Brandt, Meeting with Marvin, Start installation in M101, Master Clk connections Meeting with Fritz. He wants to make another temporary clock program. He wants to make it so that at network load time one supplies a series of characters to control the offsets of the various fixed timing patterns. I got no where. Fermi Stock Numbers: High Density Camac Kluge Card 1440-301000, Unistrut track for 45U rack 1775-215000, Long shelf for rack 1775-230000. Recall the location of the vertical bar (yellow bars) mounting holes. Use the 4th and 20th holes from the back of the rack and the 2nd hole from the front of the rack. This puts the back two bars 8" apart center to center and the front and middle bars 16 1/2" apart center to center. Get the vertical bars installed in M101 and the front build out installed on it. Get from the stock room: 8 vertical bars, 4 high density camac kluge cards and 12 shelf chassis supports. Meeting with Andrew Brandt. EM Cryo Obj and Jet Cryo Obj now understood to just be the classic Run II eta information signals. Will send note to them Monday. French FIC Test. Suggest they move the BIT-3 to slot 1 of the VIPA crate and then they can talk to the crate. Pointed them to the VIPA backplane schematics. Bob Hirosky was having the same problem with Bit-3 PCI Expansion and VME crate power off hanging the PC that Philippe saw. The error the Jean-Francois sees is the error line on the G-Link Receiver pulsing on and off. I tell him that we have not looked at it but will try doing so. Talk with Marvin about phase noise in the current PCC possible causing serial link problems. Need to send him the references. Run a couple of 100k loops of SCT. No problems. Normal Top M123 TOM lights stay on at power up. DATE: 17,18-JUN-1999 At: Fermi TOPICS: More tests of FW Timing, Carmen Master Clock Cables to SCL Hub-End, Talk with Mary Anne Cummings about L1CT Simulator, Talk with Fritz about Master Clk Program Before changing the FPGA code, and this trip armed with the logic analyzer, I need to verify using last trips new V5.7 SCT and new FOM configuration that things still look the same at: Helper Clk is 1' delay from Tick Clk, i.e. what was called 39 nsec timing on the last trip. Still No errors. Check Tick Clk positive edge to Helper Function signal positive edge and the logic analyzer reads: 40, 35, 35, 35, 35, 35, 35 nsec. So this is the same as last trip. Helper Clk is 1' + 46" from Tick Clk, i.e. was was called 45 nsec timing on the last trip. Yes, still BigTimeBlowUp. Yes, logic analyzer says that the Maginot Lines are stuck Hi. On a couple of sweeps I can see Maginot go HI and the other timing lines that I expect to cycle (e.g. capture HSRO data) do not cycle. On the two sweeps that I see Maginot go HI measure Tick Clk positive edge to Maginor (i.e. a Helper output) positive edge and it is 45, 40 nsec. So all is the same as last week. Helper Clk is 3x 46" + 157" + 10' from TRM Clk, i.e. what was called 113 nsec timing. Things look the same: it fails to initialize with error from TRM Geo Sect Busy 64:127 Monit Data for terms 72:75 Read 02f2 Instead of 00f0. Note this is a slight change from last week but still a SCT Initialize error from TRM for Geo Sect Front-End Busy. Logic analyzer showed 110 110 nsec Tick Clk pos edge to Maginot pos edge. Bring down the new TRM_22_2.exo and HELPER_7_1.exo. First edit the TRM.dci Using the new TRM and old HELPER and 113 nsec helper clk delay it now dies during SCT Initialize with a TDM error instead of a TRM error. Specifically: TDM for spec trig 0:15 Monit Data for spec trig #12 read 5775 & 0000 instead of 7fff & 0000 Move to about a 90 nsec helper clk and pass 5k SCT loops, so new TRM looks OK. Because the new TRM looks OK and it looks like it probably improved things, try to fix the TDM problem that repairing the TRM apparently uncovered. Try running with TDM ver 13 rev 2. This has problems: Using TDM_13_2 a number of sites fail during the initialize cards part of SCT Init. They have post write checks which are "fixed" about 1/2 of the time when trics tried to write for a second time. So at the sites where TDM_13_2 appears to have made FPGA registers that have read error configure TDM_13_1 over the top of TDM_13_2. The failing sites were: slot 9 chip 11 then slot 7 chip 12 & 14 then slot 6 chip 8 then slot 5 chip 11 Ok now most of the time it makes it through the "initialize the cards" part of SCT Init. The next part of SCT Init is to kick the helper and then verify the initial state of all the cards. Here it fails at the TDM for Spec Trig 0:15 with Monit Data problems for Spec Trig #12. But the Helper Clk is set for 90 nsec so it looks like TDM_13_2 has worst timing for collecting its data than TDM_13_1 does. So quit using TDM_13_2 and go back to TDM_13_1. Now work on the new HELPER configuration to see if it cures the "islands of Big Time Blow Up" problem. So edit the helper.dci to start using HELPER_7_1 exo. Working with this weeks new TRM and HELPER and the older TDM that is TRM_22_2 HELPER_7_1 TDM_13_1 and with helper clock derived from Tick Clock, Search for islands of Big Time Blow Up. Recall that the delay is measured from TICK Clk positive edge to Maginot Line positive edge. measured Cable delay ------------------------- ----------- 1.0' 36 nsec | 2' 2x 1' 37.5 | 3' 3x 1' 40 | 3.8' 1x 46" 42.5 | 4.8 1x 1' + 1x 46" 42 | 5.8 2x 1' + 1x 46" 45 | 6.8' 3x 1' + 1x 46" 46 | 7.7' 2x 46" 46 |-- No SCT Errors 8.7' 1x 1' + 2x 46" 48 | 9.7' 2x 1' + 2X 46" 50 | 10.7' 3x 1' + 2x 46" 52.5 | 11.5' 3x 46" 54 | 12.5' 1x 1' + 3x 46" 53.5 | 13.5' 2x 1' + 3x 46" 56 | 14.5' 3x 1' + 3x 46" 59 | 34.6' 3x 46" + 157" +10' 90 nsec | And for comparison make a few check with TRM clk being the Helper Clk source: measured Cable delay ------------------------- ----------- 3.8' 1x 46" 61.2 nsec 34.6' 3x 46" + 157" +10' 112 nsec error at SCT Init Verify Init State, TRM Geo Sect FE Bz 64:127 Monitor Data errors So I was not expecting a TRM error with this timing but need to explore this more. OK now explore things near the long end of helper clock timing. Once again measure things in M123 Bottom with the logic analyzer where the measured delay is TICK Clk positive edge to Maginot positive edge. Recall that we are running the new HELPER_7_1 & TRM_22_2 but the old TDM_13_1 measured Cable delay ------------------------- ----------- 34.6' 3x 46" + 157" +10' 90 nsec | <-- TICK Clk is the source 26.9' 1x 46" + 157" +10' 98 nsec | <-- TRM Clk is the source 27.9' 1x 46" + 157" +11' 100.5 nsec | <-- TRM Clk is the source ---- above here no errors 28.9' 1x 46" + 157" +12' 101 nsec | <-- TRM Clk is the source With this delay it will Initialize but always dies in a loop or two. The errors are: AONM part spec trig fire sclr inc AONM part exp group fire sclr inc FOM L1 Geo Sect Accpt Scaler inc Aonm part exp group monit data See the log closed 13:00 18JUN99. 30.8' 2x 46" + 157" +10' 105 nsec | <-- TRM Clk is the source 34.6' 2x 46" + 157" +10' 112 nsec | <-- TRM Clk is the source With these delays it will NOT Initilz Always TRM Geo Sect FE BZ monit data errors. So it is not 100% clear to me why with the old HELPER we saw it work with slightly longer delays and then the TDM die first and now with the new HELPER it does not work with quite so long a delay and the TRM is back to dying first. Leave it running with a single 46" cable from the TRM clock. This gives a 60 nsec delay from TICK Clk to Helper outputs which is right in the middle of the known island free range. The cables from the Master Clock to the SCL Hub-End are 32 ft long. I made a bundle of 6 of these Trompeter cables. 32 ft may be a bit on the long side but this came from cutting our old 65 Ft cables in two. We can shorten them if necessary. "Installed" but need to finish their routing in rack M100. As has become normal the M123 TOP crate hung for 30 seconds or so when first powered up. Next week Thur at 10AM with Fritz to "learn clock code". DATE: 3,4-JUN-1999 At: Fermi TOPICS: OnLine Workshop, Work on L1FW, FW Master Clock Timing study, visit SCL, Deliver Epoxy to IB4, Commissioning Meeting. Kirsten,Roger,Philippe,Dan at Fermi. Kirsten works with the new version of FOM configuration and the new version of SCT that run the Helper Function in the way expected by its FPGA. With these new versions installed we need to explore the range of Helper Function Clock cable delay over which SCT will run without errors. Old SCT and Old FOM configuration: Error free with a 7.7' delay. Old SCT and Old FOM configuration: With a 20.8' delay, failed with FOM scaler error (off in the hundreds digit) at loop 513. Old SCT and New FOM configuration: OK with 20.8' delay cable. Old SCT and New FOM configuration: With a 30.8' delay cable it failed with TRM problems. Old SCT and New FOM configuration: With a 20.8' + 46" Big time blowup just like when Helper hangs a line hi. But note this is 19 nsec more delay than the classical place where Helper hangs hi. Old SCT and New FOM configuration: With a 13.8' delay. Big time blowup. This is the classical place for Big time helper hang hi blow up. New SCT and New FOM configuration: With a 13.8' delay. No error in 40k loops. New SCT and New FOM configuration: With a 3.8' delay. Big time blow up. Is this Helper hanging hi ? Can't tell because no logic analyzer. Old SCT used to run OK with 3.8' delay, see 2 wks ago. New SCT and New FOM configuration: With a 7.7' delay. No error in 4k loops. New SCT and New FOM configuration: With a 10.0' delay. No error in 5k loops. New SCT and New FOM configuration: With a 17.7' delay. No error in 6k loops. New SCT and New FOM configuration: With a 21.5' delay. No error in 5k loops. New SCT and New FOM configuration: With a 23.1' delay. No error in 5k loops. New SCT and New FOM configuration: With a 26.9' delay. Big time blowup in 5 loops. New SCT and New FOM configuration: With a 30.8' delay. Error during Initialize. TRM Geo Sect Busy 0:63 Monit Data for terms 48:51, Read 00f2 Instead of 00f0. New SCT and New FOM configuration: With a 34.6' delay. Exact same initialize error as with 30.8'. New SCT and New FOM configuration: With a 3.8' delay. Big time blowup in a few loops. New SCT and New FOM configuration: With a 1' delay. No error in 6k loops. So it is running OK with a Helper Function Clk that is generated by a 1' cable delay from the TRM Clk. So the only way to move to an even earlier Helper Function clock is to derive it from the Tick Clock. OK have now switched to using the Tick Clock as the source of Helper Function Clk. New SCT and New FOM configuration: With a 1' delay. No error in 5k loops. New SCT and New FOM configuration: Try a 1' delay from the Tick Clk again the next day just to make sure all is OK. No error in 5k loops. New SCT and New FOM configuration: With a 3.8' delay. No error in 5k loops. I half expected this to cause a blow up. Stop here and triple check that 3.8' delay from TRM Clk causes it to blow up. Yes it does. New SCT and New FOM configuration: With a 4.8' delay. Ah yes, this causes it to blow up big time within a few loops. New SCT and New FOM configuration: With a 7.7' delay. No error in 5k loops. New SCT and New FOM configuration: With a 8.7' delay. No error in 10k loops. New SCT and New FOM configuration: With a 11.5' delay. No error in 5k loops. New SCT and New FOM configuration: With a 12.5' delay. No error in 9k loops. Now using just new FOM configuration want to double check the differences between new and old SCT at 4 different Helper timings, all TRM Clk derived Helper Clk. All of the blow ups happen within a few loops (perhaps about 20 at the most). Delay New SCT Cable Old SCT TRICS 5.7 Length TRICS 5.5 ----------------- ------ ----------------- 2k Loops 0 Errors 1.0' Big Time Blow Up Big Time Blow Up 3.8' 2k Loops 0 Errors 2k Loops 0 Errors 13.8' Big Time Blow Up Big Time Blow Up 15.1' 2k Loops 0 Errors Summary of what we see with new SCT and new FOM Earliest Helper timing tested. 39 nsec No errors 44 nsec No errors 45 nsec narrow band with big time blow up 50 nsec No errors 52 nsec No errors 56 nsec No errors 58 nsec No errors 62 nsec narrow band with big time blow up 69 nsec No errors 72 nsec No errors 79 nsec No errors 81 nsec narrow band with big time blow up 85 nsec No errors 92 nsec No errors 94 nsec No errors 100 nsec narrow band with big time blow up 107 nsec Fail to SCT Initialize TRM Geo Sect Busy 0:63 113 nsec Fail to SCT Initialize Monit Data for terms 48:51 Read 00f2 Instead of 00f0 Latest Helper timing tested. The above timing is based on 1.66 nsec per foot and a 1' cable from Tick Clock casuing a 39 nsec delay from Tick to Helper and a 1' cable from TRM Clk causing a 57.5 nsec delay from Tick Clk to Helper Signal The only change since the visit 19,20-MAY was to make to "5th" Selector FanOut provide copies of both Tick Clk TL00 and TRM Clk TL01 as possible sources of the Helper Function Clock. So to write down the current setup of the Selector FanOut Modules is: Module Delay Ch#0 Ch#1 Ch#2 Ch#3 Clock Function ------ ----- ----- ----- ----- ----- ----- ----------------- 12th 9 TL03* TL02 TL01 TL00 PCLK --\ 11th 9 TL07* TL06* TL05 TL04* PCLK* --/ M122 10th 9 TL03* TL02 TL01 TL00 PCLK --\ 9th 9 TL07* TL06* TL05 TL04* PCLK* --/ M123 8th 9 TL06 TL04 TL00 TL01 PCLK* --- Helper Clock * --> The output is not enabled Somehow the cable length estimate for the SCL cables which was done in April has now been lost. The following is an approximate recreation but we need to do a string length verification. Get out of M124 to its S.E. corner: 7' \ Rack top to ceiling: 5.2' \ Total To the hole: 1' / 14 ft Through the hole: 0.5' / To S.E corner of M224 under floor: 1' \ Cross the aisle to front of South row: 2.5' \ Down to N.W. front corner of M213: 22' \ Total Up out of the floor: 2' / 37 ft To top of the rack: 7' / To back of the rack: 2.5' / To S.E corner of M224 under floor: 1' \ Up from 2nd MCH floor to Ceiling: 10.5' \ Over to the hole 2' \ Total Through the hole: 0.5' / 16 ft Over to the S.E. cornet of M324: 2' / So the longest run to the 2nd floor is 51 ft and to the 3rd floor 67 ft. The LMR-200 cable that will be used for these runs has a velocity factor of 83% so in time the 2nd floor runs will be 62 nsec long and the 3rd floor runs will be 82 nsec long. (c=0.984 ft/nsec) Talked to SCL people. From Ted Zmuda, He talked to D0 people today and Johnny Green is happy with the current connectors. Specifically this is: Times Microwave cable LMR-200 with Johnson MCX series connectors: 133-3407-101 on the cable (right angle) and 133-3701-321 on the Receiver Cards. From Neal Wilcer, He today got a tester card from Mike Utes and Antonneo. He will have this for one week. On Monday he will send out the Gerber for his tester card. First of the Christenson Kotcher Commissioning meetings - mostly Muon. Philippe and Roger take part in the On-Line Workshop. DATE: 19,20-MAY-1999 At: Fermi TOPICS: Get SCT to work, Get CT to work, study master clock signals, visit Neal Wilcer, budget-schedule meeting with Jerry Blazey, Talk with Ed Arko, VIPA & FM's to MSU Steve gets CT running in 5 minutes, the M123 Mid slot 17 - slot 18 Spec Trig's Fired input cables were criss-crossed. Steve's new FPGA code for the Gated Scaler fixes the SCT problem when trying to run from Master Clock. Steve removed the P1-P5 copiers from the SCT .dct files and did other general clean up of files. E.G. we now have a single .dct to configure everyone for CT testing. He installed the Net Meeting stuff and tested it with Philippe. Used the scope to look at lots of 53 MHz and Tick and TRM clock signals. Details are in the paper note book. The short version is: you can only measure things to about +- 1 nsec., There are some systematic funny delays (e.g. signals come out of SFO #12 about 0.8 nsec before SFO #10, and perhaps most importantly, we do NOT really know exactly how to phase the 53 MHz wrt Tick Clock. Take the decision to reduce the Tick Clock setup by 2 nsec wrt 53 MHz. Thus all 5 SFO's are set to a delay of "9". Then making the measurements with a scope in 6 crates one sees: Tick Clock TRM Clock --------------- --------------- Set Up Hold Set Up Hold ------ ----- ------ ----- M123 TOP 11.5 6 12.5 6 MID 10 7 12.5 6.5 Bot 12 5.5 13 5 M122 TOP 11 6.5 13 5 MID 12.5 5 14 4 BOT 12.5 5 13.5 5 Move the Helper Function Clock from via's on the TOM-PB for the cable from the SFO in slot 11 to the 5th SFO i.e. the slot 8 SFO. Now explore the range over which the SCT (with scaler checking) will run error free. SCT Loops Tick Clock up edge to Helper up edge Cable Length until error Timing Helper up edge WRT 53 MHz clock edge ------------ ----------- --------------------------------------------- ? 1.0' 183,46,371 55-60 nsec 53 MHz mid hi - down edge * 3.8' error free 60-65 nsec 53 MHz down edge - mid low * 7.7' error free 65-70 nsec 53 MHz mid low - up edge * 10.0' error free 70-75 nsec 53 MHz up edge - mid hi # 13.8' 38,16,26,226,113,219 75-80 nsec 53 MHz down edge @ 17.7' 179,430,170,339,63 85 nsec 53 MHz mid low - up edge @ 21.5' 452,2,60,275,139,877 90-95 nsec 53 MHz up edge - mid hi @ 23.1' 39,28,235 95 nsec 53 MHz mid hi - down edge @ 26.9' 61,366 100 nsec 53 MHz down edge - mid low There seemed to be three general modes of operation: * A narrow range where everything appears to be OK # A narrow range where the Maginot Line comes high again about 18-19 usec after it pulsed high during the normal Helper Function output signal chain. When it comes high again it sticks high. Ton of SCT errors. @ A wide range where the only errors are scaler increment errors In the "#" range, note that the Maginot Line sticks HIGH at about the time TRICS makes an access to the Helper FPGA to clear the "launch pattern" bit. Why should there be such a range -- the Helper doesn't receive 53 MHz so it seems that it should be impervious to any 53 MHz phasing issues. But the Helper does receive On-Card Bus, which *is* locked to 53 MHz via the VME FPGA. So it's suspicious that an On-Card Bus cycle triggers this Maginot Line latch-up. Need to look at Helper logic to see if any design flaw can be found. In the "@" range, the only scalers with increment errors were 3 FOM FPGA's on two different FOM cards. Most (but not all) of the errors were on Channel 0 of these FOM FPGA's. The error most frequently seen was that the "read" value (i.e. final value minus the base value) was either 100 (hex) too high or too low. Looking at the values read, it appeared that the bit of value 100 (hex) was NOT set when it probably should have been in either the base read (resulting in 100-too-high read value) or the final read (resulting in 100-too-low read value). Simply re-reading the final value did NOT fix the problem, so it was likely incorrectly stored in the data capture register. Need to look at the FOM FPGA timing to see if there are any issues there. On Friday, we may have run a few loops (but didn't write anyting in the paper notebook) to show that the only errors in the 85 to 100 nsec range were scaler increment errors. That is we did not run a large number of SCT loops with scaler checking turned off. Recall that during testing on the previous Fermi visit it would run error free, with scaler checking turned off, over a range of about 65 to 90 or 95 nsec. These were measured at a different SFO retiming delay. Capture logic analyzer traces on the Kuhn camera disk. Made a scan doing voltage checks at the TOM test points and the Power Pan test points. See page 77 in the paper notebook. M122 TOP -2 and -4.5 need attention and so does M122 Lower -2. M122 Mid and all of M123 look fine. Visit Neal Wilcer and Ted Zmuda. They are talking with Marvin about the connectors for the coax cable. Concern is, "will the receiver card's coax connector stick through the front panel of the supporting circuit board ?" They are building an error tester circuit board to test the SCL link. I think that this gets them out of needing Mike Utes to do work for this testing. Check the power to their VIPA crate. With meter red on Vw and meter black on Rwx the meter reads -5.2 Volts. With meter red on Vz and meter black on Ryz the meter reads -2.0 Volts. Bring back to VIPA crate from the top of M124. This is Rital SN 0010, Fermi SN 545895, Rev Level 06. Will use this crate at MSU for continuing HSRO testing. Bring back three FM modules from Fermi. These are the Big Ben with the rock glued onto it (FM SN#15) and two P1->P5 Copiers (FM's SN#03 and #13). This leaves FM serial number ?? at D-Zero Hall running as the L1FW Helper Function. Talk with Ed Arko about VIPA crates. The other company is Weiner. They sell powered VIPA crates. DATE: 6,7-MAY-1999 At: Fermi TOPICS: Work getting the FW to run from Master Clock ReInstall SM serial number 25 in M122 Mid Slot 13. I will bring its temporary replacement back to MSU. Replace the burned TOM-PB and hot glue all the TOM-PB's. On power up the top crate in M123 once again hung with its DTACK* and Interrupt LEDs on which I assume indicates a VME Interface FPGA that will not load. Pushing the TOM buttons appears to have nothing to do with getting it to load. Just waiting for about one minute and then it spontaneously loads (or at least these LED's go out. Try running Connectivity Test. Run on M122-M123-All and it fails. Can see a lot of Mast 1 Slav 1 Slot 17,18 stuff i.e. the TRM's. Close log at 16:33 6-MAY. Run on M122 Low is OK. Run on M122 Mid is OK. Run on M122 TOP fails close log at 16:40 6-MAY-1999. Nothing is plugged into M122 Top. These per bunch scalers have their per bunch SM-PB's but nothing is plugged into it. Work on the Selector Fanout Modules. All 5 SFO's are set for retiming with a delay setting of "A". On SFO's 10,12 disable the output from SFO channel 0 which is Sequencer Timing Line 3. On SFO's 8,9,11 disable the P-Clock output. All of this is to reduce the amount of noise in the timing cable coming from Master Clock to FW. A delay of "A" puts the rising edge of the timing signals as seen from the TOM monitor connector right on the falling edge of the 53 MHz as seen from the TOM monitor connector. Run SCT. If you include the scalers it is a disaster. Lots of TDM scaler increment errors. i.e. TDM de-coor daq enable scaler increment, TDM coor daq enable scaler increment, TDM spec trig fired increment, TDM spec trig exposed increment, TDM and-or fired for spec trig increment, TDM daq enable scaler increment. All read the same, e.g. 3eb26 and all have the same instead of 7d637. Also FOM scaler errors. Without scalers run 10k loops of SCT OK. Try to guess what is wrong. Ah I get it. The Helper is still running from its own rock. So instead of pulling the rock off of the helper, I just make one of the P1->P5 Copiers the helper. I do this by exchanging Card Addresses between the classic Helper and the left most P1->P5 Copier, and moving the front and rear Paddle Boards from the classic helper to this P1->P5 Copier. On the P1-P5 Copier that I make the new Helper, I pull the white/black twisted pair stuff off of it and tie its U47 Pin 12 back up to its via so that once again this is a stock FM board. The P1->P5 Copier that was returned to being a stock FM is FM serial number 04. Eventually we will want to pull all the P1->P5 Copiers out of the Fermi setup. What ALL software needs to be changed when this happens ? OK it still will not run SCT with scalers. It will pass SCT without scalers for a couple of thousand loops and then it fails big time. This is true even if the only stuff in the SCT are some of the input TRM's. The more it runs the fewer loops it takes before it fails. I think the Helper Function signals are in the wrong place. Steve's page that begins "The best TOM to look at is M123 Middle" shows the Helper Function outputs going active on the 3rd falling edge of the 53MHz after the Tick Clock goes active. On the logic analyzer I see the Helper Functions go active on the 5th falling edge after the Tick Clock. The Logic Analyzer says it is 95 nsec from the rising edge of Tick Clock to the rising edge of a Helper Function signal. But on Steve's page that begins "Carmen timing signals for SCT" it shows the TL_7 Helper Clock as being delayed by only 3 cycles of 53MHz from the TL_0 Tick Clock. In comparing these two pages I just want to make sure that the Helper Function really does NOT need a tick of 53MHz between its stimulus and its output (e.g. to update output latches or something). OK, use our 5th SFO module, i.e. #8 SFO, to get us a copy of Sequencer Timing Line #1, the TRM Clock. This comes to the FW racks via our installed Master Clock to FW cables. Now put it through 10 feet or so of single signal cable and into Helper Function MSA_IN_51. OK, SCT without scalers is now working. The delay shown on the logic analyzer between the rising edge of Tick Clock and the rising edge of a Helper Function signal is 65 or 70 (mostly 70) nsec. I do not know what I should be timing ? Helper Function output ? Helper Function Clock MSA_51 ? Does the Helper Function eat a tick or two of 53MHz ? Does the Helper Function have latched outputs that are updated via 53MHz ? I have pulled out the 4 output cables that carried P1->P5 Copier Big Ben signals to the TOM_PB's. We can not backup now. Made 5 Philips Logic Analyzer "system disks" this morning with no problem, but now I'm having trouble writing capture files to them. The Logic Analyzer scroll knob is getting very noisy. Single Signal background material. In M123 Mid crate on the J3 connector in slot #3 pins 32 D&E go to the bottom pair of pins on the card to card daisy chain connectors on the TDM-PB via 3 or 4 feet of coiled up single signal cable. I think this may be skip next type of signal. In M123 Mid crate on the J3 connector in slot #3 pins 32 A&B go to the 16th pair of a short flat cable to M122 Mid crate J3 per bunch SM-PB. The connection from M123 Mid crate slot #3 J3 pins 32 A&B to the flat cable is via 3 or 4 feet of single signal cable. Friday, check the M123 Mid FOM to TRM cabling. It is all rational, labeled, makes sense, appears correct, no obvious problems, looks in good shape,... Using a delay of "A" the range of Tick Clock positive edge to Helper Function signal positive edge over which SCT would run was about: 60 nsec fail after about 10 loops 65 nsec runs OK 65-70 runs OK 85-90 runs OK 95 fails after about 50 loops 100 does not run Files that were captured with the delay of "A" are: M123TOP 1,2,3,4 M123MID1 M123LOW1. With delay of "A" use the scope to check in all 6 crate the relative phase of TICK CLOCK and 53MHz M123TOP 53 falls Low 1 nsec before tick goes Hi M123MID 53 falls Low 2 nsec before tick goes Hi M123LOW 53 falls Low 1 nsec before tick goes Hi M122TOP 53 falls Low 1 nsec before tick goes Hi M122MID 53 falls Low 1 nsec after tick goes Hi M122LOW 53 falls Low 1 nsec after tick goes Hi Move to a delay of "7" i.e. 3 nsec less delay on the Carmen lines relative to the Carmen 53MHz. This should put the rising edge of the Carmen lines at about 2/3 of the way through the high part of the 53MHz. Now with delay of "A" use the scope to check in all 6 crate the relative phase of TICK CLOCK and 53MHz M123TOP Tick goes up 6 nsec after 53MHz goes up M123MID Tick goes up 7 nsec after 53MHz goes up M123LOW Tick goes up 5 nsec after 53MHz goes up M122TOP Tick goes up 7 nsec after 53MHz goes up M122MID Tick goes up 5 nsec after 53MHz goes up M122LOW Tick goes up 5 nsec after 53MHz goes up The files to look at are: M123TOP 5,6 M123MID 2,3 M123LOW 2,3 M122 MID 1,2 M122LOW 1,2 With a Delay of "7" SCT without scalers would run in the following range of Tick Clock to Helper Function output delays: (positive edge to Pos edge) 60 nsec dies in 50 loops 65-70 OK 70 OK 85-90 OK 90-95 OK 100-105 dies in some number of loops 110 will not run Test run of SCT exclude the scalers, Initialize and run 5k loops zero errors include the scalers initialize ask for 2 loops dies on the 1st loop New Scaler Base Verify all Again OK ask for 2 loops dies on the 1st loop Close logfile at 17:24 I have check and the Tick/Turn scalers were incrementing Test of Connectivity Test M122 LOW OK M122 MID OK I see it also talks to M123 Top some And-Or cards flash M122 MID Internal OK M122 TOP Internal OK M122 TOP Fails it also talks to M123 TOP And-Or modules M122 Top is not cables to anything Close the logfile at 17:41 M123 Low is OK M123 Top is OK M123 Mid Fails forgot to click abort, so close the log file at 17:45 by clicking the X Random Register Test Run with the sct configuration loaded OK in both M122 all and M123 all 19,386 registers millions of loops. DATE: 4-MAY-1999 At: MSU TOPICS: TOM Timing Signal to Logic Analyzer Adaptor Make a adaptor pod to connect the TOM front panel Timing Signal monitor connector directly into the Philips Logic Analyzer. See page 63 of the paper log book date 14-OCT-1992 for more details about the input to the logic analyzer. Basically the input to the logic analyzer itself, looking into the pod cable (without a test point pod) it looks like 20k Ohm in parallel with about 61 top 63 pFd to ground. The test point pod has 180k Ohm in parallel with 7 pFd caps in each test lead, right out at the end of the test lead. This just gives a 10:1 compensated divider setup. Based on what mica caps were available, and the desire to have less than a 10:1 attenuation when looking at ECL swings, the TOM Adaptor was made for a 7:1 attenuation. It has 10 pFd caps in parallel with 121k Ohm resistors. Testing of the TOM Adaptor: Used a test power supply and a voltmeter to see where the threshold actually was Logic Analyzer Input Voltage to the So this looks right Threshold TOM Adaptor at the considering that the Logic Setting Switching Point Analyzer Threshold is -------------- -------------------- calibrated for a 10:1 - 2.0 V 1.405 V probe attenuation. - 1.9 V 1.337 V - 1.8 V 1.263 V For ECL threshold of 1.29V - 1.7 V 1.196 V Setting the Logic Analyzer - 1.6 V 1.122 V to -1.8 V should be right. Test looking at a TOM Timing Signal monitor output connector. Logic Analyzer Threshold What you actually see -------------- --------------------------------- -1.1 V Highest Threshold where you still see any signals move. -1.4 V Some of the signals look sometimes sick. -1.5 V Highest Threshold where all signals look OK. -2.1 V Lowest Threshold where all signals look OK. -2.2 V Some of the signals look sick. -2.5 V Lowest Threshold where you still see any signals move. So also by this method a Logic Analyzer Threshold of -1.8 Volts looks good for working with the TOM Adaptor pod. DATE: 28,29,30-APR-1999 At: Fermi TOPICS: Fire up the racks, Work with Master Clock and the new version of Connectivity Test, Examine ERPB, DC, MTG Connections, DC wiring to M124 Lower Wanted to run SCT and then Connectivity Test to check out the replacement SM card in Slot 13 Middle Crate M122 (see entries from 7-APR and 15-APR) and to test a new cut of the Connectivity Test files that will test more of the cards. When turning on the power to M123 the Top Crate sat with its DTACK* and Interrupt Request LED's illuminated. This most likely means that a VME Interface FPGA in M123 Top did not load up. I waited about 30 seconds and then cycled the power - same LED's stayed illuminated. After 30 seconds I started poking at the System Reset push button on the TOM module and I think in response to poking it, the LED's went out. The power supply LED's were not flashing or anything funny like that. After all of this I checked the Voltages at the TOM module all all were fine. If this happens again what is going to be the best way to sort it out? Ran 10k Loops of SCT including checking scalers. But at loops 961: Bit 3 Error Interrupt, Device Not OnLine, Remote Bus Timeout, Remote Bus Error, Post Write Check Mismatch, Read 180d, Last Wrote ffff, Master 1, Slv 0, Slot 12, Chip 6, Reg 16. So start a fresh run of just 1k Loops of SCT and it finishes OK. Checked on some details of the Run I ERPB DC MTG setup: MTG --> M103 --> M104 --> M105 --> M106 --> Term MTG --> M110 --> M109 --> M108 --> M107 --> Term MTG --> M112 --> M111 --> Term The DC to ERPB feed down a rack is the following (tw = twisted section): TOP ---------->----------->----------> BOTTOM DC tw ERPB tw ERPB tw ERPB tw ERPB 2xtw ERPB tw ERPB tw ERPB tw ERPB tw Term ---------------------------------- ------------------------------------ Upper Tier I Crate Lower Tier I Crate So as things stand, there are 9 twisted sections between the DC and the bottom ERPB. Just a little problem. DC switch settings - it appears to know the sign of eta. Eta Setup ID/Mode Rack Coverage Switch Switch ---- -------- ---------------- ---------------- M103 +1...+4 d d d d d d d d d d d d d d d d M104 -1...-4 d d d d d d d U d d d U d d d d M105 +5...+8 d d d d d d d d d d U d d d d d M106 -5...-8 d d d d d d d U d d U U d d d d d --> the key is down U --> the key is up I can not read whether up or down is circuit open/closed. Worked with Laura Paterno and Fritz to get the Master Clock working. Set the PCC at $3000, set the main Sequencer at $4000, and set the 1st through 12th Selector Fanouts at $7000, $7010, ..., $70A0, $70B0. They can start the Sequencer and I have set up the 5 Selector Fanouts via their DIP switches and run them in Local mode. These are the 8th through the 12th Selector Fanouts. Set switch packs 2,7 all Closed, switch pack 1 is all closed except for key 2 which is open to select the P-Clock. The Selector Fanout channel selection of Timing Lines is basically setup the way it is described in the current TIMING_SIGNAL_GENERATION_DISTRIBUTION.TXT file with the following exceptions: The 9th & 11th Sel Fanout's Channel 0 Switch pack 4 is set to enable Time Line 7 to be sent out. This can not hurt very much because these signals do not make it past the vias on the TOM rear PB and they may be useful (see below). The 8th Sel Fanout has its channels 0,1,2 enabled to send out Time Lines 10,9,8 just to give us a way to see them. One idea for getting Time Line 7 the Helper Function BX Clock to the Helper MSA_Input 51 is to grab it off of vias on the TOM PB. This in fact could save the need of SFO 8. Moved M122 Top and Middle to run off of their Master Clock cables. The FPGA's in these crates download OK and run Random Register Test OK. Connectivity Test is not running again yet and its too early to try Single Chance. Most of the problems with the new version of Connectivity Test are now fixed but there are still some errors (or hardware problems). See the log file that was closed on 28-APR-99 at 18:37 for a CT run that had errors but no Bus errors. What I do not know is are these errors due to hardware problems, i.e. stuff that has never been tested before, or are they errors in the new cnx files ? Also not that I tried running: M122_Top_ct.cnx, M122_Top_Internal_ct.cnx and the same two files for M122_Middle just by themselves but they give tons of initialize type errors. Should I be able to run these in isolation ? Finish connecting DC power wiring to the lower VIPA carte in M124, i.e. the SCL Hub-End crate. Connect -5V to Vw and -2V to Vz. The return W and return Z are both connected to the power supply common return. I still need to verify that this is the correct setup. Install a good Master VI and a good Slave VI on a 400mm extender and setup a 214 at $00020000 i.e. slot 2 and things take off OK. Can run Random Register Test on Master 2 Slave 1 Slot 2 first 100 registers. Also plugged in the VI slave in the lower VIPA crate via the slave 0 cable from the master, i.e. the cable for the upper VIPA crate and ran Random Register Test just to check the other Master channel that we need and its cable. The upper VIPA crate in M124, i.e. the crate for VRB readout that we have had for a while is being recalled. It was only at Rev. 4 and it needs to be at Rev 6. I should receive its replacement on Friday. There will be a meeting on 7th May to talk about/to the new vendor for VIPA crates. Things that could/should be changed in the setup of the SFO's P-Clock is coming out of all 5 SFO's. It should be stopped on 8,9,11 We can free up SFO 8 by getting Timing Line 7 from SFO 9 or 11, pulling it off of the vias on that TOM-PB, and feeding it via a single signal to MSA_Input_51 on the Helper Function. SFO's 10,12 currently route Sequencer TL 3 via their SFO Channel 0 which ends up on P1_TS 4. Right now this is OK because Sequencer TL 3 is programmed just as a flat always down signal, but if we start to us TL 3 then we need to change the SFO configuration to keep this signals off of the P1 backplanes that do not want it. OK, now something very strange in the M122 Bottom Crate. I had the TOM-PB's off to move to Master Clock timing cables. I noticed that the TOM-PB from M122 Bottom had a melted contact in its ERNI connector. The very bottom C row contact, C32, is melted right in two. There is no hot-melt on the back of this TOM-PB so I assumed that it had been pushed up against the card file. If you put a "good" TOM-PB onto Bottom M122 then it shows a +5V to Gnd short. Watching with an Ohm meter this short starts when just the TOP of the normal TOM-PB is engaged and it does not show a short when just the bottom of the normal TOM-PB is engaged. But , it is the bottom of the burned TOM-PB that has the burned pin. Worked on this some more, yes the burned pin on the TOM-PB from the bottom M122 is real but the short is not real. The reading of 0.09 Ohms instead of the expected 2.5 Ohms from +5V to Gnd is caused by "leakage" currents moving these two conductors apart by the right voltage to cause this zero Ohm reading. Where does the leakage come from - it is the TOM-PB feed over to MSA_Input_51 on the Helper Function that causes this. Disconnect this feed and the effect goes away. Why the Master Clock driving ECL into MSA_Input_51 of an FM card causes this effect while driving the same Master Clock signals into a TOM has no effect I do not understand. But there is another problem. The Rear Paddle Board on the Helper Function in Slot 20 is a Rev. A Rear Paddle. If someone were to more this to Slot 21 it would go boom. Should collect all the Rev. A Rear Paddle Boards. Single Signal List. In a file should we make a list of all the single signals. Loaded Connectivity Test Configuration Files into 6 Crates and ran Random Register Test on 4 of them. See Log File closed 23:32 29-APR-1999. It would not run on M122 Middle due to a problem in Slot 13. Note this is the replacement SM card. Loaded the SCT Configuration into all crates. It gives errors. See the log file from 23:43 29-APR-1999. Want to make an adaptor for the Philips Logic Analyzer so that it will plug into the front of a TOM module. The adaptor at Fermi to go to NIM signals uses 40.2k Ohm series resistor bridged by a cap that says 27J (and of course 51 Ohm terminators at the NIM input. Had one long run, 4 hours or so, with just the blowers running and all the FW crates off. The heat is NOT coming form the blower motors. It is from the FW electronics. Need to bring the Hot-Glue here to fix the TOM-PB's. Need a written description of what the Time Lines ideally should be. Need to think about how the timing files should be described. Ration pass through the Connectivity Test files: Load 6 crates with cnx FPGA configuration Register I/O 6 crates for cnx M122_M123_ct.cnx some errors close log at 11:41 30-APR-1999 Register I/O 6 crates for cnx M123_Top_ct.cnx OK 1 meg loops M123_Mid_ct.cnx some errors, appears to talk to all crates in M123 M123_Lower_ct.cnx OK M123_All_ct.cnx some errors close log at 11:55 30-APR-1999 Register I/O 6 crates for cnx M122_Lower_ct.cnx OK M122_Middle_ct.cnx OK M122_Middle_Internal_ct.cnx OK M122_Top_ct.cnx some errors appears to flash top crate M123 M122_Top_Internal_ct.cnx OK close log at 12:01 30-APR-1999 No Bus errors seen in any of the above Connectivity Tests. DATE: 23-APR-1999 At: MSU TOPICS: VRB and Resistors On Friday we finally get our VRB back via UPS Ground. Just for the records it is VRB SN# ??. Norm Birge borrows the 4 current shunt resistors on the plywood panel and power cables so he can shunt this magnet. DATE: 15,16-APR-1999 At: Fermi TOPICS: Get VIPA crate for the Hub-End, Collaboration Meetings, ECB Meeting, Philippe L3 Review on Saturday 17th, Took a replacement SM to Fermi Received from Ed Arko a VIPA crate to use for the Hub-End SCL crate. It is Fermi ID 548162 Rital SN 8098751-04 ECO-6. Move the VME TCC Communications Crate from where the SCL Hub-End crate belongs to the expansion rack space on top of M124. This is only temporary but it give the Communications Crate a new home, without making new Vertical Interconnect Cables, until we can figure out where we want to permanently install this crate. Installed it with a NIM fan tray under it. The VME Communications Crate and it fan tray get switched power from M124. DC Power wiring into the lower VIPA crate in M124, the +5 and +3.3 are tied up, need 4 more Return cables, and need to tie up the -2 and -5. It is clear that the -5 is on the Vw circuit and the -2 is on the Vz circuit. Need to check is the Return wx and return yz are common with the +5 and +3.3 Return or if these are isolated returns. If it is isolated return then need to verify that these negative voltages are really on the Vw and Vz pins and that they have not grounded these pins and made the isolated returns the negative supply distribution. Tried talking to the upper VIPA crate via Vertical Interconnect from the Communications Crate. This did not work - the cycles never completed. Information added 19-APR-1999. The Master that this was tested with is bad. It completes cycles OK but returns bad data. The Slave that this was tested with has a problem that in a VIPA crate this master only works if some other card e.g. a BIT-3 is crate controller. See the VIPA Crate Notes. ECB meeting. Yes poke a new hole between 1st and 2nd MCH. Pull the cables out of the 2nd to 3rd MCH hole. All Run II stuff must be fire rated cable. Will use two cable lengths. One to make it to rack 213 and the other to make it to rack 313. Need to verify with all that the 2-3 cables are all junk. Then ask Ed PODSCHWEIT to pull them out and to work with Delmar on the 1-2 hole . Took a replacement SM card to Fermi to replace the SM in M122 middle crate Slot #13 that quit passing Connectivity Test. The original SM card that now fails connectivity is SM serial number 25. The replacement SM just taken to Fermi is SM serial number 48. Philippe stays Saturday the 17th for the Level 3 Review. Ray Zeller with there for the review. Jan Hoftun is now working for ZRL. Visit Ted Zmuda about the VRB. He has sent it back to MSU and sent a note to Steve. They changed how the header looks and we did not know this. The overwrite of the flash apparently caused by the switch flip should not have happened. Talked to Dean about the Luminosity database stuff. No big change since the last note to him. Philippe also checked with him about this. They would like to be able to ask TCC to get a set of Luminosity data without having it increment the Luminosity Interval. Asked Harry about John Marriner's Accelerator talk. It will be at least 2 years of running before going from 396 to 132 nsec crossings. I believe that this means that we could think about 3 lookups in L1 Cal Trig to get EM data for readout without any Symmetric Low Energy Cut and a separate lookup with a Symmetric Low Energy Cut selected for Preshower Quadrant Matching. DATE: 7,8,9-APR-1999 At: Fermi TOPICS: Work on Framework, Measure for L2 cables, Install cable trays, make and install cable to Carmen Clock, Pickup the repaired VRB from Ted Zmuda, L1CT pcikoff and Luminosity discussion with Dean, Trouble with Connectivity Test. Vertical MCH Dimensions ----------------------- Space under 1st MCH computer floor: 14 " Top of 1st MCH computer floor to bottom of 1st MCH ceiling: 12' 1 1/2" 1st MCH ceiling thickness: 6" Space under 2nd MCH computer floor: 24" Top of 2nd MCH computer floor to bottom of 2nd MCH ceiling: 10' 7" 2nd MCH ceiling thickness: 6" Space under 3rd MCH computer floor: 24" Horizontal MCH Dimensions ------------------------- Space between the faces of the two rows of racks in the MCH (i.e. width of the MCH middle aisle): 43" Space behind the South row of racks in the MCH: 30" Space behind the North row of racks in the MCH: 30" Rack Dimensions --------------- External Rack Height: 83 1/2" Internal Rack Height: 78 3/4" i.e. 45U External Rack Width: 24" External Rack Depth: 30: FCH Dimensions -------------- Distance between FCH North to South walls: 24' Distance in the FCH from East to West Cable Windows: 60' Distance East from the West Cable Window to the likely location of the Level 2 Test Stand: 8' Distance from the MCH wall, through the cable window, to the FCH wall: 35" Fix the problem with the 6 pack radiator in M102 hanging down between it and M103. Bolted M102 to M103 in the back. Put a side panel on M101 between it and M100. Pulled the air blocker panels out from under M101 and then replaced the bolts holding M100 and M101 together. Installed M101 to M102 bolts. Pushed the string together with a jack. Should have cut a hole in the side panel between M101 and M100. Installed cable trays on top of M122:M124 and running over M101:M104. Put up two cross bridge cable trays. One is near the center of M122 where the L1.5 - Voltage Monitoring bridge was, and the other is at the air conditioner end of M124. This second one can be used for Master Clock Timing cables. Installed the grills at the back of the air outlet boxes on top of M122:M124. Ran order of 6 hours of SCT just fine. Trouble with Connectivity test. It is a problem with slot #13 of the Middle crate in M122 Scaler Rack. "Register Contents still not Zero after zeroing every source during Initialization Read 0x0008 at Master #0 Slave #1 Slot #13 Chips 1:16 Register #0" I looked at this SM card but did not have time to fix it. Made and Installed but did not connect the 26 conductor flat cables to the Master Clock. These are all 30' long, 18 flat sections long. In the bundle between M100 and M122,M123 they are grouped with adjacent cables flipped over. This was thought to help "shield" the 53 Mhz carried on the first active pair of the cable. The cables were threaded into M100 and M122,M123 but not plugged in yet. We will start using the Selector Fan Outs near the high slot number end of the Master Clock Crate and use the Static Timing Lines e.g. the first 12 timing lines. Dean wants the initial interaction clock file setup for 3 super bunches of 12 bunch crossings each at 400 nsec with even gaps between. Attempt to download to the Master Clock but Laura and Stu could not make either the old VMS software work or the new system work. They will push on this this next week. Laura has only until the end of April. Some new VME CPU module is needed to make the new system work. Fritz Bartlet has this module. The Master Clock has been moved into M100 and some 13 Hz Vertical INterconnect system was poking at it. Master Clock is powered up. Talk with Dean about pickoff signal time resolution. The signals before the summer will have order of 140 nsec for absolutely their full risetime. After the summer this will take somewhat longer and have a flatter top. Being able on special runs to readout 2 L1CT samples is OK. Under special run the precision readout system will be able to digitize 3 adjacent BX samples. This is how Dean will find the peak of the precision signal, by knowing 3 samples and knowing its shape. L1CT should be able to do the same type of thing. Should be able to compare the two but it will be complexe software because of the various calorimeter elements that make up a Trigger Tower. May want to have the logic that looks for low threshold trigger in tick N followed by high threshold trigger in tick N+1 and just use this in increment a scaler...I.e. this scaler would give you a good idea if things have gone wrong. Also the idea that the first tick after a gap is a magical one because it does not have energy before it and the last tick does not have energy after it. So how often does the L1CT fire on the tick after the last tick of a bunch. Talked with Dean about Luminosity logging. Want to be able to identify what Luminosity Interval a given event belongs in. So said that we could readout the following types in info and scalers with each L1 Accept: COOR Run Number, Luminosity Interval for this Run, Never Reset 132 nsec Clock Scaler, L1 Accept Number (packed and unique in a run), Tick Number, and a Turn Number that is not reset at SCL Initialize. Still lots of questions about how logging to the database will work. Philippe can "micro pause" to change the Luminosity Interval Number and trigger the capture of the Luminosity Scaler information. May also want an absolute time number on these luminosity records, e.g. acnet time. DATE: 31-MAR-1999 At: MSU TOPICS: MVME-214 shipped Shipped a MVME-214 Memory module (SN#8) and a 214 book to Drew Baden. DATE: 29-MAR-1999 At: MSU TOPICS: Cable Tray Part Number The proper part number for the Square D Cable Tray mentioned in the next entry is CLA3AD-06SS06-144 i.e. Cable tray, Ladder type, Aluminum, 3" usable depth, siderail design, Double rung, - 06" wide, Straight Section, 06" rung spacing, 144" long = 12'. We still have lots of side splicing plates and the special hardware bolts and nuts for this stuff. DATE: 24,25,26-MAR-99 At: Fermi TOPICS: See the SCL proto-types, Talk with Ted about our VRB, D0TCC1 on the net, Carmen Clock being installed, Visit Neal Wilcer and see proto-types of Status Concentrator, Serial Link FanOut, Hub Controller, and J3 Backplane. I also saw samples of the cables that will run from the Hub-End to the Geographic Sections. They need to know the cable length for the runs and we need to make the map of what Geo Section to what Geo Section Number so that these cables can be installed once and only once. The Serial cable going out to the Geo Section is about the size of RG58 and the status coming back is about the size of a 1" wide flat cable. Routing all of these cables into this crate is going to be a big deal. Need ECB input. Talked to Ted Zmuda about our broken VRB. He will try to fix it. They are not going to be making any more until sometime after mid June. Initial run was 16 and these have lots of problems. Then there was a run of 10 with the same etch and these seem fine. Right now the big push is "full crate tests" for CDF and D-Zero. Install the magnet and key latches on our 3 new racks. Single Chance Test is running fine. Recall that you need to tell it that the Helper Function is at Master 0 Slave 2 Slot 21. Connectivity test is running fine. For it recall that during download you need to tell the download program to Enable the ECL Outputs at the conclusion of download. Ran both SCT and CT for 6 to 8 hours each without error. The thin net cable is in to the PC and it is on the net. Steve Chappa is installing the Master Clock in M100. Things to get: Side Panel for M101. Cable Tray need one or two 10 or 12 foot sections. It is 6" wide by 3 1/2" deep and made by Square D. It is aluminum and has numbers on it similar to C2732033 & CLA3ADD65506144. We also need splicer plates for it. Grill at air outlet This needs to be about 13 1/8" wide with 1" wings folded back by 7 3/16" tall with a 1 3/4" wing folded back. These wings will all fit inside the current air outlet box and the bottom wing will screw to the taped hole in the top hatch opening. The top edge of this cover fits with in the lip on the folded edge of the top cover. This cover grill will be removable. Voltage Monitoring Cables. Need enough for 3 PP + 3 PP + 2 PP + 2 PP where each Power Pan makes 4 voltages. Cables to bring Master Clock signals over 31 ft long This is 13 pair cable with normal connectors. For now we need at least 7 of these. Safety system stuff e.g. air flow sensor, terminal blocks, temperature sensor, smoke detector, RMI Meeting with Arnaud Lucotte meeting with Jerry Blazey DATE: 21-MAR-99 At: Fermi TOPICS: Steve picks up backplane and Verticals Steve brings back from Fermi the backplane that we need for the VIPA crate so that the VRB and the G-Link VTM can talk to each other. Steve also brings back 3 more Vertical Interconnect slave modules. They are serial numbers: This now gives us enough Vertical Interconnect stuff at MSU to run the MSU Test Framework Rack and the MSU Test Crate. DATE: 17,18,19-FEB-99 At: Fermi TOPICS: Deliver and begin to install the Run II Framework Kirsten, Philippe, Steve, Dan deliver and begin the installation of the Run II Framework at Fermi. Get it physically installed and running Connectivity Test and SCT. Notes, right now Connectivity did not appear to be looking at the output FOM or L2 TRM and it was only low rate on the M123 Bottom TRM's (disable inputs). Right now you have to tell it that the Helper is at slot #21. Talked with Marvin. They are NOT planning to have split VIPA crates to get two Zeller modules into one crate. Problem of splitting the VIPA J1-J2-J0. 2nd topic: The worry is that SVXII will loose its configuration when a heavy nuclear particle goes through it. So want to reload it, perhaps once every 5 min. What data to reload (i.e. the 192 bits) is stored out on the sequencers ? on the platform. But it would take a long time for the normal down load system to tell all the sequencers ? to reload their SVXII's. And during this reload process the SVXII's are dead so they would need to get a "BUSY" back to the FW but there is no path for this signal. So, can we pause the L1 trigger, send a L1 Qualifier to stimulate the SVXII reload, wait on the order on 1 msec, then restart the triggers ? Talked with Rich Partridge. He wants/needs to talk with Steve in Paris about FPGA stuff. DATE: 4,5,6-FEB-1999 At: Fermi TOPICS: Collaboration Meeting, L2 Review Work getting ready to bring FW to Fermi. Collaboration meeting and ECB meeting. Jim presents his L2 special Geo Section concerns to the ECB - no big deal and Rich Partridge presents the Luminosity Monitoring stuff. I ask for a second copy of the signals that we have to feed the scalers (i.e. I do not want just one copy for feeding both And-Or Terms and Scalers. Talk with Dean about BLS signals. Need to ship Dean a long cable. Need to pass Dean and Boris names to Neal and Ted. Remove all the cabling from M114 and the Power Pan from M114. All the CBus and TSS cables for L1 Cal Trig are wound up on top of it. Talk with Delmar about cutting and removing the cable trays from behind M122:M125. Give Del our schedule for delivery of FW. Setup and test 3x of the 20 Amp 3 phase outlets for the new FW. DATE: 20,21-JAN-1999 At: Fermi TOPICS: Steve and Dan at Fermi Steve was on the L1 Review Steve was on the L1 Trig's - MSU L1 Review Committee. Dan visit with with Neal and Ted at SCL Headquarters. Removed the M122, M123, M124 racks. This involved pulling lots of equipment and tons of cables that are not ours out of these racks. I hope no one blows up. DATE: 19,20-Nov-1998 At: Fermi TOPICS: Remove more equipment, schedule meeting with Jerry Blazey, talk with Dean about removing the M122 and M123 racks, Meet with Neal and Ted about SCL, Bring back VME and VI Slave Remove the M114 VME crate, remove the M124 voltage monitoring equipment Need to check with Lyn Bagby about removing the M124 Nim and M122 scope NIM stuff. Bring back 3 Vertical Interconnect slaves and 1 master and the M114 VME crate with its modules. The two Run I FW racks are up on the 6th floor and the blower has been moved Brought back the VRB that Ted Zmuda has tried to repair. He has it alive again by resoldering an Altera chip but Channels 0,1,2 are still making mistakes. He worked on it for two days. It suffers from poor assembly soldering plus possibilly other problems. Returned to Dean all the Zeller cards from Run I L1 and L1.5 Cal Trig. Dean says that Ed Poshwit has a way to splice the twisted section of twist and flat cables by combing and putting connectors on them. Brought back more hand made cables pulled from the L1 FW. The VMS online cluster was not running. Talked to Neal Welcar and Ted Zmuda about the crate power supply and cooling for the SCL Hub-End. Pulled all the voltage monitoring equipment out of M124. We are now fully moved out of M124. Pulled the VME stuff out of M114. Delmar has removed the two Run I FW racks to the 6th floor storage area and he has moved the blower. Give schedule stuff with resource info to Jerry Blazey. DATE: 29,30,31-OCT-1998 At: Fermi TOPICS: Bring broken VRB back to Fermi, Upgrade meetings, Remove L1 FW equipment Talk with Delmar Miller. The broken VRB does not work in Mike Utes's crate either. I take it to Ted Zmuda at FCC. He will send email after he looks at it. Remove the L1 and L1.5 Frameworks including M101 and M102 racks, L1.5 FW crate in M103 and its power pan in M104. Remove all cables running up the hole above M103 except for some 17 pair cables to L3 Supper and some Master Clock cables. Remove all cables going to M124 except for the L15CT readout itself. Remove all the cables involving the FW that run around the back of the rack cable tray except for the C-Bus and Timing Bus 32 pair cables. Remove the 4 32 pair flat cables that carried L1 Cal Trig And-Or Input Terms to the L1 FW. Remove TCC and its BA23 box with built in VME. Bring TCC's Vertical Interconnect Master and the VI Slave from the L15CT crate back to MSU. Ask Delmar to remove M101 and M102 and to move the blower 48 inches West. DATE: 9-OCT-1998 At: Fermi TOPICS: ECB Meeting, Hub End Meeting, Swap VIPA crates Return to Ed Arko the VIPA crate that I got from him on about May 22nd to be used at MSU for Level 2 Trigger work by Jim Linnemann. This was CD SN# 545893. The new crate that I got is Rittal SN 0018 ECO-5 Fermi ID 548288. This is for Linnemann Level 2. Went to ECB meeting, All is rational with how people think about using the SCL Initialize. Looked for but did not see Dan Owen. DATE: 17,18 SEPT 1998 At: Fermi TOPICS: Philippe and Dan at Fermi for Luminosity Meeeting. Luminosity meeting, all OK up through getting data into data base, then it gets complicated. TCC will send to only one consumer which will distribute and log the data. Philippe has meeting with Lars Rasmussen about the communication stuff in Run II. Have meeting with Neal and 2 other people at FCC. First meeting without Walter Knopf. Talk with Marvin and Mike Utes about HSRO and Finisar. DATE: 19,20 Aug 1998 At: Fermi TOPICS: Bring back VRB equipment, Visit Walter Knopf, visit Marvin, Online meeting Bring back a VIPA crate. This one has the safety ECO. Ed Arco needs the one back that the MSU L2 setup is using to swap for one with the safety ECO. The parts that I got are: Crate No. 32233 with Fermi bar code 548299 VRB with front panel sticker "VRB PP15", Transition Module SN 4610 with Fermi bar code 548198. The online meeting was Jim L's commissioning of L2 lack of partitioning presentation. DATE: 16,17-JULY-1998 At: Fermi TOPICS: Muon Electronics Review, Talk with Marvin about Master Clock and VRB, Talk with Mike Utes and Johnny, Talk with Dean, Pull apart L1.5 CT and 36x36 Scalers, Bring Stuff back to MSU. Site Survey Muon Electronics Review was on Thursday, I get to do the Amplifier Discriminator Board for the MiniDriftTubes. Everything looks in rational shape wrt Run I. Talk with Marvin. He wants 3-4 weeks before supplying a VRB and controller and crate. We both independently like the idea of M124 for the Master Clock. Not yet clear when to begin the move of Master Clock. Marvin says that its move may be the end of VMS. They would run Master Clock from old PC test type programs. Mike Utes shows me his new "Port Card" now called "Sequencer". I think that its controller will now send it "NRZ Data and Clock" aka the "slow optical command link" over copper signals on the backplane. They (Mike and Johnny) have made a Finisar Card with the connector and G-Link Chip and the Finisar Module all on the same side of the board. They did exactly what we understood they were not going to do. I.E. they flipped the connector so we can not use this board. Still need to check with them about do they have bags of parts. Dean and I talk about sending "Test Triggers" and L1_Busy to stop just a BX or two. All this looks OK and is basically the second go around on all of it. See mail messages over the past 5-6 weeks. He also wants to change some calbes in the last 4 slices of eta. This effects only our last two racks in L1 Cal Trig. If right now these cables to each CTFE are A,B,C,D we will need to change them to A,C,B,D or something like that. Pull all of our equipment out of racks M124 and M125; this means everything out of M125. The only thing related to us that is left in M124 is the Shea Module for voltage monitoring and out Blus Voltage Monitoring boxes on top of M124. I labeled this stuff. Distribution of this equipment: BACK to MSU the lower (i.e. spare) L15CT VME Crate, the 36x36 Scaler Power Pan with two bricks its #6 cables and its Cu Bars and red/white power drops for the 36x36 crate, and the M124-M125 rack power contactor box (old Intergraph power box). Still at Fermi the: L15CT VME crate with its Hydra Modules and Ironics and 68K and 214's and some VI's, the 4 supply L15CT Power Pan, the mini card file for the L15CT MTG and the Receiver Cards, the 36x36 Scaler crate with all its cards. All the cables are folded back onto the Cal Trig racks. Site Survey: M124 is across from M103 and the bridge runs between M105 and M122 and we currently have cable tray along the front of M122:M124. DATE: 5-JUNE-1998 At: Fermi TOPICS: Framework TDR Review Philippe and Dan DATE: 18-22-MAY-2998 At: Fermi TOPICS: CMS Review, Bring back a VIPA VME Crate for Level 2 DATE: 7,8-MAY-1998 At: Fermi TOPICS: CAL TDR Review, write Shaper and SCA sections DATE: 1-MAY-1998 At: Fermi TOPICS: ECB at Fermi DATE: 2,3-APRIL-1998 At: Fermi TOPICS: Jim's L2 Global Mini Review DATE: 12,13-MARCH-1998 At: Fermi Topics: STT Review at Fermi write report on some hardware software issues. DATE: 5,6-MARCH-1998 At: Fermi TOPICS: L2 Meeting at U of Maryland