D-Zero Hall Log Book for 2001 ------------------------------- The most recent entries are near the beginning of this file. This file began in January 2001. Earlier D-Zero Hall Log Books are on the web either in the directory with this file or else at: http://www.pa.msu.edu:80/hep/d0/ftp/run1/l1/inventory_logs. DATE: At: Fermi TOPICS: DATE: At: Fermi TOPICS: ------------------------------------------------------------------------------ DATE: 29,30-DEC-01 At: MSU & Fermi Topics: Problem doing VME cycles in Rack M122, Dead Power Pan in Rack M104 The control room called about 1 AM on Saturday the 29th because events had stopped flowing and when they tried to Initialize the Trigger Framework there were errors. From the office via VNC (that Philippe just got working on Friday using multi hop SSH tunneling) it was clear that VME cycles to rack M122 were often not working. They were failing in all 3 crates in M122. The two things that are common to making VME cycles work in all 3 crate in M122 are the Vertical Interconnect Master for M122 and the Carmen Master Clock Selector FanOut that sends 53 MHz to M122. This same problem, i.e. TCC not being able to reliably do VME cycles to any crate in M122, happened once before. See the log book entry for 13:15-DEC-00. During that incident a lot of effort was put into trying different Vertical Interconnect Masters for M122. The resolution of that incident was that after making various tests, VME cycles to M122 just started to work again using the original VI Master. Because the other common element to all crates in M122 is the Selector FanOut, this time, I asked people at Fermi to swap the Master Clock Selector FanOut that send 53 MHz to M122. That did not help. Also tried swapping VI Masters and that did not help. After making lots and lots of tests, Daniel noticed that if M122 Middle was turned off, then we could configure M122 Top and Bottom with no problem. But if M122 Middle was powered up then there were VME problems to all 3 crates. The cause of the problem was the cable between the VI Master and the Slave in M122 Middle. The AMP contact on the lower wire of the lower pair of wires at the Master end of the link to M122 Middle was not clipped into the housing and it had pushed back and was making only a flaky connection to the backplane pin. Just clicked the contact into the housing and no more problems. We are running with all the same electronics modules that we in the system before this incident. The interesting point of all of this is that a cable problem in one of the links, killed all three of the links. M104 Lower Tier 1 Power Pan had a dead _5.2 Volt supply. This -5.2 V brick runs OK for a couple of minutes and then stops. So, PDM-04 is pulled out of M104 Lower Tier 1. Its dead -5.2V brick is SN#8 from 9-NOV-88. Replace this Power Pan with the one from M112 Lower Tier 1. That is PDM-08 was pulled from M112 Lower Tier 1 and installed in M104 Lower Tier 1. PDM-08 had already been uncabled from M1112 to allow access to the VESDA inlet tube. The Run I Power Pan log book is at: www.pa.msu.edu/hep/d0/ftp/run1/l1/inventory_logs/power_pan_inventory.lbk and we need to think about how we want to keep track of the Cal Trig Power Pans in Run II. The -5.2V brick from PDM-04 is one of the old kind that they will not repair any more. Also PDM-04 needs the new type of terminal strips and varistors added to it and the new type of AC ON light. New idea for adding the varistors is to put them on the terminal strips on the bricks. The old 5V 200 Amp supplies are: Pioneer Magnetics Model: PM 2500A-2 Type: 5D200-0-4-6-S No longer sold or serviced. The newer 5V 200 Amp supplies are: Pioneer Magnetics Model: PM 2926A-2 Type: 5D200-0-4-6-S Yes, still sold and serviced. The 2V 325 Amp supplies are: Pioneer Magnetics Model: PM 2501B-2 Type: 2D325-0-4-6-S Yes, still sold and serviced. The 5V 600 Amp supplies are: Astec (was Powertec) Model: 9R which is still in their web site catalog. DATE: 12:15-DEC-01 At: Fermi Topics: Connect L3 Trans Num to last SCL FanOut, Connect more L1 Cal Trig Count Comparators, SCL Cable work in GS $11,$12,$20,$21,$23,$49,$4c, Trics 9.5.D - TrigMon_II, explore some single signals and scaler cabling. Make a new front panel bus cable for the top 8 SCL FanOut Cards so that we can start to feed L3 Trans Num and L1 Qual to the SCL FanOut for GS 120:127. The connectors (Thomas and Betts 609-3430) are spaces at 50 mm increments along the cable. This could be reduced by 5mm or maybe even a little more. Installed this Wednesday night and all has been well with it. Elizabeth would like more of the L1 Cal Trig Count Comparator Outputs connected to the Trig FW. Right now we have just the first 2 Count Comparators from the 4 EM Ref Sets and the first 2 Count Comparators from the 4 Jet Ref Sets tied up as And-Or Input Terms. She does not need any more Count Comparators from the EM Ref Sets but she would like (and the target layout calls for) all 4 of the Count Comparators from the Jet Ref Sets to be connected as And-Or Terms. Scott already has this in the COOR Resources file which is located at: /online/data/coor/resources/ coor_resources.xml For AOIT's 128:151 it shows things connected just as in the target design layout for the AOIT's. So we need to start sending a 2nd block of 16 AOIT's from the L1 Cal Trig to the Trig FW. The only easy way to make this work today is to use 2 more Time Lines from the L1 Cal Trig CMC Sequencer #2 to generate the required Strobe and Gap signals. The Strobe and Gap signals are currently generated by TL9 and TL10. So let's make second copies of each on Time Lines 12 and 13. Implement this and call it the 14-DEC version of Sequencer #2 program. Tie up these 2nd copies of Strobe and Gap and the 3rd and 4th Count Comparator outputs from the Jet Ref Sets to the next block of Cal And-Or Input Terms, i.e. 144:167. Check and verify that the TRM FIFO depth is the same for AOIT's 128:143 and 144:167. One at a time set the Tot Et Count Comparators 2,3 to require a count of zero and verify that the proper AOIT lights up. Edit the file that lists the "connected" AOIT's. Could not find any other way to get copies of the Master Clock files back to MSU to put on the web, so I gave up an mailed them from online to kepler. SCL Cable Work Found another bad SCL Status Cable. This one was to L2 Muon on the 3rd floor. It is G.S. $21. The Status cable crimp at the G.S. end was bad. Connect Serial Data and Status SCL Cables to G.S. $11 and $12 in rack M115. Connect SCL Status Cables for G.S. $20 and $23 to rack M121. The 4 SCL Status Cables described above are using the following raw cable labels: 41-3 GS $11 41-4 GS $12 41-5 GS $20 41-6 GS $23. Finally get around to connecting SCL Status Cable for Dean's 13th G.S. Until now we had been using Status Cable 4C to carry the 9tatus for G.S. 49. See 9,10,11-MAY-01 near the end for details of how it had been setup until today. So now Status Cable 4C will carry the status for G.S. 4C and a new Status_PB and 40 conductor twist and flat will carry the status for G.S. 49. This cabling uses old 40 conductor cables between 1st and 3rd MCH, plus 40 conductor cables run along the back of the FW racks to reach over to the vertical run to the 3rd floor. The full setup is: 3rd Floor 1st Floor Into SCL 3rd-1st SCL M124 Status MCH 1st MCH Status SCL Geographic Paddle Vertical Horizontal Paddle Hub-End Geographic Section Board Cable Cable Board Cable Section ---------- --------- -------- ---------- --------- ------- ---------- 40 A 1 1 A 1 40 42 B 1 6 1 1 B 2 42 44 A 2 2 A 3 44 45 B 2 5 2 2 B 4 45 46 A 3 3 A 5 46 47 B 3 3 3 3 B 6 47 49 A 7 7 A 7 49 spare B 7 "4" 4 7 B 10 spare The Geographic Sections in Calorimeter that have "normal" SCL Status cables are: 41, 43, 48, 4A, 4B, 4C. So now there are no "cross connected" cables to Cal and we now also have one spare "status channel to Dean stuff. Single Signals and Scalers. TCC Pause/Resume This comes out of the L1_Helper on its MSA_Out_20 and runs by flat cable to the Patch Panel Box in M122 where it is routed to connector #15 pins 9-10. From here it runs into M123 where via pins it plugs into the the 4th pair of a 17 pair twist&flat cable. This twist&flat cable runs to the MSA_In 0:15 and MSA_In 16:31 connectors of a Rear_PB on P2 of Slot 20 of M123 Top. This is the Global Disable TRM. So this would be MSA_In_3 and MSA_In_19 to this TRM. L1_Acpt Strobe from the M123 FanOut runs to the L1_Helper to its P2 MSA_In_0 input in M122 Bottom. Gated Scaler to Count the Number of L2 FW Cycles. The location of this scaler and the control input to use is described in Gated_Scaler_List.txt. We did not make an explicit L2_Helper output signal to control this scaler but we can use the copy of Send L2 Decision that was planned for the "logic analyzer" and comes out of the L2_Helper on MSA_Out_11. This is routed via twist&flat cable to the Patch Panel Box in M122 where it is routed to connector #8 pins 3-4. Currently this signal is not used. Does this signal have the proper time relationship to FW BX Clk to control this Gated Scaler ? Gated Scaler to Count the Number of L2 Accepts. The location of this scaler and the control input to use is described in Gated_Scaler_List.txt. We did not make an explicit L2_Helper output signal to control this scaler but we can use the copy of Increment L3 Transfer Number that was planned for the "logic analyzer" and comes out of the L2_Helper on MSA_Out_13. This is routed via twist&flat cable to the Patch Panel Box in M122 where it is routed to connector #8 pins 7-8. Currently this signal is not used. Does this signal have the proper time relationship to FW BX Clk to control this Gated Scaler ? The Increment L3 Transfer Number comes out a tick or two after the L2 Decision is issued so this scaler would be a tick or two behind the Number of L2 Decisions scaler. Began running TRICS 9.5.D and have moved over to using TrigMon_II. Need 9V Batteries for both Fluke meters and new batteries for the Thermometers. Need to bring card transporter box to return SM SN# 63 to MSU. DATE: 5:7-DEC-01 At: Fermi Topics: Clean up in D0Config, TRICS 9.5.B, Tie up some L2 Scalers, L1 mask optic cable to L2, Cal Trig optic cable to L2, M123 Scaler Cabling, repair Exp Grp #3 pBS, Blue cables plugged into L1 Cal Trig, CTFE cables from Pat As part of the clean up in D0Config setup the top FPGA configuration file as: Edit Configure_L1_FW.mcf so that it only calls Configure_FPGAs.dcf Creat and Edit Configure_FPGAs.dcf so that it calls M122_All.dcf and then M123_All.dcf and then M101_All.dcf Note that this leaves us with a M122_M123_All.dcf file that is not used in the normal Trics Master_Command_File Menu initiated FPGA configuration process. But I would like to keep it for "manual" initiated configuration of just the whole Trig FW. Scaler Cabling Understand the cabling to the Exposure Group per Bunch Scalers. The Exp Grp pBS are in M122 Mid. The flat cable that feed the P2 per_Bunch_SM_Paddle_ _Board's comes from M123 Mid Slot #3 P2 Rows A&B pins 16:32. The flat cable that feed the P3 per_Bunch_SM_Paddle_Board's comes from M123 Mid Slot #3 P2 Rows D&E pins 16:32. M123 Mid Slot #3 is a Pass-Through card that carries the bulk of the signals to feed the TRM's and the Exp Grp per_Bunch_Scalers. The pinout of this Pass-Through is Backplane pin MSA Number Carries Signals --------- --------------------------------------- 15:0 31:16 Exp Group Partial Enable to EG PBS's <---- 47:32 Exp Group type signals to Gated scalers 63:48 Exp Group Partial Enable to TDM's 79:64 95:80 EG FE Bz, Glob Disable to EG PBS's <---- 111:96 127:112 EG FE Bz, Glob Disable to TDM's This is described in: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/cabling/ level_1_fw_cabling.txt Need to understand what thee couple of unconnected things on this Pass-Through are. These come from pins A&B, D&E row 32. This needs to get into the single signal file. M123 Bot Slot 18 has a Scaler Module installed but nothing is connected to either its P2 or P3. M123 Bot Slot 19 has a Scaler Module installed. P2 MSA_In_4 receives a copy of Global L1 Accept Strobe. P3 receives a copy of Global L1 Accept Strobe and a copy of Send L2 Decision. These P3 signals are used by the L1 Await L2 Scaler and are described in the single signals file. M123 Bot Slot 21 has a Scaler Module installed. On P2 MSA_In_0 it receives a 30 nsec delayed copy of Global L1 Accept Strobe. On P2 MSA_In_1 it receives a copy of SCL Initialize. Thursday morning there was chaos because at about midnight Gustaaf Brooijmans chose to play with the SCL Hub-End Patch Panel (this type of activity being encouraged by D-Zero management). Druing the process of re properly connecting the SCL cables I blocked too much of the M123 air outlet and thus tripped M123. The Exposure Group #3 upper per_Bunch_Scaler card that was pulled out last week, SM SN# 63, M122 Mid Slot 14, probably does have a problem. I'm 95% certain that SM SN# 63 was in the system in June 2000 when the following log book entry was made. DATE: 1-JUN-2000 At: MSU via VNC TOPICS: PBS Testing Begin with: TRICS Version 8.7 Rev A PBS version 8.1 Begin testing PBS with a new version of TRICS which knows how to set up the Exposure Group PBS's. Note a problem with: Master 0 Slave 1 Slot 14 Chip 13 This FPGA configures correctly but fails L1 FW Initialize and Random Register Test. Many registers read back 0x0003 or 0x0303. Need to remove this card and replace with a good spare, bring the broken card back to MSU for repair. For now, kludge TRICS V8.7 Rev B to simply skip this card (it's Exposure Group 3, Ticks 81:159 + Integrated over all Ticks, we don't need it right now). So, last week SM SN# 63 was replaced with SM SN# 52. We should not re-install SM SN# 63 until it has been tested and repaired if necessary. SM SN# 63 is labeled and needs to go back to MSU. Tied up 8 of Adam's flat cables for controlling L2 Scalers. These go to Gated Scaler PB's at P3 on slot 9 and 10. Testing of this looks OK. Installed optic cables to carry L1 Cal Trig readout from M103 and M104 over to the L2 Cal Pre Processor in M121. The optic power level indicated by the VTM's in our L1 Cal Trig readout crate did not change much when the fibers to M121 were plugged in (the splitters were already plugged in). These levels now read $283 and $287 for ch 0-1 and 2-3. These are low but it appreas to run OK. Need to translate this to dBm. Installed a splitter in the output of the FOM++ which is in slot 16 of M123 middle. The FOM++ is readout by the VRB in slot 16 ch 4-5. This splitter passes through the tray under the fan along with the rest of the optic cables. Using this splitter there are no additional joints in the optic path to our L3 readout. There is one barrel and then a cable from the splitter to feed L2. So we now have FOM++ Mask of L1 Fired feed to L2 Global. This is all labeled and installed. Before adding the split the VTM optic power was $357, $349, $329, $256 after the split it was $357, $349, $293, $256. So FOM++ is unfortunately low. Need to translate to dBm and look at this. At some point we can "un split" the Tick & Turn Scaler feed to L2 because they shound not need it long term. The VTM that reads the split Tick & Turn scaler shows optic power of $303. Bob had spotted that a couple of the L1 Cal Trig cables that should be plugged in were not and that a couple of cables were plugged in the wrong place. This was all fix and the only blue cables that are not plugged in now are: ?? Picked up from Pat Liston the CTFE cables both types. They look OK. Need tag labels with string at Fermi. Need Brother P-touch TZ tape, type TZ-231 and type TZ-211 white 1/2" and white 1/4" 2 spools each. DATE: 27:30-NOV-01 At: Fermi Topics: Work on Cal Trig Readout, Install M101 RMI, Verify Master Clock Timing, SCL Hub-End work, Install L2 Scalers, Edit important files, Investigate the top 1/2 of Exp Grp #3 PBS Work on starting readout from M104. Setup the DC card for M104: Cook a ERPB_7.FUL for SCP1 This is format 82 sum check 000E 1E83 Cook a U26.NOW for U26 This is format 82 sum check 0003 F8D6 Do the white wire ECO for Xmit_Trig signal source. Install the header for Selector GAL GAL2. The prom burner files for the ERPB_7.FUL and U26.NOW are stored on D0TCC1 in the exo directory for the CT_Readout_Helper. Don't ask why they ended up there. Make 8 more headers to replace the Transmit GAL's on the ERPB cards and install them. Using the Sparks in slots 10 and 11 and channel pairs 0,1 and 2,3 in the VRB in slot #9. The negative eta readout order from rack M104 looks OK so far. Installed RMI and smoke detector for M101 and connection to RPSS. See note book pages 88 and 91. A M101 RMI smoke detector trip will show up on RPSS as trouble with water flow or water pressure in M101. Have noticed in the past that the VESDA shows a very high air flow when the fan in the Cal Trig first starts up. I think this may be due to the blast of cold air that the VESDA gets when the fan starts up. The VESDA uses the normal thermistor to detect air flow. Right now after the fan has been running for a long time it comes down to a 80% to 81% reading. The "trouble alarm" level is 90%. When the fan first starts it is typical to see a 90% or 91% air flow level. Yes, this week it did go into trouble alarm. How the L1 Cal Trig Readout is currently started for test runs: Config FPGA's Master 3 Slave 1 Slots 10 and 11 the Support FPGA site i.e. site #17 /Bougie/Spart_7_2.exo Config FPGA's Master 3 Slave 1 Slot 21 FPGA site 4 / /ct_read_helper_8_1.exo Register I/O /scratch/CTRO_Spark_Test_1.rio VME I/O /scratch/CTRO_Test_2.vio After the shutdown, we get are first store Wednesday night so Check Master Clock timing and the number that we get under the standard test conditions is 356 or 357 nsec. So things are OK within 2 nsec of the number from April. See 19:21 Sept 8:10 Aug 24:28 April. Check Master Clock timing again Friday night and get number of: 355, 356, 356, 358, 355. This is with the standard 64 nsec and 8 nsec cables. The new best estimate number for BX to the leading edge of the SE01 Bump in the M114 patch panel is 297 nsec. Visit Ted and Neal and obtain: 10 more SCL Receivers, 16 pcb and 16 flat cable connectors, delay lines, 2 FanOut boards (SN# 003B and 022B). On Thursday swap back to the "old" hub controller and install the 16th and final fanout. This gives us: 1x spare Hub Controller 1x spare Fanout 2x spare Status Concentrators 11x spare SCL Receivers Work on making the Cal Trig Readout start up automatically after turning on the power and doing a normal Configure from TRICS master command file menue and then a COOR Initialize. To do this edit: Edit Configure_L1_FW.mcf to add a call to M101_all.dcf Creat and Edit M101_all.dcf to configure the Bougie/Spark and CT_Read_Helper FPGA's Creat and Edit Bougie.dci Bougie/Spark into slot 10,11 Support FPGA site Creat and Edit CT_Read_Helper into slot 21 FPGA site #4 Edit Init_Post_Auxi_CT.mcf so that it now calls Init_Post_Auxi_CT.rio and then Init_Post_Auxi_CT.vio Creat and Edit Init_Post_Auxi_CT.rio setup Sparks and CT_Read_Helper Creat and Edit Init_Post_Auxi_CT.vio setup VBD VRB & VRBC The big problem was that this did not work. The problem is that the CT_Read_Help needs its front panel P4 Main Array ECL Outputs enabled. This is now taken care of in the Init_Post_Auxi_CT.rio file. Test this and all seems OK. Doing just a M101_all.dcf and a L1CT_Init will wake the system up from a de-configured output disabled state and the system will readout OK. Install the 6 Gated Scaler Cards for the L2 Monitoring. These are all in M123 Bottom. The Species rotor switch is $80. Scaler Slot Address Module SN# ---- ------- ---------- 8 $16 45 9 $19 46 10 $1c 47 11 $1f 49 12 $22 51 13 $25 56 Edited files so that these would be Contigured. Edit M123_Bot.dcf to add Configuration of the 6 new L2 Scaler Modules To move what Tick the Foreign Scalers use as their "tick 1" use the command, "TrgMgr_Foreign_Scaler Base_Tick_Select

" All 10 of the Foreign Scalers (0:9) should get moved to 16 to line things up the way that Michael Begel wants it. e.g. TrgMgr_Foreign_Scaler 5 Base_Tick_Select 16 Also edited the FW post auxi to move the base tick of the Foreign per bunch scalers. Edit Init_Post_Auxi_L1FW.mcf to set all 10 Foreign per bunch scalers to a base tick value of 16 Try to understand the problem with the top half of the Exposure Group #3 per Bunch Scaler. This is slot 14. It always reads all zero. Pull scaler card SN# 63 and try running SN# 52. Exact same problem. So it is not the Scaler card. It is the backplane per bunch scaler PB. Why is one of them, it just happens to be slot #14 P2, labeled in red and all the rest in black. Terry Toole x2321 Toole@fnal.gov is the new person working on the de-mux card. Need to bring some PB_SM_PB cards to Fermi next week. DATE: 14:16-NOV-01 At: Fermi Topics: Returned Becane to Fermi, Status Cable from Dean, Work on Cal Trig Readout Move Becane fnal configuration to ip address 131.225.224.55 Dean did not have and "status" information coming back to the Trig FW for G.S. $49. The cable was plugged in wrong. Cable Lebel $4C is current used to carry the Status Information for Geo Section $49. See the end of the 9,10,11-MAY-01 log book entry. Build this week's CT_Readout_Helper FPGA on Becane under M1.4 and capture a couple of the commands used: par -w -ol 5 -d 3 map.ncd ct_read_helper.ncd ct_read_helper.pcf trce ct_read_helper.ncd ct_read_helper.pcf -o ct_read_helper.twr bitgen ct_read_helper.ncd -t -l -w -f bitgen.ut Edit the Master Clock file for Sequencer #2 to make a couple of small changes in the timing signals for the Cal Trig readout. Nothing else was changed. Then see how things run: Look at some timing coming out of the CT_Readout_Helper: +--------------------+ +--- EM/Tot | | | ---+ +--------------------+ +------+ +------+ Input_Clk | | | | -----------+ +-------------+ +--------- nsec | | | | | | | 0.0 96 163 206 283 351 394 Verify the Capture_Data coming out of the CT_Readout_Helper is asserted for 2 cycles of EM/Tot and makes its transitions on the positive edges of EM/Tot. Try to see the relative timing of the active edge of "Helper_BX_Clk" and positive edge of EM/Tot in the CT_Readout_Helper by looking at the Xmit_Trig output (which is clocked out by Helper_BX_Clk) wrt the EM/Tot output. This will not be a single relationship because Helper Clock runs at 3x EM/Tot. What I see is that positive leading edge of Xmit_Trig comes either: 107 nsec after positive edge of EM/Tot 26 nsec before positive edge of EM/Tot 290 nsec before positive edge of EM/Tot (only at a gap). So it does not look like "Helper_BX_Clk" and EM/Tot are dangerously close to each other (but 26 nsec is not a lot of room). Using single isolated pulse to CTFE, scan the range of "Lookback" values: Value Loaded Readout for Values seen for CTFE in Manual Lookback Looking ----------- Channels Whose ADC are Control Reg. Value Back HD EM are driven to output $00 ------------ -------- ------- ---- ---- ------------------------ $77 $17 = 23 9 zip zip 0800 0800 0902 0a04 $78 $18 = 24 8 zip zip 0808 0808 0908 0a0a $79 $19 = 25 7 good good 0800 0800 0902 0a04 $7a $1a = 26 6 zip zip 0800 0800 0902 0a04 $7b $1b = 27 5 zip zip 0800 0800 0902 0a04 I have no understanding yet why the data from $78 looks funny. Moved the position of the pulse going into the CTFE wrt Beginning of Turn to scan all 12 beam crossings in the first Super Bunch. Saw good EM data at all 12 crossings. Checked the Had data on the 1st, 5th, 10th 12th BX of the Super Bunch and it looks OK. The "number of data words" register in the Spark is loaded with $7f to readout the 128 words from each rack. Need to bring more Status Cable Adaptor cards to Fermi for putting the two of the 26 conductor 25 mil status cables into standard 40 conductor 50 mil cable. Notes from Daniel's survey of the Status Cables. Geographic Sections whose Status Cable has been plugged in recently, and also the list of those G.S. which do not have a status cable labeled and are currently unconnected. Connected Crate Name Location on 11-14-2001 ------------- ---------- -------- G.S. 0x13 L1CTT M322-2 G.S. 0x14 L1CTM M321-2 G.S. 0x21 L2CMU M324-0 G.S. 0x22 L2FMU M324-1 G.S. 0x24 L2PS M200-1 G.S. 0x25 L2CTT M200-0 G.S. 0x70 STT0 M202-0 G.S. 0x71 STT1 M202-1 G.S. 0x72 STT2 M203-0 G.S. 0x73 STT3 M203-1 G.S. 0x74 STT4 M204-0 Status Cable non existent or Crate Name Location not labeled ------------- ---------- -------- G.S. 0x0A L2TA FCH2 G.S. 0x0B L2TB FCH2 G.S. 0x0C L2TC FCH2 G.S. 0x0D L2TD FCH2 G.S. 0x0E TFC MODULE ---- G.S. 0x11 L1LUM M115-0 G.S. 0x12 L1FPD M115-1 G.S. 0x17 L1MUN M321-1 G.S. 0x20 L2GBL M121-0 G.S. 0x23 L2CAL M121-1 G.S. 0x49 CCNE M310-0 (*) (*) USES THE CABLE FROM 0X4C WHICH NO LONGER EXISTS AS A G.S. See log Book 9,10,11-MAY-01 log book entry. DATE: 10-NOV-01 At: MSU Topics: Junk data in the readout from TrgFW to L3. Called at about 11 PM and came in to look at the problem. Some one had figured out how to write a trigger file that did not include reading out the Trig FW. This killed the Trig FW readout for other running triggers. Just the normal shove data into the VRB's but don't tell the VRBC to readout issue. I think that COOR let this through because there were only non-readout crates in this trigger configuration file. Anyway they added the Trig FW $1f and the L3 wake up $7f to their configuration and then all was OK. DATE: 7:9-NOV-01 At: Fermi Topics: Work on Cal Trig Readout, more information for the official crate list. Setup Becane to run at FNAL, i.e. just copy the 7 files (sure wish people had done it this way the first time): /etc/defaultdomain Just swap the _fnal and _msu versions /etc/defaultrouter of each file. /etc/hostname.le0 /etc/nodename /etc/resolv.conf /etc/inet/hosts /etc/inet/netmasks /home/mgc/etc/cust/mgls/mgc.licenses the NEOCAD_SSERVER environment variable still is set to becane but stell -a shows good licenses - I do not understand this. Will the Neocad software actuall run ?? Neocad License Server is running OK with the d0sunmsu1 host name ? But how does the application or stell find it ? Still need to do something about making room on the system disk. Cook a PROM for a test of the ERPB's. This is version 5_73 made on Desmo on 6-NOV-01. It will be ERPB version III. I followed Philippe's instuctions for running the PROM Burner PC which are in the 4:11-OCT log book entry. We need a new floppy disk drive for that PC. Old problem with it was that it would not give your disk back. Now you can not put one in. Swapped the MSA_Inputs for EM/Tot and In_Clk CMC signals going into the CT_Readout_Helper as is required for the new FPGA for this function. Edited the Sequencer #2 file to make it generate the In_Clk and EM/Tot patterns specified in the CT_Readout_Helper document. Could not do this from becane - although from becane it does work to telnet to d0mino, use the crypto card to get into d0mino and then ssh to the d0l1 group account on the online. But then I could not throw a xemacs window back to becane. So find an online machine, it is 99% already logged in to some account that can not write the clock files, first xhosts +this_machine.fnal.gov then su to d0l1 then fire up xemacs. This is the only current way that I know to do this. Try running with the new setup and I can not even get the FPGA's to configure. It's not just that the Yellow LED stays on (as with the May 1999 design) but the DONE is not going HIGH. Could be the cooking of the PROM or something in the BitGen. With the May 1999 PROM the Yellow LED stays on but the DONE does go HIGH. Need to check the options to BitGen vs the old BitGen log file. The new CT_Readout_Helper looks like it is putting out the right signals on the right MSA_Outputs to the DC Card. OK the problem is that when you expand the address range with the PROM programmer sometimes it packs in FF (as you need) and sometimes it packs in 00. Yesterdays PROM had all 00's packed in in the expanded address section. The new ERPB Serial PROM file is called ERPB.NOW It has a SumCheck of 000e 2c8d. OK there is one extra strobe coming out before the data starts. This is because we clock the data out of the LCA in the Run II system. So need to change the U26 PROM on the DC so that it has: D D D D D D D D 7 6 5 4 3 2 1 0 - - - - - - - - Adrs 0 is $FE 1 1 1 1 1 1 1 0 Adrs 1,2,3 $EF 1 1 1 0 1 1 1 1 Adrs 4:$83 $E7 1 1 1 0 0 1 1 1 Adrs $84:$FF $FE 1 1 1 1 1 1 1 0 D0 is the SQ_DDC0 signal low at adrs 0 then the rest hi until adrs 131 D2 is the SQ_ERPB_OE signal which is always hi D3 is the SQ_Clock_MASK signal low for adrs 0,1,2 then hi until adrs 131 D4 is the SQ_FBACK0 signal hi at adrs 0 then low until adrs 131 The file with the new U26 for the Distributor Cap is called U26.now It is in Exorcisor 82 format. I has a SumCheck of 0003 f8d6. U26 is the PROM closer to the Tier 1 Backplane. This fixes the extra strobe at the start and now all the "first CTFE channel on each ERPB card" and "last CTFE channel on each ERPB card" look in the right spot. There is still really a question of how best to setup this Strobe from DC to Bougie/Spark. You really just can not get what you want with the current GAL4 part. This is OK for now by inverting the Strobe line before it goes into the Bougie/Spark but doing that is both clumsy and not optimal. The headers that I have here are wrong. They need to be 24 pin not 20 pin. Walking the CTFE channels through the ERPB looks all OK except that the ERPB "B FIFO" is wired backwards to the output mux, the bytes are swapped. EM should be the Hi byte and Tot the Low byte. Fire up Mentor on Desmo and make the small edit, then on Desmo edif, map, and start 100 place & routes par. Desmo makes a nice version of erpb multi_100_6.dir/5_29 BitGen this with just the standard options (w,t,n,u) and cook a PROM. On the floppy this is stored as erpb.full and erpb.fl2 (should both be exactly the same). Note again that the Data I/O first tried to fill the user expanded address range with $00 instead of $ff. Now working with the ERPB.Ful prom: Recall what the Energy Lookup PROM's look like (see the log book entry from 4-OCT-01). And understand the eta dependent Zero Energy Response. For that look in section #18 of: www.pa.msu.edu/hep/d0/ftp/run1/simulator/lsm/data/official_file.lsm Where you will find: with CHANNEL EM list MAGN_ETA 1 to 20 8 8 9 10 11 12 12 12 13 13 13 14 14 14 14 14 14 14 14 8 with CHANNEL HD list MAGN_ETA 1 to 20 8 8 9 10 11 10 12 12 13 13 13 12 12 14 14 14 14 14 14 14 i.e. this is the output of Energy Lookup Page #3 when the value of 8 is put in as the address and recall that 8 comes out of the ADC when the signal representing zero energy in the Calorimeter goes into the ADC. What I see in the Run II Cal Trig readout for the first 4 positive eta's when all the TT's have their pedestal DAC driven to $00 so that I know that $00 is coming out of the ADC i.e. not the zero energy response is: $0800 $0800 $0902 $0a04 this is eta 1,2,3,4 EM-Tot Philippe points out that Energy Lookup page #3 is a slope of 1 and thus if a decimal 10 comes out of the PROM when an ADC zero energy response of 8 is going into the PROM, then when the ADC puts 0 into the PROM we should expect a 2 to come out. Thus what we see in Cal Trig readout looks good. EM and Tot all look in the right place. There is no extra word at the beginning. Walking through a CTFE card looks in the right order. Passing from one ERPB card to the next is OK. Note that all these tests are in positive eta and not at the funny card position. All the above work has been with "static" data, i.e. data that is the same from one BX to the next. Work on Friday afternoon trying to find the signal when I just pulse a CTFE input for a single crossing. I do this with the "triggerable" CTFE pulser that I made. I pulse it at about 5 Hz, always in the right place for the first BX in a turn, and then have the L1 Cal Trig generate the L1 Acpt. I scanned the range of "lookback" values but never found the signal. I did see a signal a couple of times but it was not consistent. So, so far the lookback is not working. Daniel dug out the accurate information about the rack locations of the SVX Geo Sections vs the L3 rack on the 2nd floor. He also dug out the mapping of Sequencer non-readout Geo Sections to VRB crate Geo Sections. So the official Crate List file was edited and re-spun to the web. The web document for the "Shea Box" is located at: http://www-linac.fnal.gov/linac_controls/hardware/DZero/DZeroRM.html DATE: 15-OCT-01 At: MSU Topics: We have a sick 114MB logfile on TCC's disk. Tried retrieving the file for archival while d0olc's hardware was being upgraded. TRICS_II_20010913_V9_3_A.LOG;2 is a sick file of size 114,807 kB. - 08-oct-2001: Philippe tried copying (pulling) the file from MSU. Probably at the same time TCC was acting sluggish while Dan saw its disk light flashing continuously. The copy failed part way through with an IO Error. - 10-oct-2001: Tried copying the file again; failed again. Philippe (via VNC) tried zipping (with WinZip) the file, but the VNC connection was lost and the compressed file ended up holding only 70MB of data. - 15-oct-2001: Tried zipping the file again and winzip hung at 61%. The operating system was then un-responsive and took a long time to allow killing Winzip. Trics also died around the same time and we have to assume that it was linked to access trying to access this file. The first error at the end of TRICS_II_20011008_V9_3_A.LOG;1 reads: "Illegal Value found in Bit3 Adaptor Interrupt Parameters" followed by many more typical register IO failure messages. This message would mean that Trics detected a mis-communication with its own interrupt service routine for bit3 interrupts. But we do not enable bit3 interupts, and I don't kwnow how we would be able to encounter this condition. Not understood. Philippe then tried a simple copy with NT Explorer of that file to TCC's own E: disk. The copy hung halfway through, and after a few minutes with no progress, the following message box popped up: "Cannot copy TRICS_II_20010913_V9_3_A.LOG;2: The request could not be performed because of an I/O device error." This file was moved to D:\Trics\D0_Log\D0_Trics_II_Log_2001_09_hold where we will now leave it alone in case it holds a bad spot on the disk. After restarting Trics V9.3.A, COOR automatically reconnected and initialized. Then the Control Room was able on their own to restart a run after minimal confusion. Trics was returned to ignore L1CT. Also recently: - The version of Trics that starts automatically when TCC boots was updated to V9.3.A on 15 0ct. - A snapshot of the current \Trics "run files" (d0_config, exo, etc) was grabbed on 12 Oct and archived. - The copy of TCC's \Trics files were brought up to date on MSUL1A. ------------------------------------------------------------------------------ DATE: 4:11-OCT-01 At: Fermi Topics: Work on Cal Trig Readout Work on SCL 2 SCL Receivers to G Steinbraeck for STT Trigger. Bob Kehoe office x8653. In the 2nd Sequencer, the sequencer for the L1 Cal Trig, I moved the TL 4 the CTFE Energy Lookup most significant address line later by 2 RF Buckets. That is it moves to the 2nd lookup later by 2 RF Buckets (and moves back to the address for the 1st lookup later by 2 RF Buckets). Need to update the drawings and the drawing on the web. This is just to give a better optimization to the timing, i.e. not to fix a known problem. To the 2nd Sequencer add: ERPB Input Clock Time Line 20, ERPB "EM/Tot Select" Time Line 21 Checking CTFE Energy Lookup memory page select address lines. Yes, backplane signls "D" and "E" are locked HI. The energy lookup most significant address line, TS&S "J", goes HI for the 2nd lookup. Scope pictures on disk "ERPB". Friday #1 Y=erpb input clk, B=erpb em/tot, V=erpb cap data Saturday #2 Y=erpb input clk, B=erpb em/tot, V=ctfe x_clk, G= real bx Sunday #2 Y=erpb input clk, B=erpb em/tot, V=ctfe x_clk, G= erpb cap data $33 #3 Y=erpb input clk, B=erpb em/tot, V=ctfe x_clk, G= erpb cap data $13 #4 Y=erpb input clk, B=erpb em/tot, V=ctfe x_clk, G= erpb cap data $03 Want to double check what is in the Distributor Cap Sequencer PROM. Read the two 7C291A EPROMS from the DC. U23, the PROM that is not really used for anything, is all $F3 for addresses 0:255 PROM U26, the transmit sequencer PROM in which bits D0, D2, D3, and D4 are important reads as: D D D D D D D D 7 6 5 4 3 2 1 0 - - - - - - - - Adrs 0 is $FE 1 1 1 1 1 1 1 0 Adrs 1,2 $EF 1 1 1 0 1 1 1 1 Adrs 3:$82 $E7 1 1 1 0 0 1 1 1 Adrs $83:$FF $FE 1 1 1 1 1 1 1 0 D0 is the SQ_DDC0 signal low at adrs 0 then the rest hi until adrs 131 D2 is the SQ_ERPB_OE signal which is always hi D3 is the SQ_Clock_MASK signal low for adrs 0,1,2 then hi until adrs 131 D4 is the SQ_FBACK0 signal hi at adrs 0 then low until adrs 131 Use the ECL box and the 4 channel scope to look at a Tier 1 backplane. Watch the X_Clock line and look at some of the Total Et signal bits. Yes, these values are changing on the positive edge of X_Clock. From the first initial rise of X_Clock to the 50% point on a data line is typically about 13 nsec. From the first initial rise of X_Clock until the typical data line is settled is 20 to 24 nsec. The raw output of the ADC's through the 29525's typically reads 0 when $00 is loaded and reads decimal 81:84 when $ff is loaded i.e. reads $51:$54 When doing the above be sure to keep in mind what the cable from the backplane does to the signal polarity. Want to double check what is in the Energy LUM PROM's. Pulled the Energy Lookup PROMs from the top card in M104 and read their eta 1 parts to verify what is on what lookup page. CMEN0101 CHDN0101 i.e. our Address Hex run values runs values Page Number ----------- ---------- ----------- ----------- 00 ff 02 -> ce 01 -> e1 0 100 1ff 01 -> ee 00 -> f6 1 200 2ff 00 -> fe 00 -> ff 2 300 3ff 00 -> fe 00 -> ff 3 400 4ff 00 -> f3 00 -> f7 4 500 5ff 01 -> dc 01 -> e7 5 600 6ff 02 -> bc 02 -> ce 6 700 744 all 1:1 all 08 7 I put these on a floppy disk in format 82 Exormax in file names CEMN0101 and CHDN0101. From the front of a CTMBD the Lemo test points of the backplane timing signals run: J K L M N P R S A B C D E F G H X_CLK is TS&S F pins dir 70 comp 38 Energy Lookup A8 is TS&S D pins dir 68 comp 36 Energy Lookup A9 is TS&S E pins dir 69 comp 37 Energy Lookup A10 is TS&S J pins dir 22 comp 23 Scope Captures on Tuesday and Wednesday: #7 Y= Data Bit, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs 100 ns/div #8 Y= Data Bit, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs 40 ns/div #9 Y= Data Bit, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs 100 ns/div #10 Y= Data Bit, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs 40 ns/div #11 Y= Data Bit, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs at gap #12 Y= ERPB In_Clk, B= x_Clk, V= 2X_Clk, G= Eng LUM MS_Adrs #13 Y= ERPB In_Clk, B= ERPB EMTot, V= 2X_Clk, G= Eng LUM MS_Adrs file TEK00006 #14 Y= ERPB In_Clk, B= ERPB EMTot, V= Data_Bit, G= ERPB Capture_Data file TEK00005 Yes, extra double checked, Eng LUM Address Lines A8 and A9 are HI this is next to MSA and next to next to MSA. Double verified that what you see in the LEMO's is what you get on the back plane for, X_Clk Eng LUM address A8:10, 2x_Clk. Look at data coming out of the ERPB's on the 4 channel scope when I can also watch Eng LUM MS Address and 2x_Clk and X_Clk. It looks good. I only will write down the top 5 of the 9 bits. eta +3 phi 5 eta +4 phi 5 -------------------------------- -------------------------------- EM HD EM HD EM HD EM HD EM HD EM HD EM HD EM HD 00 00 ff 00 00 ff ff ff 00 00 ff 00 00 ff ff ff ----- ----- ----- ----- ----- ----- ----- ----- D4 L H L->H L->L D4 L H L->H L->L D5 L L L L->H D5 L L L L->H D6 L H L->H L->L D6 L H L->H L->L D7 L L L L->H D7 L L L L->H D9 L L L L D8 L L L L This was done very carefully. L->H means that HI data came out of the CTFE for the address lookup when A10 was Low. The notation implies is that the data bit was toggling and that Low data came out when A10 was HI. L->L means that Low data came out of the CTFE for the address lookup when A10 was Low. The notation implies that the data bit was toggling and that Hi data came out when A10 was HI. Look at and then extract VBD data vs waling EM eta DAC's this is in the file walk_eta_10oct01.txt Also look at 6 other test cases. this is in ttro_6_cases.txt CT Readout Status: There is one extra word at the start of each ERPB card One of the words per ERPB FPGA looks better than the other We are 100% correctly lined up to CTFE data source and the CTFE is making good data. LCA's read in the proper order ERPB circuit boards read in the proper order --> The overall eta,phi readout order is correct. Multipe transport without a new ERPB Capture Data gives stable data in the VBD. Stopping X_Clk in the L1 Cal Trig gives stable data in the VBD. Readout of a static diff ECL bit gives mostly good data in VBD (see below). --> Transport of the data is OK Issues: Something is wrong on all the Build_A aonm Bougie Spark in the LSB going to the HSROCB. It is stuck either Hi or Low depending on what card you are looking at. Most likely a timing problem in the ERPB FPGA shift register. Want one more change to CT_Readout_Helper to allow stopping of the ERPB Data Capture Clock. To burn a new PROM for the ERPB: -------------------------------- The ERPB S-record file generated for the "Xilinx XC1736D DIP" serial PROM is only $f77 bytes long, while the PROM programmer expects a stream of $11bc bytes. Note that the last four bytes of that stream select the device polarity. The Run I PROM was found to be programmed with the last four bytes set to $ff which correspond to "Active-High Polarity". We thus need to pad the byte stream generated by the xilinx software with $ff bytes from address $f77 to $11bb. This is easy to do with the Data IO 2700 programmer. After loading the file from the floppy, click on "Edit | Address Range..." then select "user defined" and set "size=11bc". I imagine you can then directly burn the PROM at this point. To burn the first device (labelled "II.1") we actually saved a padded stream to an S-Record file on floppy and later reloaded this file and burned the device from it. To save the padded file, click on "File|Save as..." then click on "Parameters" and set "user data size = 11bc" while leaving it as a "82 Motorola Exorcisor" format, which seems to be our familiar S-Record. Work Thursday and Friday on Cal Trig Readout We disconnected one of the CTFE connector on the second ERBP from the top of the stack; specifically the connector furthest from the backplane and on the left side of the ERPB as seen from the back of the rack. This should make it the CTFE at phi 5, but only two of the four Trigger Towers serviced by this CTFE. With this CTFE (half of it) no longer driving the ERPB input, we should see zeroes for two adjacent trigger towers, i.e. two pairs of bytes for word #18 and #19. Instead we see Zeroes on four words #38-41. We set high one signal pair at a time and read the events in the VBD: Pair # Spark Spark Spark Spark on ERBP Readout Readout Readout Readout connector Word Word Word Word Forced #38 #39 #40 #41 High 20 $8080 $8080 $0000 $0000 19 $4040 $4040 $0000 $0000 18 $2020 $2020 $0000 $0000 17 $1010 $1010 $0000 $0000 16 $0808 $0808 $0000 $0000 15 $0404 $0404 $0000 $0000 14 $0202 $0202 $0000 $0000 13 $0100 $0100 $0000 $0000 12 $fffe $fffe $0000 $0000 11 $0000 $0000 $8080 $8080 10 $0000 $0000 $4040 $4040 9 $0000 $0000 $2020 $2020 8 $0000 $0000 $1010 $1010 7 $0000 $0000 $0808 $0808 6 $0000 $0000 $0404 $0404 5 $0000 $0000 $0202 $0202 4 $0000 $0000 $0100 $0100 3 $0000 $0000 $fffe $fffe 2 $0000 $0000 $0000 $0000 1 $0000 $0000 $0000 $0000 The $fffe and the $0100 show that the LSB gets lost. the $fffe also corresponds to the ERPB saturating when bit #9 is set in the energy coming from the CTFE. This response showed that the bit ordering gets reversed somewhere between the CTFE and the VBD. It was found that the Spark was expecting a "natural" bit order coming into its P5 while the DC Card uses a "reversed" bit order on its output connector. The cure is to change the Spark FPGA. The fact that we had four null words and that they were about twice too far down the list suggests that the ERPB FPGA was trying to operate in the two-time-slice-mode. This mode is selected by a signal sent to the DC, which wasn't driven. This ECL signal is not received by a ECL to TTL translator and will thus not default to zero without being explicitely driven. Driving this signal helps and we now get only two null words instead of four, and they appear in a more rational place, while still not exactly where we expected. We test each bit again with the new spark_7_2.exo Pair # Spark Spark on ERBP Readout Readout connector Word Word Forced #20 #21 High 20 $0100 $0000 19 $0202 $0000 18 $0404 $0000 17 $0808 $0000 16 $1010 $0000 15 $2020 $0000 14 $4040 $0000 13 $8080 $0000 12 $fffe $0000 11 $0000 $0100 10 $0000 $0202 9 $0000 $0404 8 $0000 $0808 7 $0000 $1010 6 $0000 $2020 5 $0000 $4040 4 $0000 $8080 3 $0000 $fffe The LSB still seems to be missing, but we note that it is still the LSB missing after reversing the order of all input bits. The problem is probably towards the output of the Spark or on the VRB. SCL Hub-End SCL Hub-End work on Tuesday 9,10-OCT-01. The "old" original Hub Controller is SN# 010. The "new" Hub Controller that Neal repaired today is SN# 011. The problem with the new HC was that some pins were not soldered to the circuit board on chips that receive data from the Trigger Framework. Neal had previously repared a problem on this HC that prevented a couple of the Fanout cards from properly receiving data from this HC. The only other thing that was required to make this HC work was to adjust the delay lines in its 53 MHz input. The new HC is currently setup with 5 nsec delay lines in its 53 MHz input. We tested this 5 nsec delay lines setup and the new HC sends out good SCL data with the "short test delay extension cord" in either the 53 MHz or the 7 MHz input to the HC. If you need to swap Hub Controllers you need to move 6 delay lines from the HC that had been running to the HC that you are going to run. Move the following: U62, U63, U64, U65 (near the J3 connector) 15 nsec U24 U25 (the lower pair near the front panel) 1 nsec Do not touch U16 U17 These are specific to individual HC's These are the 53 MHz input delay lines. Neal is going to order some additional 50 Ohm delay lines of: 1, 5, 15 nsec We also tested the old original HC that we have been running and it also worked fine with the "short test delay extension cord" in either its 53 MHz or 7 MHz input. We left the system running with the "new" HC. The problem of no DTACK* when talking to the Status Concentrators in crate slots #7 and #14 was due to open traces in the backplane circuit board. Neal repared this with jumper wires on the back side of the backplane down under the connector shrouds. These slots now work and the Trigger Control Computer can talk with all the Status Concentrators. When putting the crate back together, all Fanout and Status Concentrator cards were put back in the slots that they came from. I started wondering why we do not have a Fanout plugged into slot #17. The reason is that we only have 15 Fanout cards over here. We have 2 spare Status Concentrators at D-Zero and now have a spare HC. Right now we have 2 spare SCL Receivers and 3 that I need to return for testing or repair. We need about 10 more. Ted sent email saying yes, more are ready. I added fans in the back of the SCL crate under the Status Concentrators. DATE: 27,28-SEPT-01 At: Fermi Topics: Work testing the Bougie/Spark, Daniel will get more scope pictures. Testing the Bougie. The readback of the on board source select and the number of words of input data that has come in is done with a common "Data Capture" block. This uses P1 Capture Monitor Data as a clock enable to latches that are clocked by BX_Clock. Thus stick P1 Cap Mon Data HI and you can get a continuous feedback. You can stick it high by writing a zero to register 10 on the CTRO_Helper. Not all of the VRB's were DTACKing when I tried to setup them up from the CTRO_Test_1.vio file. They have been working just fine for more than a month. They ran for days OK last week. Did someone take good ones and give us junk ones ? Drew has been in the crate since last week when things were OK. So,I made a CTRO_Test_2.vio that only tries to setup the VRB in slot #9. You need to physically pull the other ones out of there sockets or they will prevent the VRBC from "seeing" end of scan and such. The M101 CT_Read_Helper is running from two copies of L1 Period instead of from L1 Period and L1 Acpt for this Geo Section. Need to move its connector 0.1" to the left on the fan out box. Running the VRBC from the SCL Hub-End connector for G.S 127 thus I can push data through the system anytime there is any trigger at all. Talked with Daniel in detail about how to make more scope pictures and spread sheet files in the same format. Emailed Dean to verify what eta,phi to look at next. DATE: 19:21-SEPT-01 At: Fermi Topics: Scope work at the BLS, L1 Cal Trig SHED readout, Capture more Trigger Pickoff scope pictures, Exposure Groupe and Foreign per Bunch Scaler Alignment, non-token VBD connection setup, Check Master Clock Timing Using the French Pulser and working with Trigger Tower +1,32 we see: at BLS end the trigger pickoff pulse is 1.9 Volt amplitude and rise time of 270 nsec. At the L1CT end 5/8 of the pulse is 1.0 Volt and a rise time of 280 nsec. The 5/8 comes from the 30 Ohm resistor that is in series with the scope's 50 Ohm input to match the 80 Ohm coax cable. So 5/8 of 1.9 Volt is 1.1875 Volt. This is a CC cable which is 120 ft or 150 ft long (I need to look this up). The principal Fourier component is at about 1 MHz so should we expect to loose about 20% of the signal on this length cable ? Need to look up the old cable frequency vs attenuation data. Made a number of runs reading out the SHED's from L1 Cal Trig. The crate reads out fine. There apprears to be no tool like the Run I ZBDump to let you look at the raw event data from the various crates. The thing that I forgot is that the BSF will put out 2 BSF header words before the Shed's put out their data. Files in \scratch\ to run this are: CTFO_Shed_Test_ Bob_1.rio which outputs the 2 word BSF Header and then the 6 word L2 Header and CTRO_Shed_Test_Bob_2.rio that outputs the 2 word BSF Header and then a truncated 4 word L2 Header. To run this test, configure the following FPGA's: Load the CT_Readout_Helper into FPGA Site #4 on the FM Card in slot #21 of the M101 Middle crate. On the Term Receiver Module inserted into slot #13 of M101 Middle for this test load the following FPGA's Site #17 load BSF_27_1.exo Sites 1:16 load SHED_Ten_1_1.exo Then run the VME-IO file CTRO_test_1.vio Then run the Reg-IO file: CTRO_Shed_Test_bob_n.rio Major rewrite of the Data_to_L2_Cal_PP document. Tighten up all the details and add information about the format of readout to L3. Talked to Leslie and Dean and then pulled out all the NIM junk and HP Pulse generator junk from the Clock Rack that we had as a temporary setup to make random triggers to the Cal precision readout on only legal BX's. Scope Shots Disk #1 n=9 EM +1,32 ps 2ss n=10 EM +1,32 ps Disk #2 n=10 2ss n=11 EM +8,17 ps 2ss n=12 EM +8,17 ps 2ss Disk #3 n=13 EM -8,17 ps 2ss n=14 EM -8,17 ps 2ss Disk #4 n=15 HD -8,17 ps 2ss n=16 HD -8,17 ps 2ss With Michael Begel I checked where the Exp_Grp and Foreign per Bunch scaler are. Tick #1 appears in Exp_Grp Scaler #10 Tick #7 appears in Foreign Scaler #22 Per Bunch Scalers are Numbered #1 through #159. Over the shutdown he would like to move both of them so that 1 is 1. [Annotation added 8-Oct-01: (1) Trics initializes the Exp_Grp Per Bunch Scaler "Tick Select Control Register" with 26 for tick #1, 27 for #2, etc. This is another place that needs to be updated when "the BeamX Spread" is changed via the D0 Master Clock. (2) Trics initializes the Foreign Per Bunch Scaler Tick Select Control Register with 1 for tick #1, 2 for #2, etc. (3) Trics has high level coor-like commands to change the Base Tick Select of the Foreign scalers (but NOT the Exp_Grp scalers). Each Foreign Scaler can be individually adjusted that way. e.g. to send a message to set Foreign Scaler #N to have a Base Tick of X you need the following line in an init auxi MCF (or MSG) file: Coor_L1fw_Msg: "TrgMgr_Foreign_Scaler N Base_Tick_Select X" We could use a similar command for the Exp_Grp Scalers. End annotation] Measure the Master Clock BX marker with respect to Level 0 SE-01. See that CMC BX is 306 nsec before leading falling edge of SE-01. Checked this on Ticks #7, #10, #13. The scope shows a 362 nsec spread but there is a 64 nsec cable to SE-01 and an 8 nsec cable to CMC_BX Marker. The previous check was on 8-10-AUG-01. The target here was 298 nsec so it looks like the Master Clock is early by 8 nsec. I need to start checking this more often to see if it is really moving. What the non token loop Repeater VBD setup looks like is the following: Data Cable +---+ +---+ 32 pair x-->| R |-->----+--->----->------x->| R |-->----+------>-- to VRC +---+ | +---+ | +-------+ +-------+ | VBD | | VBD | +-------+ +-------+ Cntrl Cable +---+ | +---+ | 13 pair x-->| R |-->----+--->------>-----x->| R |-->----+------>-- to VRC +---+ +---+ Repeater input is on the bottom for the Data Cable and on the Left for the Control Cable. Repeater output is Top for the Data Cable and Right for the Control Cable. If you are going to unplug things then do so at the "x". Unplug both cables and the diagnositcs cable from the VRC and put the junper plug into the Diagnostics Cable port on the VRC. The last connected Repeater must have power all the time. In the real system with tokens this is a loop and you just flip the "bypass" switch like we did in Run I. DATE: 11:14-SEPT-01 At: Fermi Topics: Review the Tick Select setup, Tests of Cal Trig Readout Helper, Documentation of BSF setup vs Board Type, Tap the L1_Acpt for Geo Section 126, Setup of the M122 Fanout Box, Move to TRICS 9.3.A, One more Status Concentrator without DTACK*, New Master Crate List, Move CFT LED Pulser signal #3. Recall the current setup of the Tick Selects: Value Selects Who "owns" Tick-Sel AOIT Loaded Tick or uses this -------- ---- ------ ------- --------------- 0 251 21 24 Muon & ? 1 252 4 7 ? 2 253 7 10 SMT & ? 3 254 22 25 CFT & Muon & ? Verified that the Capture HSRO and Transport HSRO signals from the CT Readout Helper were properly being distributed on the M101 middle backplane P1 Timing signal bus. All looks good. You can use any number from 1 through 15 in the normal mode control registers for these two signals on the Ct Readout Helper any you get Capture and Transport signals with the proper delay. Note that the standard setup used in the Trig FW is 1 tick delay for Capture HSRO Data and 3 ticks delay for Transport HSRO Data. We are using TRM SN#21 for the SHED Test of CTRO. TRM SN# 21 came from the MSU Test Rack without an HSROCB attached to it. I attached HSROCB SN# 63. This TRM came from MSU setup for slot #20 (CA=$3A) and was changed to slot 13 (CA=$25). Recall that the TRM uses 4028XL for its Main Array and its Board Support Function. The current BSF for the 4028XL is: BSF_27_1.exo Put the setup stuff for the Shed test of the Cal Trig readout into the file CTRO_Shed_Test.rio in the scratch directory on TCC. Recall that the current use of the SHED is in the Trig FW Global Disable TRM in slot #20 of M123 Top. The Trig FW Global Disable uses the SHED at all main array FPGA sites except for: 1,2,5,6. After studying how the BSF in the Global Disable TRM and L1_Busy TRM's and Individual Disable TRM's were actually setup, I edited the BSF_FPGA_ Programming document so that it now indicates what is actually setup. This document had said that BSF Register 16 in these TRM's was a $2420 but it is actually $2120. $2120 gives you P1(1) -> HQ(0) (Tick Clock) P1(11) -> HQ(1) (Maginot Line) P1(6) -> HQ(2) (Gap Marker) <-- had been LOW. P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data I have taped into the L1_Acpt cable that takes L1_Acpt's for Geo Sections 112:127 from the FOM backplane to the SCL Hub-End. I pulled the L1_Acpt for Geo Section #126 out of this cable and it will be the "non-readout" Geo Section that provides the L1_Acpt to the source of the L1 Cal Trig Data. So L1_Acpt for Geo Section 126 is now routed over to the "Fanout Box" where it is buffered and then continues on to the Cal_Trig_Readout_Helper. So the Cal_Trig_Readout_Helper gets both a "L1_Period" signal from the "Fanout Box" and an L1_Acpt from the Fanout Box. Recall the setup of the Fanout Box: Input Outputs ----- ------- 7 ---> 1:8 8 ---> 11:20 5 ---> 21:25 6 ---> 26:30 and how is the Fanout Box wired up : Input Outputs ----- ------- Delayed L1_Fired_Strobe --> 7 ---> 1:8 -- 8x L1 Strobe to L1 Mask L2 Input TRM -- 4x L1 Strobe to Aux Data L2 Input TRM -- L1 Trig Number FIFO Write -- L1_Fired to L1 Helper L1_Fired_Strobe --> 8 ---> 11:20 -- L1_Period to SCL Hub-End -- L1 Fired to L1AL2 Scaler M123B slot 19 -- L1 Fired to M123B Slot 19 MSA_In_4 ---------+ | +----------------------------------+ | +---------> 5 ---> 21:25 -- L1 Fired to M100 ECL to NIM Converter -- L1 Period to Cal Trig Readout Helper Geo Section 126 --> 6 ---> 26:30 -- L1 Accept to Cal Trig Readout Helper Level 1 Accept Running the Cal Trig all SHED readout test on Wednesday afternoon I put 2 paris of raw and semi formatted dumps from the VBD into the log file. The 2nd one is at about 17:00. Reinhard from Level 2 picked up 5 more SCL Receivers (in addition to the 3 that they currently have). Later he returned one that he had been using but says that its yellow LED no longer comes on. He traded that broken one for a new one. I labeled the broken one and put it in the SCL Parts box. Daniel Mendoza returns an SCL Receiver that was making a 53 MHz clock output that had a 14 nsec period. We start to run TRICS 9.3.A which takes ownership of the SCL Hub-End and for now sets up all registers in it and reads back the status from the Geo Sections both at Initialize Time and just before and just after SCL Init. From earlier work with the SCL Hub-End we knew that there were 2 Status Concentrators that did not DTACK*. Running TRICS 9.3.A we found a new 3rd Status Concentrator that does not DTACK* on reads or on writes. So the list of TSC's that do not DTACK* is: TSC Number VME Base Address counting from SCL Channels of this TSC Crate zero Hex Decimal seen through VI Slot Number ------------- -------------- ---------------- ----------- TSC #2 10:17 16:23 $ 1880 0480 7 TSC #8 40:47 64:71 $ 1880 0600 14 TSC #11 58:5F 88:95 $ 1880 06C0 17 TSC #11 had worked before but it does not work now. CFT people want their 3rd LED Pulser signal moved to 800 nsec after their 1st LED Pulser signal. I moved it to 42 RF Buckets after the first pulser. Work with Philippe and other to make a new official Crate List. This is at http://www.pa.msu.edu/hep/d0/ftp/scl/crate_list.txt. Advertize to management that we need one official maintained crate list. DATE: 30:31-AUG-01 At: Fermi Topics: Master Clock and CFT Pulser time line, LMR-200 to Fermi, VRBC tests and new run of test stand SCL Status signals, Alpha Scaler pcb, Investigate the L1 Cal Trig calibration issue, Technician Jobs Changed Time Line #18, the 2nd LED Pulser signal for the CFT group from 320 nsec after their 1st LED Pulser signal to 470 nsec before it. Master Clock would not re-load. The Clock Gui would not come up. Showed an error something like, "Notebook instance has no attribute setnaturalpagesize. This problem is related to the recent change in Python versions. Fritz quickly fixed it and all worked again. People were running so I down loaded just the Dynamic A/B timelines in the #1 Sequencer. It has been about 2 weeks now and no problems with the Master Clock loosing time line programming. Brought the 1000 ft spool of LMR-200 to Fermi this week. Dean is on hold with the final lengths for the delay cables. We make a test of a new version of the VRBC firmware. This has a different "FIFO macro". In the test stand running 4 L1_Acpt's then 4 L2_Acpt's it was now sending out the right buffer numbers in the messages to the VRB's. Running it in tests in Trig FW readout we did the "assert L2 Busy from a different Geo Section to hold the L2_Acpt's, let a number of L1_Acpt's take place, then release the L2_Acpts. The problems were: missing transfers to VBD (missing events), skipped L3_Transfer numbers, Lost buffers i.e. each time it would hold few events before going L1_Bz, and asserting L2_Bz when we knew that it was not holding any events that had been given L2_Acpt's. It did work OK when just given L1_Acpt L2_Acpt pairs. We forgot to verify that this version also worked OK just so long as there were only 2 L1_Acpt's before getting the L2_Acpts. Daniel wants to be able to run this from his test stand and control it via the SCL Status signals. So a 25 mil pitch cable was run from his test stand over to Mike Utes test stand and then via the "B" side of the adapter card and the standard 40 conductor 50 mil cable down to the Trig FW. At the Trig FW DAniel's test stand uses cable "x8" to make the final run into the rack with the SCL Hub-End. It is labeled both "x8" and "Daniel's" and "98". It plugges into Geo Section $98. Trigger Task force calorimeter trigger meeting in the morning in the black hole. Tried to push to get the Alpha Scaler circuit board finished up. I added the two connector mounting holes (for 4-40 or M2.5 hardware) for the 68 pin AMP connector to the circuit board. I then made the 7 Gerber files, aperture table, drill file, and wrote the instructions for manufacturing and assembly of the circuit board. This is ready to zip up. I made 5 plots and printed the instructions and left them for Adam to approve. For something this size Mentor takes 13 directories and 144 files. Adam's phone number is x6904 Pat Liston phone number x2332 and his email is pml@fnal.... Sent them the zipped manufacturing data. Also passed to Pat Liston the description of, drawings of, and examples of the CTFE to Term-Attn cables. I need to add the Molex part numbers to this and get it too him on Monday or Tuesday. There have been two "funny" issues with L1 Cal Trig. During the runs that used HD Veto, the HD Veto has to be turned very low before it cuts into the rate very much. Is this really what the Physics looks like ? They were setting the HD Veto to 0.5 GeV before they got much of an effect. One point is that the HD signal is known to be only 60% of the size that it should be. We did download the Trig Config and then by hand read back the values in the registers that hold the Ref Set thresholds and all was OK. EM_0 12 GeV HDV_0 0.5 GeV read back 55 and 9 EM_1 12 GeV HDV_1 3.0 GeV read back 55 and 19 EM_2 12 GeV HDV_2 5.0 GeV read back 55 and 27 EM_3 12 GeV HDV_3 inf GeV read back 55 and 255 This all looks rational so it is not some problem of TCC not setting up the HD Veto registers correctly. The second issue is that they see events with only 6 GeV or so in the leading EM object (according to the current percision Cal readout calibration - but it should require at least 12 GeV. There is some hint that the EM Trigger Pickoff signals are off by a factor of 2. If the pulser is set to put 10 GeV into the Cal (according to Cal percision readout) and is hitting 2 EM cells, then we see a bump of about 38 GeV at the trigger pickoff instead of 20 GeV. This all depents on the pulser shape so who knows what this really means. There is also something that I don't understand about the BLS resistors having been picked to give the 2V = 64 GeV at a point x nsec (100 or something) after the pick off signal started to rise and not at the top of the pickoff signal. I got the 7 LMR-100 MCX to SMA cables from Victor so now we have some spares. Pete got a replacement fan for the "ceiling fan above the M114-M125 row of racks. It is now plugged in and running again. More scope shots of +8, 17 HAD. Jobs so far on this list for technical help from Fermi. Action started on numbers: 2, 7, 8, 9. Ready to go on number 1. 1. Make the LRM-200 SMA delay cables for Calorimeter precision readout. About 13 cables. 2. Make more LMR-100 SMA MXC patch cables for the SCL Hub-End About 10 cables. 3. Make and run SCL cables to the L2 Test Stand on 2nd floor fixed counting house 3 or 4 more cables. There is one installed now. 4. Make 8 standard 34 conductor twist&flat cables to run the Answers from the L2_Global stage into the L2 Hardware Framework. 5. Design and make a "test boxes" for each end of the SCL Status cable. 8 RS_485 receivers with LED's in one box. 8 RS-485 transmitters with toggle switch inputs in the other box. Small and battery power would be nice. 6. Package up the current "SCL Test Receiver" that sits in the yellow plastic tray on top of the MCH-1 air conditioner. 7. Verify that the proto type wiring harness for the Term-Attn-Brd for the L1 Calorimeter Trigger is OK and see about getting then made at Fermi (or elsewhere). 8. Take care of getting manufactured the "Alpha Scaler Paddle Board" for the L2 system that is all layed out but that I have not had time to send to production yet. Small paddle board, 5 connectors, quantity = 41 for Jim Linnemann & Adam Yurkewicz. 9. Make brackets to install the 2 SHAE 1553 "Data Acquisition & Control" boxes on top of M103 for the L1 Cal Trig power supply voltage monitoring. Get all the cables plugged back in that bring samples of the power supply voltages from inside the L1 Cal Trig to these 1553 boxes. Setup all the "data base type stuff" for watching these voltages and sending alarms if there is trouble. Make the cables to sample the voltages in the Trig FW and connect them the this voltage monitor setup. DATE: 22:24-AUG-01 At: Fermi Topics: Calo Hot Towers, TRICS 9.2.L, VRBC Tests, Calorimeter Mapping GUI, Fiber Optic split out of Trig FW for L2-Global, Connect L1 Cal Trig Voltage Monitoring, scope pictures As I watched it this afternoon, And-Or Input Term #136, Jet_Ref_Set_0 Count_Comparator_0 was running anywhere from 6 KHz to 36 KHz. Watching Trigger Tower +3,16 Hadronic it does appear to look a little funny. At some low rate, e.g. one every 5 or 10 seconds, there is a pulses of about the right shape with about 8 GeV of energy but they come about 750 nsec after the BX. Something is funny but it is low rate. For now leave it plugged in. TT -4,25 Hadronic is the one causing trouble. A noise pulse of about 150 mV about every 2 usec. A noise pulse of about 300 mV at a couple of KHz. There are periods of 10 to 20 usec when the signal from this TT looks OK. Unplug TT -4,25 and leave it unplugged. With -4,25 removed, the rate for And-Or Term #136 is in the range 875 to 900 Hz with a D0 Luminosity of 4.9E30 and appears stable. This afternoon at about 5:45 we stoped the Trigger Control Computer (TCC) so that we could start running a new version of the TRICS program. Begin running version 9.2.L of the TRICS program on Trigger Control Computer D0TCC1 to fix two problems in the operation of the Trigger Framework. 1. Monitoring data from the L2_Hardware_FW was not being updated during periods when L2_Decisions were not being distributed, e.g. during periods when the distribution of L2_Decisions was blocked by an L2_Busy from a Geographic Section. This has been fixed and L2_Hardware_FW monitoring data is now always updated about every 5 seconds. 2. During the SCL Initialize process, during the time that the SCL Initialize signal was asserted, the last L2_Decision message that the L2_Hardware_FW was trying to distribute could have been distributed instead of being deleted by the L2_Hardware_FW. This has been fixed. Now, as per the design specification, no L2_Decisions (or L1_Acpt's or anything else) will be distributed during the SCL Initialize process. NEED TO VISIT THIS AGAIN when we start using the Roger Answers FIFO. VRBC Tests. Asserted L1_Busy before it was buffering 16 events and it was "loosing" buffers, i.e. each time it would hold fewer events. Was asserting L2_Busy when it should not have been buffering any events of the type passed by L2 and awaiting readout to L3. When you would ask it to buffer more than 2 events and then give out all the L2 decisions it would send out fewer than it was asked to buffer and skip some or duplicate some L3 Transfer Numbers. To run the Calorimeter Mapping GUI Display do the following on an online machine: > setup D0RunII t01.46.00 > /online/config/cal/map/cpmap & This lets you map between the various coordinate systems and look at the capacitance of Calo cell and Cable Lengths and a lot of other stuff. Reinhard Schwienhorst asked that the Trig FW Tick and Turn Number Scaler optic cable be split and a copy shipped to the L2 rack M121. So I did a permanent type of installation on this splitter. It is installed along with the rest of the optic cables in the pass through under the M124 fan. This lets it reach from the Tick and Turn scaler in M123B Slot 21 the whole way to Ch 0&1 of the VRB in Slot 18 in M124. So the main path for the Trig FW readout has no extra splices or cables in it. I used the "Read_VTM_Optic_Power_2.vio" command file to look at the optic power in this channel before and after the split. YES use the _2 version of this file. Daniel's reading from 8-AUG-01 $5d -1.97 dBm My reading today before any work $5f -1.88 dBm nothing plugged in $01 -21.65 dBm with the split $35 -4.41 dBm Check the next day $31 -4.75 dBm From Daniel's 30-JULY-01 note (4) Adjusted to the scale V(mv)=(5/256)*V(read) ADC reference voltage = 5 Volts, 8-bit ADC (5) Adjusted to the scale P(dB) = 10 log ( Vread(adc_counts) * (1.58/4.52) * (5/256) ) where (5/256) is the adjustment of the ADC converter scale and (1.58/4.52) is the adjustment of the scale provided in the VTM documentation: +2 dB = 4.52 Volts -13 dB = 0.150 Volts So this simplifies to P(dBm) = 10 log ( Vread(adc_counts) * 0.00683 ) From the FTM-8510 Transmitter puts out: Min -1.5 dBm typ -0.5 dBm Max +0.5 dBm FRM-8510 Receiver requires at least -13 dBm for BER of 10E-12 requires at least -14 dBm to assert receive signal detect. At some point we need to go through all the channels in Daniel's 8-AUG-01 note and understand what is going on with the channels that read low optical power e.g. -6 dBm. Re-connect Cal Trig Voltage Monitoring for the L1 Cal Trig (which could be expanded to include the Trig FW's. The 2 boxes to connect the long shielded cables that run into the L1 Cal Trig to the short flat cables that go into the Shea 1553 boxes are now mounted on top of rack M122. The Shea 1553 boxes are also mounted up there. All the long cables from the L1 Cal Trig Power Supplies are now plugged in. Need the 1553 connection and line power. Need to find the Run I documents. Started connecting scope trace from high capacitance channel. Working on +8,17 HD. Maris went to the TTF meeting. Need to bring another 500ft spool of twisted pair to Fermi DATE: 15:18-AUG-01 At: Fermi Topics: Check operation of the VRBC when it is asked to actually buffer events, Small progress on CT Readout, Delay cable timing study for Cal precision readout, cable length to external L1_Fired_Strobe, L2_Helper knows the spread, Measure when L1_Decision is issued wrt D-Zero BX, L2 FW Monitor Data goes stale, Put TT signal scope shots and spread sheets on the web for +1,17 EM HD, Booted Master Clock slot #1 processor and down loaded the TL's. Tests of VRBC-VRB-VBD when L2_Bz is asserted for a few events at a time. The VRBC hangs with the VRB's stuck scanning. This is because the VRBC is issuing scan messages to the VRB's as soon as it receives the L2_Acpt for event "N" instead of when it has finished reading out event "N-1" Daniel will work on this problem. Until then we continue to run the "single buffer" VRBC in the Trig FW to mask this problem so that SMT and CFT and such can continue to operate. The single buffer VRBC in the Trig FW forces a L1_Acpt L2_Decision interleave and masks the problem. Got the CT_Read_Helper plugged into Selector Fanout Helper B so it is now receiving its Master Clock signals. The cabling is now installed to take the CT_Read_Helper output to the two TOM_PB's in the M101 crates. The cables run from the CT_Read_Helper to the TOM_PB's on the back of slot #1 of the two crates in M101 are 10 feet long. The two twisted pair runs are in to bring the L1_Fired_Strobe (aka L1_Period) signal and the Geo Section L1_Acpt signal for the Cal Trig non-readout G.S. to the CT_Read_Helper. Right now these are both plugged into the L1_Fired_Strobe so it is easy to see it cycle. The twisted pair cable is about 1.66 nsec per foot. The 26:28-JAN-2000 log book entry says that the FOM++ data has 65 nsec setup at the SCL Hub-End. Install-Remove the delay cables in Geo Section hex 48 for the Calorimeter timing measurements. Thursday: Move G.S. 48 delay to 65 nsec + 32 nsec = 97 nsec Thur AM just before the store started Move G.S. 48 delay to 65 nsec + 16 nsec = 81 nsec 18:30 Move G.S. 48 delay to 65 nsec + 32 + 16 = 113 nsec 19:35 Move G.S. 48 delay to 65 nsec 20:40 Friday: Move G.S. 48 delay to 65 nsec + 32 nsec = 97 nsec 9:50 Move G.S. 48 delay to 65 nsec + 16 nsec = 81 nsec 11:45 Move G.S. 48 delay to 65 nsec + 32 + 16 = 113 nsec 12:45 The cable brinning the the L1_Fired_Strobe from the FanOut in M123 to the Diff_ECL to NIM converter in M100 to give a L1 Fired signal to Ron for SMT noise studies is about 30 ft long or about 48 nsec long. The L2_Helper also has some knowledge of the spread between "Current front end time zone" and the "L1 Decision time zone. I did not know this. This is also in a logiblox shift register but I do not yet understand all the reasons why it needs to exist. It is currently set for a "bus width" of 25. I must check and see where the L2_Decisions are coming out. This shift register has to do with telling the L2_Helper when there is an open SCL slot. This is in the input buffer block of this design. Made a measurement of the actual time when the L1_Decision leaves the L1 Trig FW wrt the beam crossing marker signal from the Master Clock. This is done by looking at the L1_Fired_Strobe signal that is brought external to the FW for the SMT people to use in their noise measurement stuff. The path here starts at the buffered fanout for the L1_Fired_Strobe in the back of M123 and goes through 48 nsec of twisted pair to the Diff-ECL to NIM converted in M100. From the Diff-ECL to NIM converted there is a long RG58 to the SMT people in the 3rd floor for their noise measurement and a short 16 nsec cable to the scope I'm using. So the scope signal that I see is 48 + 16 = 64 nsec later than the actual L1_Fired_Strobe from the Trig FW. There is an 8 nsec cable from the D-Zero BX marker output from the Master Clock to the scope. The scope shows a rock stable 3.42 usec difference between the Master Clock D-Zero BX marker and the L1_Fired_Strobe. This is with 0.01 usec resolution. Because of the cables the actual L1_Fired_Strobe must be 64 -8 = 56 nsec earlier than this (and delay in the Diff-ECL to NIM converter would make it earlier yet. Putting this together says that the tick with L1_Decision starts 3.42 usec minus 56 nsec = 3364 nsec after the real D-Zero BX. 3364 nsec is 25.52 ticks. This measurement was done by using And-Or Term 249 so that we would only fire on the first BX in each Super Bunch so there is no ambiguity about which D-Zero BX marker the L1_Acpt belongs to. This was confirmed by looking at the logic analyzer on the SCL Receiver to verify that we were only firing on the first BX in a Super Bunch. It looks like currently the Capture_L2_Monitor_Data signal is only issued when the L2 Hardware FW is actually issuing L2_Decisions. When no L2_Decisions are being issued, either because nothing is running or because the runs are blocked by a system stuck L2_Busy, then the monitor data goes stale and you can not see who is stuck L2_Busy. HOW does the Capture_L2_Monitor_Data work when the system is blocked from distributing L2_Decisions. Because, even in normal operation, there is a different delta_times between when successive Cap_L1_Monit_Data's and successive Cap_L2_Monit_Data's are issued, it makes it hard to calculate things like percentage L2_Busy based on the L1 delta time. Need to remove the Init_Post_Auxi stuff that sets up some thresholds and Ref sets and stuff in the L1 Cal Trig. Fritz has pulled the "old C program" from the boot configuration for the slot #1 processor in the Master Clock crate. Friday evening, boot the slot #1 processor, and down load the time lines. This includes a small change in the CFT #2 LED Pulser signal. When the slot #1 processor RESET button was pushed I saw no change in the master clock modules. Need to verify that they do or do not listen to VME SYSRESET. When the slot #1 processor rebooted there was no change in the master clock modules so the "old C program" real is gone. Updated the Master Clock instructions to better explain the plug unplug Ethernet status. Skip the TTF meeting. Note to Leslie-Michael of tech jobs. Finished getting the Trigger Tower scope pictures and spread sheet data together for +1,17 EM & HD and got it on the web. Need to bring another 500ft spool of twisted pair to Fermi DATE: 8:10-AUG-01 At: Fermi Topics: Add buffers to Fanout Box in M123, Trouble again when the FW is off, Connect the SCL Status lines to Mike Utes's Test Stand And-Or Term to select the last BX of each of the 3 Super Bunches Problem with G.S. $35 --> L2_Acpt when L2_Busy is a global problem, More Calo SCL delay cables, Bring more cards to Fermi, Verify Master Clock Timing, More scope shots of real TT signals, L1 Cal Trig turn off, TTF meeting Muon saw a problem that when their G.S $35 asserts L2_Busy, the FW still issues L2_Acpt's to that G.S. Verify that at Fermi we are running L2_BAD ver 3 rev 1. This was made on 5-MAY-2001 and was made for 4036XLA so this sounds like the right stuff. There is evidence that the L2_BAD programming by TCC was correct from the 3-JULY-2000 log book entry about L1AL2 scaler testing. Philippe spots a problem in the loading of the registers in the L2_BAD's that control which L2_Acpt AND L2_Busy will go into the OR the output of which can block (delay) the issuing of an L2_Decision. These were being setup so that none of the AND's was going into the OR, i.e. so that the Busy input to all 128 of the AND was tied low. TRICS 9.2 Rev K has the fix for this problem. So this was not a problem of just G.S. $35 as reported on Monday but was a global problem, i.e. we were not blocking L2_Decisions that would send an L2_Acpt to a G.S. that was reporting L2_Busy. We need to do more checks of all of this and learn how to read all the scalers and know if the thing is stuck waiting for a Busy Accept conflict to go away. Added two new sections to the "Buffer Fanout Box" so that we may have a buffered version of the Global L1 Acpt Strobe outside of the Trig FW (e.g. as is being used to send the signal to the SMT "noise monitoring". Added the two new 1 in to 5 out buffers as described below. The current detailed description of this fanout box is: What is in the Trig FW FanOut Box M123 Back Middle ----------------------------------------------------- As of 31-JULY-01 the FanOut Box had 2 sections. They are: 7th input pin pair --> 1st through 8th output pin pairs 8th input pin pair --> 11th through 20th output pin pairs The chips that are in are: U23, U20, U19, U24, U25 Both inputs are using U25. U25's 3 unused sections look clean and these would be the 4th, 5th, and 6th input pairs. The 1st through 8th output pairs use chips: U23 for the 1st through 5th output) and U20 for the 6th through 8th output. I'm not certain what pull down terminator resistors are used. U20 also drives the 9th and 10th output pairs but one would need to be careful connecting up to the inputs of these sections of U20 to make sure that there were not additional pull down terminators connected to these inputs. The 11th through 20th output pairs use chips: U19 for the 11th through 15th outputs and U24 for the 16th through 20th outputs. I'm not certain what pull down terminator resistors are used. We added two more sections, each with a 5x fanout, on 9-AUG-01 5th input pin pair --> 21th through 25th output pin pairs This uses all 5 sections of U21 as the output driver Its inputs can be terminated by using just pins 1,5,6 on R63 6th input pin pair --> 26th through 30th output pin pairs This uses all 5 sections of U22 as the output driver Its inputs can be terminated by using just pins 1,5,6 on R61 Power was clearly turned off for this. When turning power back on and trying to re-configure the FPGA's, TRICS would just immediately say "DONE" and not actually do anything. I did this enough times to that I'm sure it is in the log file and then killed TRICS. So the file to look at is the one that end Thursday morning 9-AUG-01 at about 8AM. Started a new TRICS and configured and initialzed with no problems. Three very other strange things happened. SMT SVX chips started drawing lots of current when the FW was first turned off and when it was turned back on. Dean's Cal blew fuses that protect the SCL Receivers and perhaps blew one of the Receivers. Muon front-end DSP's crashed because they thought that they were getting an unmanagable pile of interrupts (L1_Acpt interrupts or L2_Decision interrupts ??). No idea how this could have happened. So the idea now will be to first stop the SCL hub-end clock, so that the SCL can only put out sync frames with no Trig FW data, and then work on the FW. We have a control bit in the SCL Hub-End that lets us do that. We should make it menu items. Verified the Master Clock BX Marker output vs the Level 0 SE01 pmt signal. Their relative timing looks exactly the same as before. See the log book for 24,25,26,27,28-APR-01 for all the details. Connect SCL Status lines to the Mike Utes test stand in the 3rd floor electronics area. This was done with the 40 conductor cable and Status_PB at each end. The Geo Sections to the Mike Utes test stand are G.S. 8 and 9. This is listed in the 11:13-JULY-01 log book entry. This is using the Status_PB #4 pair. I will use 2 of the 4 extra stub lines to run into the Trig FW Rack that I installed when I installed the Status_PB's for Dean's Status lines. These stubs into the Trig FW are labeled x8 and x9 which leaves 2 stubs still as spare x7 and x10. The wiring for this is: Cable from Cable Into Geo Section SCL Receiver Status_PB Trig FW ----------- ------------ --------- ---------- 8 8 4_A x8 9 9 4_B x9 In the Utes test stand the VRBC uses G.S. 9 (so it is connected up) and the Sequencer Controller uses G.S. 8 (so to make it the same as the rest of the Sequencer Controllers G.S. 8 is not connected at this time). People want an And-Or Input Term to select the First BX of each of the 3 Super Bunches and another And-Or Term to select the Last BX of each of the 3 Super Bunches. The best and only clean certain way to do this is to send it through the SCL_Helper Function. But I can not do that because there are no spare channels of SCL_Helper function. So I will make up the signals on the last two lines of the Master Clock (i.e. Time Lines 21, 22) but then I will need to hunt around to get them lined up right. If we change the Spread between the Current Time Zone and the L1 Decision Time zone then these two Time Lines will need to be adjusted. The idea is to bring them out of the Master Clock on Trumpeter Cable and take them to And-Or Inputs 249 and 250 which have been until now Skip Next N #2 and Skip Next N #3 but they were never used. The "hunt" showed that offset values of +207 through +213 got the First/Last BX in SB signals to the Trig FW at the right tick. Bigger offset numbers mean that the CMC changes values earlier and thus there is more setup time. I will leave it at 211, i.e. lots of setup and 2 RF Buckets of hold. It is possible that things looked just a little funny at 210, i.e. never saw the wrong tick but perhaps some times the And-Or rate was 10 or 20 Hz less than 3x the revolution rate. I updated the list of connected And-Or Terms, and sent a note to the appropriate people. Provided more LMR-200 delay cables to Calo. There now are: 65 nsec, 32 nsec and 16 nsec cables which lets them get up to 113 nsec of delay. Sandy said that the 1000 ft spool will not be here for another 2 weeks. It was promised on the 8th AUG. Bring some more cards to Fermi as spares and also for use in making a first step in L1 Cal Trig readout. Bring the following: TRM SN# 21 This was pulled from the MSU Test setup AONM SN# 5B This is an AON and has HSROCB SN# 13 on it AONM SN# 26B This is an FOM The idea is to put the TRM in the M101 Mid and load SHED's into it and make that readout. Got another scope shot of an HD signal. Same TT as last week. and files are in the normal order, i.e. eps, spreadsheet of Ch1 spreadsheet of Math. This was at 16:25 on the 10th. The L1 Cal Trig shut itself off on Friday afternoon or else someone bumped a button and turned it off. Daniel got to start it back up. It came back up and was happy. DATE: 1:4-AUG-01 At: Fermi Repair the Geographic Section $38 cable, Move L2_Helper CMC signals from SFO #4 to SFO #7, Run Single Chance Test - causes trouble for VRBC and Seq Cntrl, SCT looks for 26 and get 35, Setup SFO #4 for Cal Trig Readout, Install FM Card for Cal Trig Readout Helper in M101 Mid, Terminal Server cable to Master Clock Console Serial Port, Scope Shots of Real Energy deposits, Free up space on DoTCC1, Exposure Group Talk, TTF meeting Tom Diehl had reported a problem in getting the SCL Serial Data signal at Geographic Section $38. The problem turned out to be in the MCX connector on the LMR-100 MCX to SMA cable. It may have been broken on Saturday when a new small patch panel was installed on top of the SCL Coax patch panel on top of M124. This new small patch panel is for timing adjustment cables for the Calorimeter precision readout and is right next to the SCL coax cable for G.S. x38. The broken cable is one of the 5 foot small LMR-100 SMA to MCX cables that, in the past, we have had a lot of trouble with. It looked like the center pin in the MCX connector was not really soldered. Reworked some Selector Fanout to Level 2 Helper cabling to free up a Selector Fanout for the M101 Cal Trig Readout. The L2_Helper FPGA had been getting some timing signals from the 4th Selector Fanout, but these same signals were available from the 7th Selector Fanout and the 7th SFO had only one cable connected to its Carmen_PB. The 7th SFO is often called the "A" Helper SFO that is, its job is to make Master Clock signals for the Helpers anyway. The L2_Helper had been using only the 6th and 8th pairs of signals on the 26 conductor T&F cable running to it from Selector Fanout 4. This means that it is only using SFO channels 1 & 2, i.e. it is only using Time Lines 3 and 7, that it is only using the Interaction Marker and the Helper Clock. Now on this same 26 conductor cable the L2_Helper is getting these same signals from SFO #7. It still gets the Interaction marker (aka live BX, i.e. CMC Time Line 3) from Ch #2 of the SFO on the 6th pair on the 26 conductor cable so no change at all there. It now get the Helper Clock i.e. CMC Time Line #7 from SFO Ch #0 which is on the 10 pair on the 26 conductor cable. So at the L2_Helper P2 Rear_PB input I just had to move this one 6" long single signal twisted pair cable so that it now picks up the 10th pair from the long 26 conductor cable. I also installed terminator resistor on the 2nd, 4th, and 8th pairs of the long 26 conductor cable, i.e. to terminate the selected clock, Ch #1 and Ch #3 from the SFO. The CMC connections to the 3 Helper Functions in the Framework is described in http://www.pa.msu.edu/hep/d0/ftp/l1/framework/timing/ master_clock_to_helper_func_fm.txt I ran Single Chance Test before doing all of the above and ran it again afterwards. This was just for 1k looks and all was OK. This was testing L1 and L2 FW's. But I could not test the scalers because the SCT Test thinks that the spread between Current and L1 Time Zones is 26 and now it actually is 35. There was *trouble* from running the Single Chance Test Diagnostics. After running it the VRBC's (i.e. ours and CFT and SMT) did not return to sanity when they were told to initializa. They were just "hung". They only way that we found to wake them up was to power cycle their crates. Also something in the Sequencers or Sequencer Controllers or that whole chain was hung and would not wake up when told to initialize or down loaded to. Power cycling the sequencer crates fixed that problem. The general plan i.e. RULE from now on is to turn off the DC power to the SCL Hub-End when running Single Chance Test. The Master Clock was turned off for some of this work. When it was turned back on the Trig FW FPGA's were configured and then an Initialize was issued. A 2nd Initialize was issued because at some time this appears necessary to make the number of data blocks built counters in the HSRO logic reset properly. But the 2nd Initialize did not do anything. You should be able to see this in the log file. TRICS new that it got the Initialize command but it did not do anything. This is what we have seen before when we have the Master Clock Turned off. So kill TRICS and start it again and all is well. Because Selector Fanout #4 is now free, its Ch# vs selected TimeLine can be changed a little to get it ready to supply signals to the two crates in M101. So the following is the new setup - only Selector Fanout #4 changed. The new map is: Selector Fan-Out --------------------------------------------------------------------- 1 2 3 4 5 6 7 8 9 10 11 12 SLF Ch CFT CFT L0 CTRO SC SC SC FW FW FW FW Num LED LED LUM M101 SCL 124 10A 10B 123 123 122 122 --- --- --- ---- ---- --- --- --- --- --- --- --- --- 0 19 15 11 3 0I 9 7 4 7I 3I 7I 3I 1 20 16 12 2 0I 10 2 5 6I 2 6I 2 2 21 17 13 1 0I 10 3 6 5 1 5 1 3 22 18 14 0 8 8 8 7 4I 0 4I 0 53 MHz I I I I I --> Inhibit Selector Fanouts: 1, 2, 3, 5, 6 are driving Trompeter_PB's or front panel NIM outputs. Selector Fanouts: 4, 7, 8, 9, 10, 11, 12 are driving Carmen_PB's. 4, 7 have 2 T&F 26 conductor cables 8, 9, 10, 11, 12 have 3 T&F 26 conductor cables. The previous Selector Fanout map is shown in the 21-MAR-01 log book entry. Installed an FM Card in M101 Middle to be a L1 Helper for the Cal Trig Readout. This is FM Card SN# 06. It is in slot #21 its address is $3D and its species is $10. I verified that I could download the standard L1_FW_Helper configuration to it site #4 FPGA and that it did not cause trouble for any of the other cards in M101 Middle. I need to update the crate layout map for M101 middle to include this card. We have to decide, is it really just exactly going to be a L1_FW_Helper or is it going to diverge and thus need a new name ? I think it will diverge and that we should start calling the FPGA Site #4 on this FM Card Cal_Trig_Readout_Helper. I checked for Fritz Bartlett which terminal server port the Master Clock console is plugged into. It is port 15. I have put a rational lable on that cable. Fritz showed me to useful commands: version Among other stuff this shows the node name so you can made sure that you are connected to the proper machine casr 1 channel access status report (format) 1 useful to see who is accessing your EPICS records. Record some more Scope Traces right from the L1 Trig end of the BLS Cables. 20:08 EM eta +1,17 about 0.5 Volt differential eps, ch1, math 20:45 EM eta +1,17 about 0.7 Volt differential eps, ch1, math 22:06 HD eta +1,17 out of time ? 0.7 Volt Diff eps, ch1, math Free up some more spare on the D0TCC1 D: disk. In D:\Trics\D0_Log\D0_TRICS_II_Log_2000_05 delete all the log files but leave the short cut files in this subdirectory and do not delete this subdirectory. This frees up an additional 96 MegBytes so that we now have about 152.5 MB free on D; Bring Mail Next Week, AA Batteries for Thermometers DATE: 25:27-JULY-01 At: Fermi TOPICS: Install more Bougie & CTRO cards, SCL to Dean's 5k test stand, Setup-Check power supply M101 Middle, TCC_1's D: disk fills up, Alpha Scaler final count, change in technical support organization, with Ken Johns measure And-Or Term arrival vs BX, power up and verify that L1 Cal Trig is OK, Daniel is back. Install more cards in the M101 middle and bottom crates. Installed AONM SN# 18, 30 and FOM SN# 19, 25. So the setup of the M101 middle and bottom crates now looks like: M101 Middle SLOT Adrs Hex Species THE-Card SN# HSROCB SN# ---- -------- ------- ------------ ---------- 1 - - TOM SN#? 2 04 60 AONM 3 HSROCB 52 3 07 60 AONM 4 HSROCB 53 4 0A 60 AONM 5 HSROCB 50 5 0D 60 AONM 9 HSROCB 54 6 10 60 AONM 10 HSROCB 55 7 13 60 AONM 11 HSROCB 56 8 16 60 AONM 13 HSROCB 58 9 19 60 AONM 14 HSROCB 59 10 1C 60 AONM 30 HSROCB 65 11 1F 60 AONM 18 HSROCB 64 12 22 A0 FOM 19 HSROCB 66 13 25 A0 FOM 25 HSROCB 67 M101 Bottom SLOT Adrs Hex Species THE-Card SN# HSROCB SN# ---- -------- ------- ------------ ---------- 1 - - TOM SN#? 2 04 60 AONM 8 HSROCB 51 3 07 60 AONM 12 HSROCB 57 All 14 of these THE-Cards have: HSROCB's installed, 120 Ohm Terminators installed, 4036XLA BSF FPGA, shorts checked, all hardware checked and tight, can configure the BSF FPGA, and can then talk to the BSF Registers at unique addresses. Recall that the current proper standard BSF configuration to load into a 4036XLA is BSF_27_2.exo We have 3 spare HSROCB's at Fermi SN# 61, 62, and 63. AONM SN# 16 would not VME I/F configure in either backplane even after running 10 minutes with power. So AONM #16 may have some problem. Recall that there was some issue with one of the first Build AONM's needing to "warm up" for 30 seconds or so and then have the power cycled before its VME FPGA would configure. That issue went away in the FW when the first build AOMN's were all replaced with second build AONM's. I think there are some additional notes in the trailer sheets about one other first build AONM once in a while having trouble configuring its VME fpga. AONM #16 back to MSU. Look at and adjust the M101 Mid power supplies. These are the values after being adjusted. This should now be stable with 12 THE-Cards running in this crate. Tom wrt Tom wrt Supply VIPA Supply Tom Gnd Rack Gnd Output Studs ------ ------- -------- ------ ----- +5.0 5.028 5.016 5.080 5.049 +3.3 3.336 3.324 3.351 3.343 -2.0 1.985 1.996 2.093 2.093 -4.5 4.500 4.512 4.594 4.603 The Tom Gnd measured 12 mV negative wrt the rack gnd. Run an SCL Line to Dean's 5k Test Stand this is G.S. $4F and has a Status Cable. This used the solid conductor cable from Adam for a test to see how well this works. Daniel is back. He is going to look at: Data Cable for CT Readout, Optic Splitters, Cable storage 13x 54 ft for Dean, how to read the VTM optic power level. Took papers to Fermi about this and returned papers to Marc on Saturday the 28th about this. TCC's D: disk is full. I noticed this when working on L1 Cal Trig readout stuff. In the log window I saw that it was writing, "Could not Deliver Luminosity Data (Full)". A quick look at the disk and it said 0 bytes free. Big question, is something wrong or did the disk just fill up ? C: where the operating system runs looks OK, i.e. lots of free space. D: where TRICS lives is full D: has 3 subdirectories: \VMS_09NOV1999 this is only 35 Meg Bytes all in a subdirectory called \Trigger \Projects has only 187 Meg Bytes \TRICS has 1.89 G Bytes Under D:\Trics it is the \D0_Log that takes all the space i.e. 1.6 GB Everything in D:\Trics\D0_Log looks OK, it is just full. So expunge the oldest subdirectory in D:\Trics\D0_Log that is delete all the log files in \D0_Trics_II_Log_2000_04 This is mostly log files from April 2000. Leave the subdirectory and the shortcut files back to MSU. This frees up 86 M Byte which should be enough for a month. It looks like I will need to restart TRICS to get it to try to write files again. That's OK because the current log file is 37 Meg Bytes so I need to restart Trics anyway. Restart TRICS. Everything looks normal now. During steady running the only log window messages are: Monitor Data Capture and Luminosity Blk Increment. Make 41 of the Alpha to Scaler circuit boards. The mounting holes for the 68 pin connectors are 2.8 mm diameter, 5.5 mm diameter clearance, spaced 57.93 mm = 2.281" apart center to center, located 1.905 mm = 0.075" forward from the back row of pins toward the edge of the card, max 8.5 mm = 0.335" from the edge of the card. Talked with Adam - he and Jim want me to get the cards made. There has been a change in the organization of FNAL technical people working at D-Zero. Russ Rucinski is the new overall manager and in change of big projects. The day to day supervision of small projects is directed by Jim Fagan. Russ is on the 5th floor and Jim Fagan is at the North end of the trailers South of DAB. With Ken Johns on Friday morning look at the timing of the Muon And-Or Input Terms. The rising edge of the L1 Muon Strobe signal that tells the FW to clock in the Muon And-Or Terms for the 1st live crossing happens about 2.655 usec after the 1st live crossing of a turn. We demand the And-Or Terms 25 ticks after the beam crossing and 25 ticks = 3.295 usec. So it looks like the Muon terms are there with 640 nsec to spare. The display of FIFO depth says about 3 and 1/4 steps of FIFO are in use. This is about 430 nsec. So by this calculation the point is that the FW is still running ahead of time by 640 nsec - 430 nsec = 210 nsec = 1.6 ticks. But I do not think that this is new news. Tested L1 Cal Trig by having COOR setup a Cal Trigger and it looks OK. The display of the TT ADC's looks OK. DATE: 18:20-JULY-01 At: Fermi TOPICS: Install more Bougie cards, Water Leak in L1 Cal Trig, work on Adam_PB, Delay cables for Dean. Install more cards in the M101 middle crate for L1 Cal Trig Readout. slot #8 ID $16 And-Or SN# 13 with HSROCB SN# 58 NO Term Installed slot #9 ID $19 And-Or SN# 14 with HSROCB SN# 59 No Term Installed slot #10 ID $1C And-Or SN# 16 with HSROCB SN# 63 No Term Installed While installing these 3 cards I noticed that all the hardware is pretty loose. So at some point I need to pull the first 6 cards out (the cards that were installed over the past 2 weeks), tighten up their hardware, and put them back in (and the 2 card in M101 bottom too). I assume that the hardware is loose from the shipping to the East Coast to get their BSF FPGA's replaced. All of these cards are setup with the low byte of Spicies ID = $60. Can talk to all of these cards and can configure the BSF FPGA in each of these cards. These 4036XLA BSF FPGA's take the file BSF_27_2.exo Once this is configured you can load register #1 bit value 1 in the BSF fpga to turn on and off the front panel BSF LED. These latest three cards were not tested in place yet. M103 water leak. The water leak is in the M103 radiators, i.e. the radiators between M103 and M104. It is the next to the top radiator of the 4. The leak is in the lower connection to that radiator. It is right where the short header connects to the 1" pipe that runs over to the radiator itself. It is in the stub coming off the header that connects to the 1" pipe. It is in the stub to header joint. It squirts a very small stream out sidewaze - about 10 drops per minute. The air for the upper Tier 1 crate goes through this radiator. Remove shockless G10 and the mud flaps. Remove CTCC Power Pan. Cut the 4 water lines the remove the top and next to top radiators. With air pressure you can see it bubble at the leak. Air hose the radiator and solder over the leak. Once again the mud flaps did keep the water out of the cards. The spray was aimed right at M104 upper Tier 1. It took about 12 1/2 hours to make the repair. Running just the Cal Trig air blower over night with a couple of the doors open did not dry up all the water because it is getting pretty humid, so I started two of the dehumidifiers in 1st floor MCH. I verified that they are draining properly and I sent a note to Pete Simon. | | +----+ radiator |--------+ | | | | looking at |--------+ +-------- M104 side | | | Lower Water | | | Hose |--------+ +-------- leak | * | |--------+ | | +----+ | I need to do something so that we have some protection from water in the Trig FW and in M101. Worked with Adam on the Alpha_Scaler pcb. It is basically ready to go. I just need to add the drill holes and make the drill files and table and the .sh to copy the manufacturing stuff. Worked to get some 54 ft SCL Serial Coax cables ready for Cal next week. Need a patch panel and some way to hange the 13 spools. Need 120 Ohm networks and Kleneex. DATE: 11:13-JULY-01 At: Fermi TOPICS: Master Clock Dynamic programming lost, SCL cables to L2 and where are the "special" SCL runs, L2 Scaler PB with Adam, Close up the communications Crate Install more Bougie and fiber optic transmitters, Test splitting a fiber optic link and running the M101 setup, Event Dumps Formatted and full raw from FW, Dean would like longer SCL cables, Turn cooling water back on in M103. Got here and people reported Master Clock problem. The dynamic lines were all at zero but they had been playing around with the clock control program. They said that nothing was coming out of the TL #17 lemo for CFT LED Pulser Trigger but that its Green LED was on. The cause of them not seeing the signal on the scope was that they did not have a terminator on the open collector NIM output line. So most likely all was well and they killed it. But Mike Begel said that there was trouble a week ago but he was not here to see it himself. I said that I would add the green led's for TL 12,13,14 and 17:22 to the list of what to look for. Pressed the idea that we need to be organized to understand what (if anything) is going on. Could not reload the clock right away because the cluster is down because of a problem in node C. Wednesday night Stu got the cluster running again (by undoing what the service people had done during the day). So Wednesday night I down loaded the master clock with no problem. Thursday AM people say that the dynamic time lines are not running. I check and the green LED's are on. They want more proof so we looked with a scope. So it is believable that nothing was ever wrong until they started to play with the master clock. I edited the instructions for the master clock to include how to check the green LED for the CFT Pulser lemo output and the lemo outputs to the L0 Luminosity system. Thursday PM we did have 2 real wipe outs of the Master Clock Dynamic Time Lines. I talked with Fritz and he agreed so we will run with the Ethernet cable pulled out for a while. I sent out a detailed note and I have updated the Master Clock instructions and Lynn and I have went through the full startup after the power off Friday around noon for SMT noise tests. Ran the two Serial Coax SCL cables over to the first floor Level 2 rack. This is G.S. $20 for L2 Global and $23 for L2 Cal PP. Added patch cords to the patch panel to send signals to these G.S. This was the very last of the Patch cords. Reinhard Schwienhorst wanted a SCL signal on G.S. $24 and did not care about $23 right now so for now the $23 patch cord is being used to send a signal to $24. The list of Geographic Sections is at: http://niuhep.physics.niu.edu/~fortner/d0/algo/unpack/crates.pdf In addition to this we have the following stuff tied up: 2 Serial SCL Cables to Mike Utes in 3rd floor electronics ares these are G.S. 8 and 9 2 Serial SCL Cables to Daniel Mendoza in 3rd floor electronics area these are G.S. $78 and $79 1 Serial SCL Cable to Level 2 Test Stand in 2nd floor computer area this is G.S. $0A Worked on the board layout for Level 2 scalers with Adam. This is stup as a standard 4 layer brd. The fancy AMP 68 pin connector should have its pin #1 0.400" back from the front and the mounting holes are 0.325" back from the front and ??" apart. The pins on this connector are 16 mil x 13 mil and will go into 31 mil hole with a pad diameter of 52 mil. This gives fine clearence with 15 mil trace. This is called ADAM_PB. He signs off on the netlist and the connector layout. We finish the routing. Next week is the fab link. Installed blank front panels on the Communications Crate in the bottom of M124 to close it up. Install more And-Or Bougie cards: M101 middle crate slot #2 And-Or SN# 3 with HSROCB SN# 52 slot #3 And-Or SN# 4 with HSROCB SN# 53 slot #4 And-Or SN# 5 with HSROCB SN# 50 slot #5 And-Or SN# 9 with HSROCB SN# 54 slot #6 And-Or SN# 10 with HSROCB SN# 55 slot #7 And-Or SN# 11 with HSROCB SN# 56 M101 bottom crate slot #2 And-Or SN# 8 with HSROCB SN# 51 slot #3 And-Or SN# 12 with HSROCB SN# not installed All of these cards are setup with the low byte of Spicies ID = $60. Can talk to all of these cards and can configure the BSF FPGA in each of these cards. These 4036XLA BSF FPGA's take the file BSF_27_2.exo Once this is configured you can load register #1 bit value 1 in the BSF fpga to turn on and off the front panel BSF LED. The only problem seen was that when configuring AONM SN# 10 in slot 6 that the VME LED on the next AONM (SN#11 in slot #7) also came on once in a while. We have seen this before with the build A AONM and I assume that the details are written some where in the logs. These AONM cards have 4013L in the VME I/F and Main Array and 4036XLA in the board support. The first 3 cards in the middle crate have 120 Ohm terminating resistors installed on their Global J5 I/O connector. I need more of these resistors at Fermi. This is CTS 750-63-R120 Ohm. There are now 3 spare HSROCB's at Fermi. These are HSROCB SN# 57, 61, 62. Put the optical splitter into the Global Disable TRM optical output. The Global Disable TRM is read by the 3rd channel pair in the 3rd VRB. The optical cables are AMP 503995-4 00 5 meters long 62.5 u cable. One idea is to stick the optical splitters right in the VIPA crate. This may allow the splitter to THE-Card link and the splitter to G-Link Transition Module link to be made with just the splitter pig tale. Friday afternoon there in the log file there are samples of dumping data from the L1CT readout crate both its raw data and the generic formatted dump. Be careful not to look at the dumps from Friday morning when the crate ID was setup wrong and the VBD was setup to read all 4 VRB's. At 9:50 PM Friday there is a full 800 longword raw dump from the Trig FW and a formatted dump of the same event. There is a L1CT dump at the same time. Do not look at it - its VRB had FIFO over run at that time. OK at 23:05 there is a good raw and formatted dumps of Trig FW and good raw and generic dumps of L1CT all for the same event. I tried dumping from VME_Access but it access violated. I tried locally issuing L1FW_ReSynch_L2TS but I do not know how to do it. Dean would like to have his SCL Serial cables be 65 nsec longer. This is 54 ft for the LMR-200 that is 83% c. There are 13 run to him. So get a 1000 ft spool and some SMA males and bulkhead barrels. still working on spool piece from the quench on Monday night I have turned water flow back on in M103. It was tripping the drip detector a month or 2 ago when I had flow in M103. I was surprised at how warm it gets when you have no cooling between two adjacent powered up racks. I cleaned off the drip detector strip under the M103 radiator (i.e. readiators mounted to M103 and located between M103 and M104) It has run 8 hours and no drip trips. So far I see no water leak. DATE: 27:30-JUNE-01 At: Fermi TOPICS: Testing in rack M101, NIM version of Global L1_Acpt Strobe to the SMT radiation monitor people, Run I Trig FW backplane, pickoff scope shots. First Build AONM cards brought to Fermi to be used as Bougie readout cards in the L1 Cal Trig are serial numbers SN: AONM_3, AONM_4, AONM_5, AONM_8 These are the THE_Cards that had a 4036-XLA fpga installed in the BSF location. These cards were installed in the middle and bottom M101 trigger crates just fror a test. I could talk to the registers in the VME I/F FPGA on all 4 cards and I could configure the BSF fpga on all 4 cards and talk to a register in it. The rocks on the two TOM cards in M101 are 12.0 MHz - it is all that I had. We have good TCC to VME connection in the three crates in rack M101. Rack M101 is now getting its AC power from the contactor box above it which is feed from breakers 13,15,17 of the MCR-1A sub-panel. Daniel has the cards plugged into the VIPA crate and he has made a couple of vio files for testing things. He has run the setup in emulation mode and it is happy. He also reminded me that there is now a control bit in some VRB CSR that makes it dissapear wrt the open collector signals so that you no longer need to actually unplug VRB's to make them dissapear. We ran over the SCL cables and the SCL Receiver locks on fine. This is GS #10. The MSU Property Tag #012711 is now on Tektronix Scope model TDS3054 SN# B018372. Magnehelic reads about 0.84 inches water with the fan now running at slow speed. When I got here this week some one had stacked some cards on top of the quilt. During the day on Friday some one used the quilt for a lap robe and then let it fall off their chair and drag on the control room floor. Friday night I folded the quilt back up and put it into double new clean plastic bags, one from each side. Saturday morning some one pulled it out and started using it as a lap robe again. I asked them to be sure to fold it neatly and put it back in the plastic sacks when they were finished with it. Saved the two Run I Trig FW backplanes that look to be the most useable for Run II, i.e. the ones with the least bussing. The rest of Run I Trig FW is now gone. I brought out a NIM version of the Global L1_Acpt Strobe signal for the SMT radiation monitor people. It comes out of the M123 fanout box for this signal and goes over to the rack M100 upper NIM crate FPD LeCroy NIM to ECL converter channel #16. I sent a detailed note to: Bram Wijngaarden and Ron Lipton with cc to Leslie and Mike. Made some scope shots of the trigger pickoff sigal right as it comes out of the BLS cables. This is with the proper 80 Ohm AC coupled termination with 1 meg DC path to Gnd. It looks like the scope right now is setup to make .PCX files. I need to learn about the various scope printer formats. Bring 6u blank panels to Fermi Bring fiber optic transmitters to Fermi for Bougie. ------------------------------------------------------------------------------ DATE: 20:22-JUNE-01 At: Fermi TOPICS: Re-Install L2 TCC, Installation work in M101 Bring L2 TCC with its bit3 PCI expansion back to FNAL and install it (again) in M125, above the air conditioner. L2 TCC (d0tcc2.fnal.gov) is now operational (and this time for real, I hope) - There are currently two Model 618's in the PCI expansion box tied to L2 TCC, accessible as unit#0 and unit#2 (unit#1 is a spare Model 617 from the L1FW). The two L2 optical links tied to TCC are labelled L2TCC000 and L2TCC002. - It can boot either the original Windows2000 but also NT4 which was used in diagnosing our problems. The default is to boot Windows 2000. - To solve all the hardware issues I ended up having to change the following BIOS settings: - turn off the "Plug n' Play" option - enable ALL host PCI slots to be "PCI Bus Master" - To solve the software issues we are using the V2.4 version of the bit3 Model 983 NT support software which is actually meant for NT4. The V2.4 software works satisfactorily with NT4 and Windows 2000, while bit3 "recommends" this version for NT4 only. - VNC is running as a service. Reinhard knows the VNC session pwd. The Trigger account gets automatically logged in at boot time. The beta version of bit3's V3.0 driver for Windows 2000 will not work satisfactorily for us. The V3.0 driver can cause the computer to freeze during boot, or blue screen or reboot when the user application tries to access a bus adoptor whose VME crate is turned off. I have made it clear to bit3 that we cannot use this software. Unfortunately customer demand hasn't been very large and loud. Reinhard should call bit3 about his problems with the test stand setup and get counted as another disatisfied customer. The VME module of the spare Model 617 for the L1FW TCC, along with the spare 25 foot copper cable that goes with it were placed in the grey cabinet by the workbench. The PCI module of this 617 is currently installed in L2 TCC and will be removed next time we add 618 adapters in its PCI expansion box. Finish DC Power Cabling in M101. All 3 backplanes are connected and all fuse and diode blocks are installed. The spare fuses and fuse blocks are left at Fermi. 20 trumpeter chassis mount to BP Need to bring 9U front panel with the cutout to see the VRBC SCL LED's and more #8 hardware to Fermi. ------------------------------------------------------------------------------- DATE: 12:16-JUNE-01 At: Fermi TOPICS: Implement the timing move to issuing L1_Acpts 2 ticks later, resolve the problems with L1 Cal Trig Find_DAC, SCL Cables, DC power cable installation in M101 Install the timing change to move the L1 Decision 2 Ticks later Verify timing before making the change: the spread is $21, The first live accelerator crossing happens at the beginning of current tick $0d, the CMC BOT output happens during current tick $9A. Verify that swapping just the SCL_Helper does the right thing. Yes, firing on the BOT AOIT, i.e. AOIT 244, causes the L1_Acpt to issue during current tick $24, L1 tick $03. Move to the new FPGA's for spread of 35. That is edit and copy to MSU: tts.dci moves to 14.1 L1_trm.dci moves to 6.1 scl_helper.dir moves to 7.1 No change of any kind to the Master Clock. Verify that the spread is 35. Run with a BOT AOIT trigger and see that the L1_Acpt is issued during current tick $24, L1 tick $01. Check the logic analyzer against the time of the real BX. As usual this is at the output of the SCL Receiver with 44 ft of SCL cable. SCL BOT is at: current tick $01, L1 tick $7D CMC BOT is at: current tick $9A, L1 tick $77 first real BX is at the beginning of: current tick $0D, L1 tick $89 Check the AOIT TRM Input FIFO Depth: And-Or FIFO Input Term Depth ---------- ----- 31 22 80 4 128 10 223 19 these look OK L1 Cal Trig Bus Communication Problem I looks pretty clear that it is CBus cycles to +1,27 EM (CA 53 FA 0) that kill the MTG which is at CA 53 and the 29525 Read A/B is at FA 0. This is most likely caused by running the MTG right off of a BBB output. So fix this by adding a MBD in the next to the top slot in the top crate in M103. This was the only spare Run I FW type slot. Set this MBD to MBA 120. 120 looks most othoganal to the other BBA's beging used in the Run II L1 Cal Trig setup. So the CBus part looks like: COMINT --+ +- BBB 152 for Tier 2,3 +- BBB 168 for Tier 1 phi 1:16 eta |1:8| +- BBB 176 for Tier 1 phi 17:32 eta |1:8| +- BBB 200 for Tier 1 phi 1:16 eta |9:16| +- BBB 208 for Tier 1 phi 17:32 eta |9:16| +- BBB 224 for Tier 1 eta |17:20| +- MBD 120 for MTG +- CBus Terminator on MBD 120 Have edited Init_Post_Auxi_L1CT.cio to change the MBA that is used to talk with the MTG card to MBA = 120. Then copied this file to MSU. Finally got a full sweep of Find_DAC to run. There is still some problem that once in a while gives an I/O error, but I have not seen the MTG get over written since it was put on a MBD card. The full sweep Find_DAC file is: Find_DAC_V2_2_A_20010613.tti;10 I copied this file to MSU. Edit the Init_Post_Auxi_L1CT.mcf file so that at the "Call_TT_Info" it gets the above new Find_DAC file. Copy the Init_Post_Auxi_L1CT.mcf back to MSU. The bus errors while performing the Find_DAC are typically 2 post write checks, where the read is typically a $ff, followed by a pre write check where the read value is about right. I have seen this error at the following TT's: +2,1 EM -4,18 EM/HD ? -2,17 HD +3,7 HD -3,1 EM Tried swapping the BBA 208 card and it did not help. Try running with the BBA 224 card pulled out. Did not work. Tied connecting the COMINT CBus to the BBB at BBA = 224 (the input to BBB BBA 224 had previously been skipped) and things begin to work better. Find_DAC sweeps ;19, ;20, 22: ran to completion. Philippe spotted the problem. We are running Find_DAC from VME_Access and this can bump into the CBus cycles from the TRICS Monitor sweeps once every 5 seconds. This will not be a problem when Find_DAC is run from within TRICS. For now the work around is to tell TRICS to "Totally Ignore L1CT" when you run Find_DAC from VME_Access. This works well and 10 sweeps of Find_DAC are made with no errors. Had notes from Muon People that the GS $33 $35 and $38 were not working. I investigates all of them, each of them had something different going on. None of the problems were at the FW end. They will work on verious problems at their end. Daniel reports that GS $6A never shows any L1_Busy. We investigate and it looks like one side of the L1_Busy is open, i.e. the first pair at the red side of the cable. Work on the installation of the DC Power cables in the rack M101. All of the cables are in and the upper end of each cable is lugged and connected. Next week need to install the diode and fuse blocks. ------------------------------------------------------------------------------- DATE: 13-JUNE-01 at FERMI: TOPIC: TFW ignoring FE BUSY from crate 0x6A Eric Kajfasz (from the STM group) reported that the Trigger Framework was ignoring L1 BUSY from G.S. # 0x6A located at MCH2. We found out that the wire carrying this signal over the diagnostics cable was broken somewhere along its path. Trics, in fact, did not show any indication of this G.S. being FE BUSY despite the fact that triggers were being knowingly issued. We flipped the cable over, taking advantage of the fact that the wire at the opposite side is not being used, and terminated at both ends. Then some tests were performed to be sure that the cable carried L1 BUSY properly. ------------------------------------------------------------------------------- DATE: 5:9-JUNE-01 At: Fermi TOPICS: L3 Reset, Reading a full VBD, GS $31, VIPA crate and P3 backplane for L1 Cal Trig readout, Master Clock running on Fiber Optic link, Adjust MAster Clock timing to the Tevatron, Muon would like the L1_Acpt timing moved, Find DAC, check timing of Cal Trig Pick Off signals, More SCL cables run to FCH3, Run 1 Trig FW moved to High Bay. I saw what I thought was a strange situation in the L3 VRC on the first floor MCH. The VBD buffers were still holding old events after a Level 3 Reset. I emailed to Sean and he said that this was normal. They do not drain out old junk event data a L3 Reset time. They wait for the next run to start and then try to get rid of the old junk data on the fly. The other big thing that I learned is that you can not read the VBD when both of its buffers are holding events. You could get confused here becase you might walk in and see that both VBD buffers are full and think that something is wrong with the data from the Trg FW. If you try to do a Formatted event dump you will just a big error right to start with. If you look at the raw data you can see the problem. There is no VBD header at the beginning. All that you get looks like some fixed pattern (or floating data lines). There remains some occasional problem with SCL GS $31 loosing Sync sometimes. No work was done on that this week. Dean had a problem not seeing any Busy signals in the Trig FW for GS $40. The signal levels looked OK and they were connected the whole length of the path. He found some other connector (not the SCL Status connector) not well plugged into his GS $40 controller card. CFT via Lyn Bagby is going to take our L1 Cal Trig VIPA crate. We will get theirs which is known to have a bad slot number ?? that kills VTM modules. Today she did take our spare VIPA P3 VRB backplane (which was a good "NEW" type. They also took our spare L1 Cal Trig VIPA readout crate. Setup of the Master Clock to run on the Fiber Optic Synchronization Signals direct from the TeV RF Building. In the Accelerator Rack the TeV RF signal comes directly out of the fiber optic receiver module for the new fiber that runs from the TeV RF Building to D-Zero. The TeV RF signal comes out of the fiber optic receiver as differential ECL and is transformer coupled and then sent on the long coax run to the Master Clock in MCH_1 where it is received by a discriminator. The Tevatron once per turn marker signal comes from the "Rev Marker A" output of the 279 module in slot 20 of the CAMAC crate. This 279 module is controlled by the encoded timing signals that arrive on the new fiber optic cable that runs from the TeV RF building to D-Zero. The "Rev Marker A" output of the 279 module is a TTL level signal. With inversion it is transformer coupled to the long coax run to the Master Clock in M100 where it is received by a discriminator. In MCH_1 the TeV RF signal coming out of the long coax looks like a sine wave that is 600 mV pp when terminated into 50 Ohms. There is no DC component. It is received by a Philips 711 discriminator that is set for a -30 mV threshold (-0.300 V on the threshold monitor test point). The discriminator is set for a 9.4 nsec period to give a 50/50 output. Outputs from this discriminator feed: the Master Clock PCC TeV RF Input, a 50 Ohm terminator, the AND Logic Unit, and the Fan_Out module. The discriminator outputs are double drive outputs and the 2nd half of the one that feeds the Master Clock PCC RF input has a 50 Ohm Terminator. In MCH_1 the Sync signal coming out of the long coax looks like a 490 nsec long pulse that starts from 0V, drops down to -1.6V, sags up to -1.4V in the 490 nsec, and then rises up to +0.4V at the send of the pulse. It decays down to 0V before the next pulse. The 10% to 90% fall time of the leading edge is about 10 nsec. The fastest part of the edge is at about -0.7 or -0.8 Volts. This raw long Sync signal is received by a Philips 711 discriminator that is set for a -750 mV threshold (-7.5 Volts on the threshold monitor output) and a 18 nsec period. The output of this discriminator feeds: a variable delay line and a Fan_Out mdoule. These are separate double drive outputs so the voltage signal going to both is about -1.5 Volts. The output of the variable delay line feeds another section of the Philips 711 discriminator that is set for a -450 mV threshold (recall it is a double drive signal feeding the delay line input). This discriminator, for the delayed Sync signal, is set for a 16 to 18 nsec period. The output of this descriminator feeds the other input to the logic unit AND. The logic unit AND is a Philips 752 and has it output period set to 18 nsec. The relative timing of the TeV RF and Sync inputs to this logic unit AND are adjusted so that the falling active edge of the Sync arrives first while the RF is in the middle of its zero Volt NIM inactive state. When approximately 4 1/2 nsec later the RF signal falls with its active edge, the logic AND condition will be meet and the logic unit will unit produce its output. This arrangement allows the RF signal's falling active edge to control when the Sync signal is sent to the Master Clock PCC module. The goal is to use the AND to uniquely select one RF bucket for the Sync signal and to have the timing where the AND takes place controlled the the RF, i.e. RF is the last to get there so it controls when the AND happens. This first variable delay line was set to 8 nsec to meet these conditions. This setting allowed the maximum relative drift of the two signals will still allowing the falling edge of the RF to control when the AND condition is meet. The correct relative timing of Sync and RF going in the the AND +-------+ +-------+ +-------+ +-------+ | | | | | | | | RF | | | | | | | +-------+ +-------+ +-------+ +-----+ --------------------+ +-------------------------- | | | | Sync +---------------+ The 18 nsec output pulse from the Philips 752 logic unit AND goes through another variable delay line and then into the TeV Sync input of the Master Clock PCC module. The output of the logic unit is a double drive with a terminator in the second output. This 2nd variable delay line is set in the middle of the range that makes the PCC mdoule happy with the relative timing of its TeV RF and Sync inputs. The delay range over which this worked was 7 nsec through 14 nsec. It was left set at 10 nsec. On the PCC Module both the Sync Delay and the MClk Delay are set to zero. Timing Master Clock to the Tevatron Working with Rich and 150 GeV proton halo the Master Clock was brought into time with the Tevatron. This was done by moving just the Sync_Ref timing, i.e. no change to any Time Lines. The move was big. 605 RF buckets Both the #1 and #2 Sequencers were moved in the same way. Because the Detector is now closed the timing has changed a little. Rich now expects PMT signals at his patch panel in 295 nsec. This plus the 64 nsec cable over to M100 is a total of 359 nsec i.e. we expect the PMT signal 359 nsec after the marker from the Master Clock. Right now it looks like the Master Clock may be early by 8 nsec but this is the closest RF bucket. See also the log book entry from 24,25,26,27,28-APR-01. Still need to look at real luminosity during a store. Moving Timing Again We know that we are putting out the L1 Decision too early. That is it is coming out of the SCL Receiver 27 ticks after the real BX vs coming out of the Trig FW at 27 ticks after the real BX. Sending it out early causes the FW side of the And-Or Term FIFO's to be read early, i.e. before the L1 Muon Trigger has had time to get there data there. I believe that L1 Muon Trig would like a move of 3 ticks but Muon readout is only happy with using 2 more ticks in their history pipeline. So the spread will change from 33 to 35. All of the Current BX SCL data stays at the same point wrt the real beam crossings. The current setup is: tts.dci selects 14.1 this is M123B l1_trm.dci selects 5.1 this is M123T scl_helper.dci selects 6.1 this is M122B 6.1 is a tied design made with xilinx 3.1 software Make the following for a 35 tick spread: l1_trm_6_1.exo scl_helper_7_1.exo <--- Tied scl_helper_7_2.exo <--- NOT Tied tts_15_1.exo First simple test of the Spread 35 FPGA's. First try the L1_TRM and see how much things change in the AOT FIFO Depth Analyzer. Depth in TRM Input FIFO ------------------------ Current 5_1 NEW 6_1 AOT L1_TRM L1_TRM --- ----------- -------- 31 20 22 128 8 10 223 17 19 So it looks like the new spread 35 L1_TRM FPGA does this part OK. Try the Tick and Turn Scaler. Chacking just the Current vs L1 BX numbers on the SCL Receiver, it has moved it from a spread of 33 to a spread of 35. Have not checked that the Tick Selects are still working. To check the SCL Helper do the following. Change just it, run a trig based on one of the markers, e.g. BOT and see where it fires. Find DAC Tried running Find DAC and I managed to kill both TRICS and the VME ACCESS programs. I started in TRICS and had: eta -4:+4, all phi, EM & HD, write file, no details. It got to EM +1,28 (it may have been phi 24 I forget) and then it said in the log file screen something like, "Failed to find DAC Value" or "Error trying to find DAC Value" and it bailed out of Find DAC. OK, let's try sweeping by that eta phi area again. So I set something like: eta +1:+1, phi 18:30, EM only, no details, and I think do not write a file. I think it did one tower and then did a memory violation. bla bla bla you can not write to this address bla bla bla. Trics dies. But no problem, nothing was going on. Fire up a new trics. Launch VME ACCESS Try Find DAC in the same restricted area. This time I'm 99% certain with do not write a file. Start Find DAC and it dies immediately with the same type of access error. All the stuff that I did last week was with show details. Look at Trig Pickoff signals during a store. Time from real BX Volts All EM +1,8 to Peak Amplitude ----------------- --------- 624 0.3 672 0.45 672 0.4 656 0.5 648 0.8 640 0.5 648 0.35 680 1.0 696 1.1 average is about 660 nsec This is all looking at the Monitor output with the old analog electronics. Compare this with the numbers from 3,4,5,6-APR-01 where the average time to peak was 658 nsec. All so looked at some trigger pack off signals right out of the BLS cable. This was at about +1,25 EM. Saw the following: Most of this is Halo. Time from real BX Volts All EM +1,25 to Peak Amplitude ----------------- --------- 688 ? 664 0.25 688 0.15 680 0.125 640 1.0 672 0.24 average is about 672 nsec Delmar ran 2 SCL cables to Daniels work area on FCH-3. This is for a test stand. These are plugged in as GS $90 and GS $91. Need more LMR-200 SMB connectors PE-4522 (I think) Need more LMR-100 connectors for the cables that plug into the front of the SCL Fanout Modules. Need more SMA-SMA bulkhead connectors PE-9071 (I think) Delmar has brought down the Run I Trig FW from the 6th floor to the High Bay. Next week I need to get what we need pulled out of these racks. DATE: 30,31-MAY, 1-June-01 At: Fermi TOPICS: SCL_Init, M101 Cooling Power, Trigger to Cal Pulser, Sync loose SCL Geographic Section $31. To give the serial data receivers at the input to L1_Muon time to re-synchronize, the duration of the SCL_Init signal was increased from 2 msec to 1.0 second. This is a semi permanent change - not just a test. This was done by editing the file D0_Config\scl_initialize.rio The new version of this file was copied back to MSU by the magic process. Cooling water connected to M101 The 3/8" hose is Fermi Stock # 1055-201000 and L1 Cal Trig WBS 1.4.3.1 is DLF Master Clock Time Line #15 set up as a temporary trigger to the French Calorimeter Pulser. This signal from the Master Clock is an 18.8 nsec pulse about 500 nsec before each of the 36 live accelerator crossings. This is pulsing every turn. To get a rational rate this is ANDed with a pulser generator signal (18.8 nsec at about 1 KHz). It is ANDed in NIM. This is stretched to 4 usec (in a NIM Gate Generator) so that the recharge noise of the Calorimeter Pulser is well away from the signal. The ouput of the Gate Generator is used to trigger the Calorimeter Pulser. All of this setup is just temporary and appears to be working OK. Muon is having trouble with the Geo Section $31 cable. They say that the loose sync once every couple of hours sometimes and sometimes it runs for weeks. I ran it with our yellow plastic box test SCL Receiver. I think that I saw it loose sync on this receiver. Work on connecting Power in M101: How the power cables are setup: For VIPA Crate: 4x Red +5.0 Monitor mini "D" connector 4x Blk Gnd 8x skip 1x Red -5.2 4x Red +3.3 1x Blk Gnd 4x Blk Gnd with 1x Blk Common 4x skip 1x Red -2.0 1x Blk Gnd Trigger Crates: P1 10 Points: 6x Red +5.0 3 left and 3 right 1x Yellow -2.0 left 1x Orange -4.5 right P2P3 10 Points: 10x Red +5.0 5 left and 5 right 4x Yellow -2.0 left 4x Orange -4.5 right P2P3 #6 Cables: 4x Red +3.3 4x Blk Gnd How much cable is needed: For the top VIPA Crate: about 70 ft of Red and 70 ft of Blk #6 For the Trigger Crate: about 20 ft of Red and 20 ft ob Blk #6 about 25 ft of Yellow and 25 ft of Orange and 80 ft of Red #14 Lugs: For the top VIPA Crate: 17x PV2-56R-X 6x PV6-10R-E For Trigger Crates (each): lots of #14 lugs 2x PV4-56R-E 4x PV2-56R-X 10x PV6-10R-E Fuse Blocks: 2x 25 Amp to feed +3.3 to the Trigger Crates 2x 50 Amp to feed +5.0 to the Trigger Crates The P1 10 Point connections are: Slot #1 End 10-Point #1 GND 10-Point #2 -12V 10-Point #3 +5V 10-Point #4 GND 10-Point #5 +5V 10-Point #6 GND 10-Point #7 -4.5V 10-Point #8 GND 10-Point #9 +5V 10-Point #10 GND 10-Point #11 +5V STDBY 10-Point #12 GND 10-Point #13 +5V 10-Point #14 GND 10-Point #15 -2V 10-Point #16 GND 10-Point #17 +5V 10-Point #18 GND 10-Point #19 +5V 10-Point #20 +12V 10-Point #21 GND Slot #21 End The P2P3 connections are: Slot 21 Slot 1 vTT vEE vTT vEE vTT vTT vEE vTT vEE vTT +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ L+5 U+5 L+5 U+5 L+5 U+5 L+5 U+5 L+5 U+5 L+5 E A Vtt = -2.0 Volts = Yellow L+5 = Lower Vcc = +5.0 Volts Vee = -4.5 Volts = Orange U+5 = Upper Vcc = +5.0 Volts Bring to Fermi: 3x TOM_PB's, punch for 5 wire AC feedthrough gromet and gromet, all parts for the load resistor on the +3.3 (resistors, plates, mounting screws), Panduit Lugs, #6 wire, P1 Terminators (Ray), 6-32 screws for the 10 Points in M101, Nuts and plated washers for the Power Bars, D-Tape, 50 MHz Rocks, AC power wire and plug and fuse block and fuses and 3x outlet and boxes and covers DATE: 9,10,11-MAY-01 At: Fermi TOPICS: Parts to install M101, Cal Pulser Scope Traces, Drew de-MUX FPGA code, SCL to Platform, Sequencer UnLoads, Calorimeter SCL Status cables Forgot the small Panduit crimp tool. I think that all the other DC power cabling tools are at Frmi now. Need to get AC stuff there for the feed into M101, 3x duplex box, cord with 20 Amp Hubbell, contactor box. Need to get the TOM cards and the VI's and the signal cabling for the VI's. Work with Jean Francois work getting pulser scope traces. Looked at two places in the CC, +1,8 and +5,8. Made a probe to plug right into the BLS cable that then runs to the scope. So none of the L1 Cal Trig Electronics is in these traces. For each side of the differential line, the probe takes the center conductor to GND with 1 Meg Ohm, the center conductor signal goes through 0.5 uFd and then 30 Ohm and then into a 50 Ohm coax to run to the scope. So you can look at either the EM or the HD and look at either both sides of the signal or else have the scope invert one side and add them to get the full differential look. We did not make the signle ended vs differential noise floor measurement. Jean Francois did look individually at all the pulser patterns that contribute to a given TT. Drew Baden loaded new fpga code into his de-mux card and now says, "I've verified it with the meter, I think it works". Got the 8 SCL serial coax cables that were installed to the platform shortly before the wall went up turned over to there users (Sequencers for SMT & CFT. This batch of 8 includes the 4 cables for Geo Sections 0:3 and 4 spare cables. These are now routed from the dumpster to the Sequencer racks and plugged in at the Hub-End. Need to let Mike Utes know that his 3rd floor test cables have been moved from GS 0,1 to 8,9. Thursday night find both Sequencers with ALL error LED's ON and it was clear that the Dynamic Buffer of the #1 Sequencer had been over written. But not all of Sequencer #1 was over written. Its LED was still on for the BX Marker signal. ReLoaded both Sequencers. Let Drew know that this had happened and what to look for (i.e. green LED by #17 cable). This sounds exactly like what happened last weekend. Hard to imagine that hardware could do this. It is not a re-boot of the slot #1 problem. Sounds more like some one playing with the software. Some one was doing a lot of playing with the HSRO Test menue to reset the VRBC. Some one who had know idea what they were doing. Tried but did not figure out who was doing this. The problem was clearly always that L3 was not taking events from our FW Readout crate. Finally got 12 SCL Status Cable circuits running up to Dean. Still need to bring one more pair SCL Status circuit boards to Fermi to get Dean the 13th circuit. This cabling uses old 40 conductor cables between 1st and 3rd MCH., plus 40 conductor cables run along the back of the FW racks to reach over to the vertical run to the 3rd floor. 3rd Floor 1st Floor Into SCL 3rd-1st SCL M124 Status MCH 1st MCH Status SCL Geographic Paddle Vertical Horizontal Paddle Hub-End Geographic Section Board Cable Cable Board Cable Section ---------- --------- -------- ---------- --------- ------- ---------- 40 A 1 1 A 1 40 42 B 1 6 1 1 B 2 42 44 A 2 2 A 3 44 45 B 2 5 2 2 B 4 45 46 A 3 3 A 5 46 47 B 4 3 3 3 B 6 47 Dean tested and all the L1 and L2 Busy signal were getting through OK. So this leaves only the last (i.e. 13th Geo Section) of his to get Status signals connected to. The Geographic Sections in Calorimeter that have "normal" SCL Status cables are: 41, 43, 48, 4A, 4B, 4C. The only thing that is connected funny right now is that cable 4C is being used to carry the Busy signals for Geo Sections 49. I need to make and take to Fermi another pair of SCL Status cards. DATE: 1,2,3,4-MAY-01 At: Fermi TOPICS: Verify L1 CAl Trig Timing, Cosmic muon trigger, Books to MSU, Move desks, tell Delmar he can junk Run I Trig FW, SCL to 2nd floor L2 Test Racks Using the now triggerable CTFE Pulser box and running with no one else on the system I checked which 3 ticks the L1 Cal Trig And-Or Terms are asserted for. As expected from last week, the 3rd tick of the 3 ticks that the And-Or Terms are asserted for is the "live accelerator crossing". This is OK but I would like the live accelerator crossing to be the middle of the 3 ticks that the And-Or Terms are asserted for. So I moved the L1 Cal Trig Sub-System Gap signal earlier by 1 tick. Now the TRM FIFO will store the L1 Cal Trig And-Or Terms for about 8.2 ticks instead of the previous 7.2 ticks. The way I explored what 3 ticks the L1 Cal Trig And-Or Terms are asserted for was to make up a trigger that is just a L1 Cal Trig AOT and a Tick Select AOT. Then by hand move the Tick Select AOT around and watch on the SCL Logic Analyzer where does the Trig FW issue L1_Acpt's. This is all while running the pulser so it makes a Trigger Pickoff signal at a known point, i.e. on a known beam crossing, and using this signal to cause the L1 Cal Trig to issue asserted AOT's. I cafefully checked the ticks on either side of the 3 ticks that the L1 Cal Trig AOT's are asserted for and they never caused a trigger, i.e. there is no problem with the L1 Cal Trig jumping around or something like that. The Belden twisted pair cable is #8442. Need a 500 ft spool. Boris and Victor would like the Cosmic Muon Trigger working again. This is And-Or Term #2. The only issue is getting the delay in the TRM Input FIFO set so that their "pipeline delay" will match running with real beam triggers. Issues are: Move from master clock setup by C program to Clock Gui Changes from move to issues current info 6 ticks early Want their front end timing to be the same as with beam trig's. Currently the And-Or Terms 0:15 are being stored for 19.1 ticks when running the Sequencer_1_5APR01 clock file. Using the C program at boot time this is 27.8 ticks. But this must realy have been 20.8 before we added 7 more stages of aging the Gap signal in the L1 TRM as part of issuing SCL Current Info 6 ticks early. Boris and Victor would like 4 ticks less front end pipeline delay than what they had back when they were using the cosmic trigger. Right now I guess that they have 20.8 - 19.1 = 1.7 ticks less. So I'm going to move the NIM Triggers Sub-System Gap signal later by 15 RF Buckets (14 for two ticks plus 1 for better alignment with the Strobe edge. I will also increase the Strobe from 1 RF bucket to 2 RF buckets. OK this is file clk_sequencer_1_2may01 and now the And-Or Terms are in the TRM FIOF for 17.1 ticks. So it is 20.8 - 17.1 = 3.7 ticks earlier than before. Does 17.1 ticks make good sense for this cosmic scintallator trigger ? Well from working with L1 CT I believe that it is about 2800 nsec from real BX center of D-Zero to Trig FW reading And-Or Terms. So 2800 nsec minus 17.1 ticks (2254 nsec) is 546 nsec. I thought that we got the NIM signal in something like 300 or 400 nsec so 546 may be a little long. Now check their NIM Input Sub-System Strobe vs their Gap. Yes, the strobe is active for 38 nsec. The active edge of strobe is about 56 nsec before a transition of Gap and the next active edge of strobe is about 75 nsec after a transition of Gap. So it looks like things are set up in a rational way. This is all with the clk_sequencer_1_2may01 file. Bring back to MSU the following books: MVME-133, MVME-135, 133 Bug, 135 Bug, MC68020 Users Manual, MVME-214, Microtec Asembler Linker Manual, VAX 4000 model 60 Owners Guide, Dilog SQ706 MSCP SCSI Disk Controller Manual, pVBA and pQBA hardware and software manuals, Ariel Hydra-II User's Manual, MVSB2400 Chip User's Manual, TMS320C40 User's Guide, C40 Parallel Debug Manager Guide, C40 Asembler Linker Manual, Our book "L1.5 Cal Trig, P2 Cards, JTag, P2 Register Summary, P2 Cabling". From the stack that the above came from, Leave at Fermi: Ironics IV-1623 Parallel I/O User's Manual, Steve Pier's "ERPB and DC Project Record". Move the desks. Tell Delmar that he can throw out the old Trigger Framework racks but that I need 1/2 hour with them to pull some cards & cables before they go into the dump. Install special GS 10=0a SCL cable to 2nd floor L2 Test Stand. DATE: 24,25,26,27,28-APR-01 At:Fermi TOPICS: First 36x36 Store on Friday Moved the L1CT MTG from BBA=MBA=152 to 208. I would like to put it at 224 because that will keep it out of the way for the longest time but BBA 224 does not appear to be working yet. Pulled a ton of cabling out of the back of Tier 3 because it was hanging loose and was in the way and would eventually need to be redone anyway. this was typically stuff like take some Tier 3 output loop it back into Tier 3 and take it to the Run I IMLRO Final L1CT Readout. Start water flow in rack M105. Look over and then power up the Tier 2 crate for eta -8:+8. Pull all the cards except the the Counter Trees. Add stuff to D0_Config\Init_Post_Auxi_L1CT.cio to setup the Tier 2 Counter Tree CAT2 Cards for eta -4:+4 to have a Count Threshold Reference of value 1 for comparator 0 and value 2 for comparator 1. There is already stuff in this file to setup the MTG which is now sitting on BBA MBA 208. Procedure to look at the signals from L0 Lum system. Use the SE01 signal on the lower patch panel. Set things up so you can see the first BX in the first Super Bunch. What you will see is an upside down "M". The first bump is the Halo and the second bigger bump is the beam signal. You want the leading edge of the second bump. At the patch panel in the bottom of M114, the leading edge of the second bump of the SE01 is 298 nsec after the real BX. Checked this with the first 36x36 store on Friday and the front panel BC_TRIG signal that I have brought out and labeled for people to use was a little bit off. It was late 15 nsec or so. This is probably due to it being setup when we had bypassed the PCC module. So before the store on Saturday I moved this signal 1 RF bucket earlier in the clk_sequencer_1_5apr01.txt file and reloaded the master sequencer #1. I did not change the date on the file as this is not one of the official signals. Measured this again carefully on Saturday afternoon. From the falling edge of the NIM D-Zero BX marker to the leading edge of the bump due to beam particles the scope read 355 nsec. This was with a 64 nsec cable between the scope and the SE01 patch panel and an 8 nsec cable between the scope and the D-Zero BX output panel in the master clock rack. So I think all is well: 298 + 64 - 8 is close to 355. Saturday afternoon look at the TRM Input FIFO stages for the various And-Or Term sources: L1 Muon typically 77 @ 2 15 @ 3 L0 LUM typically 17 stages L1 CT average of lots of looking 7.2 ticks Saturday morning, start using TRICS 9.2.H This required putting COOR commands in the Init_Post_Auxi_L1CT.mcf to setup the Count Threshlds instead of using CBus IO Writes from the Init_Post_Auxi_L1CT.cio file to setup these Count Thresholds. Need to move the mcf and cio files to MSU. In \Scratch there is a file to change the Tick Select references to something that Michael wanted for the first 36x36 store. I will leave this in the Scratch directory for a while. NO change was made to the normal Init Post Auxi FW files that TRICS uses to setup the Tick Selects. The Drip Detector for M103-M104 was going off on Thursday morning. It had been OK since this flow was started back again a few weeks ago. It looked like it was making about one drip every 5 minutes. It is near the back of the drip strip - 6 inches from the connector end. I do not know which of the 3 radiators is leaking. This is the stack between M103-M104 that is mounted on M103. I shut the water off to these radiators. After watching the first 36x36 store, the sequencer #2 ADC Clock signal has been moved earlier by 2 RF buckets. This lines up the falling edge of the ADC Clock with the peak of the Pickoff signal. This is a fine place for this signal. So it now has an offset of -15. I need to fix the Cal_Trig_Timing.txt and the .dgn files. We may need to move this again once we see signals from the other eta's. Add stuff about the check of L1CT subsys strb gap aot. The remaining big question is is the L1_Acpt in the write spot. By watching lots of L1 CT L1_Acpts I showed that we were issuing them for all the BX's in the various super bunches. Issuing them based on Dean's Cal Pulser they look OK. The pulser fired at about the right spot for the L1 Cal Trig to think it is charge from the BX in SCL Tick #19 and we see L1CT issue L1_Acpts for BX #19 but what I want to see is all 3 BX's that the And-OR term is set for - and I want to make tick 19 the middle of the 3. SCL Frame L1 Accept Tick Number of the 36x36 Accelerator Live Crossings --------------------------------------- First Second Third Super Super Super Bunch Bunch Bunch --------- --------- --------- BX dec hex dec hex dec hex ---- --- --- --- --- --- --- 1st 7 07 60 3c 113 71 2nd 10 0a 63 3f 116 74 3rd 13 0d 66 42 119 77 4th 16 10 69 45 122 7a 5th 19 13 72 48 125 7d 6th 22 16 75 4b 128 80 7th 25 19 78 4e 131 83 8th 28 1c 81 51 134 86 9th 31 1f 84 54 137 89 10th 34 22 87 57 140 8c 11th 37 25 90 5a 143 8f 12th 40 28 93 5d 146 92 DATE: 18,19,20,21-APR-01 At: Fermi TOPICS: PLL PCC, Epics, Fiber Timing to D-Zero, TRICS 9.2, L1 Cal Trig work First test of the PCC with just a Stean PLL on it. It did not work. SCL Hub was not running. Could not Configure in crates M122 TOP and MID. There may have been problems in others. It looks like what is wrong is that the duty cycle of the 53 MHz was strange, something like 35 % NIM active. It did work if we took the output of the PLL Only PCC and stretched the P_Clk with a discriminator before giving it to the Sequencer. Has this been one of the problems all along with the PCC ? Does the SCL Hub-End "latch" its input data on the wrong edge of the P-Clk. Is that why the SCL Hub-End is so sensitive to the relative phase of the 7 MHz and the 53 MHz ? The Clock Gui quit working. The read back (i.e. pattern of red and green dots) does not match the real status of the Sequencer. Can not change the status, e.g. Clock ON/OFF, Clear Errors. Fritz fixes this from home by about 22:20. It was something to do with the description of the control variables (epics I assume) that were loaded into the front end slot #1 processor in the clock crate. Error was, "The Type you have requested from the channel is unknown". I think that Xiaonan's home phone is x2048. Thursday, worked on the clock configuration file for the 2nd sequencer and then checked all the time lines and the alignment with the real BX's as predicted by the master clock and all is fine. Recall that when we start distributing these signals through long cables into the L1 Cal Trig that we will have to launch them early which is done by moving the SYNC marker to a later time. OK, on Thursday afternoon the new PCC with just Sten's PLL is working. I think it does everything we need. If TeV RF goes away it will just free run. If TeV_Sync goes away then it still gives a sync to the Sequencer from its divide by 1113 circuit. So I think that we are imune to the Tevatron doing random things. One thing I learned from this swap is about epics. Steve Chappa "hot swaps" these VME cards. This is trouble from the electronics point of view and it gives epics a fatal problem. The "readback" in epics is just a read from a pool that a pool filler process spins on at some fixed rate, e.g. once per second or once per 5 seconds. When you pull a card then the pool fill VME reads of that card do a bus time out. The epics response to this is to permanently suspend the pool filling process. Thus the view from the ClockGui is of old stale data. Marvin worked to get people interested in getting the fiber version of TeV_RF and TeV_Sync the whole way to D-Zero. Right now there are two fibers. One comes directly from the RF Building to the D-Zero service building but it does not have any signal on it. The other comes from the RF Building to CDF where there is one repeater and then it comes to D-Zero. This cable does have signals on it. This is some "phase encoded" TeV_RF and TeV_Sync all on one signal. It needs a small box to make it into ECL signals. Marvin would like the fiber run the whole way into the MCH Clock rack. The accelerator people want their fiber - ECL box in their rack. Marvin would like to use the shorter direct cable. Rick Hance will be involved in getting people to do this work. The accelerator people are Greg Vogel and Terry Hendrix. Made a test of pulling out first the TeV_Sync input from the PLL PCC and then pulling out the TeV_RF input. NOTHING happened to our stuff or to the SCL - even the receivers stayed locked. The only thing that I did not try was leaving the TeV_Sync plugged in while pulling the TeV_RF. That could bother things but we can always move to PCC free run. I did see a couple of error lights while watching for the last day and a half. I assume that Tevatron was restarting their timing generator or something. What you see is: PCC Sync Error, Sync Missing, and RF Missing along with Sequencer #1 Hold and parity error and Sequencer #2 Hold. This is clearly just a transit as it all clears right away. I never see the Sequencer #1 parity error except during the rest of this. It does not appear to cause any trouble for Trig FW or SCL. Started running TRICS 9.2.D This is the L1 Cal Trig stuff, the never repeat Lum Blk Num, and more different Lum Logging information. Running the L1CT stuff in TRICS 9.2.D TT_ADC_MON It is displaying the right range of TT's (so I think that it is following the global setup stuff. But the data looks in trouble: slice: 0,1,2,3 all RED 25, slice 4 Red 0 & 25, Blue 6, white 7 slice: 5 Red 61, slice 6 I forget, slice 7 Red 61,0,3 CBus running Init_Post_Auxi_L1CT.cio Post Write Check Abort this is the MTG stuff. It is Write not Write_Verify DAC Programming Init_Post_Auxi_L1CT.tti Pre Write Check Abort Setting up the Ref Sets looks OK. Is the value in GeV or in just 0:255 type value. What do you put into the HD Veto of the EM Ref Set to make it never veto ? In Scratch made and Init_CTFE_eta_pos_1_4_phi_1_16.cio It puts value 1 at FA 80 and value ff at FA 81 and in all Pedestal DAC's it puts value 25 decimal. Then hand readback of the 29525's looks OK. Will want something in the Tier 2 Counter Tree CAT2's by next week. It can all be from the Init Auxi. Fixed Stuff. With the current setup of the L1 CT Sub-System Strobe and Gap I see the following. Typically using 8 steps in the FIFO. Active edge of strobe is 38 nsec before a transition of Gap and 93 nsec after a transition of gap. This is running into AOIT 128:143 Watching the CHTCR output timing wrt the falling edge of Latch-Shift from the front panel LEMO Monitor output on the BBB. The CHTCR "Hint" output moves active 352 nsec after Latch-Shift falls. The CHTCR Data output moves to its correct state 380 nsec after the falling edge of Latch-Shift Exit with TRICS System Control told to totally ignore the L1 CT. DATE: 11,12,13-APR-01 At: Fermi TOPICS: Switch TCC keyboard. Install Bit3 cards d0tcc2, Measure timing for Cal & Muon, work with L1 Cal Trig, Run the 2nd Sequencer, SMT Geo Sections, VRBC hangs when Tevatron clock stops. d0tcc2.fnal.gov has IP address 131.225.231.218, and runs Windows 2000 Pro d0tcc1.fnal.gov was recently changed to 131.225.231.215, and runs WindowsNT 4.0 Switched the TCC keyboard (on the side of M102) from the Adesso keyboard with built-in TouchPad to the Cherry G84-4400 keyboard with built-in TrackBall. Try installing a 7-slot bit3 PCI expension box with 2x bit3 Model 618 in D0TCC2. Route the bit3 optical cables labelled "L2TCC000 M121 Crate 0 Global" and "L2TCC002 M200 Crate 0 CFT" that were landing near M120 to the back of the mini-rack M125 following the top edge of the back of M121>M122>M123>M124. There will eventually be 6 or 7 optical cables. These are the initial two cables that the L2 crew (i.e. Reinhard) wants to use. The bit3 PCI expension is made of the following: PCI Bridge Module: 85224036 Rev A, S/N 182523 MotherBoard in Expansion box: 85421140 Rev A, S/N 187996 The two Bit3 Model 618 are 85851090 Rev B, S/N 197674 and 197687 Tried with the PCI bridge module in the third, and later in the first PCI slot (meaning closest to CPU) of TCC2, but trying to connect to the Model 618 always fails with "error in communicating with driver", both with V3.0.B bit3 Model 983 Windows NT support software (targeted to Windows 2000) and the V2.4 software. Note that different executables need to be linked for V3 and V2 drivers. Tried with the two 618 directly in the TCC2 enclosure, and no PCI expansion, and the error messages now only complain about "remote power off", which is true. The V3.0.B bit3 software does not work properly, as it prevents W2K from starting up if the remote crate are powered off. We are thus using V2.4. We ran out of time and didn't try doing VME cycles. Philippe took the PCI expansion box back to MSU for testing. [Note: Reinhard tried using the system on 16-April and we continue getting the same "power off" errors after the crates have been powered up. Reinhard plugged one of the optical cables in his test PC in M120, and it worked. We thus believe we still have some software problem. To be investigated.] Recover from last weekends master clock fiasco: The cabling to bring Sync and 53 MHz from the PCC monitor output to the Sequencer has been pulled apart so I will have to find and time new cables to make this work again. Wedneesday morning they were running in PCC Normal mode with the real PCC outputs driving the Sequencer at 150 GeV and having trouble with Sequencer holds about once per minute. Put the PCC into FreeRun mode and things were OK. Some of the VRBC's on the 2nd floor were not telling there SCL Receivers to Re-Sync when the SCL was glitching when the Sequencer was doing its Holds. By Thursday everything was restores and we were running from the PCC monitor outputs. A couple of time the accelerator did something to stop the Tevatron timing generator. The problem with this is it put the Trig FW VRBC into a state that could not be recovered from by doing a VRBC Init. We had to power cycle the VIPA readout crate to get things working again. Daniel knows about this and we have a vio file to display all the VRB and VRBC status registers in the scratch directory. Had a note from Harold Fox that they never saw L1_Busy for Geo Sec $62. Plugged in the Status cable for Geo Sec $62. Now all Status Cables $60: $67 are plugged in. This is all SMT Geo Sections. Got the 2nd Sequencer running and found the problem in the ClockGui that required a readback before a download. The ClockGui is now fixed but we are running a private version until it is released. Sent out instructions for this weeks version of clock loading. Worked with Dean and Leslie on measuring timing of Cal Pulser. Worked with muon on how the timing is currently setup wrt real bx. We got enough timing into the L1 Cal Trig to run the ADC and the Latch shift. By hand we did a move old pedestal DAC and saw it in the readback. The cables between 2nd Sequencer and timing distribution are 10" longer than the model left at Fermi. The good AMP 34 pin housing that the pins fit nicely into are AMP # 2-87832-9. Need to bring to Fermi: Cable Ties, small Panduit labels ------------------------------------------------------------------------------- DATE: 3,4,5,6-APR-01 At: Fermi TOPICS: First STores, Master Clock, Move to sending out Current SCL Info 6 Ticks Early, Connect L0 Lum signals to Foreign Scalers, Look at L1 CT Pick Off signals. The Sub-System Strobe and the Sub-System Gap signals from L0_Lum were upside down. In addition we moved the Framework early by 32 RF buckets. The min bias Level 0 triggers are now issued for BX number 7,8,9. The leading edge of the Fast-Z signal from L0 Lum leaves their module about 450 nsec after the BX in center of D-Zero. That plus the 48 nsec of cable that we were using to get a scope pattern over by the Trig FW made the leading edge of the signal 500 nsec after the BX. Looking at Prob #1 signal #6 (i.e. the 8th odd pin) from the SCL test receiver that was running through 44ft i.e. about 60 nsec of cable. That put the SCL signal about 200 nsec behind when the Trig FW issued the L1 Accept. So 27 ticks is 3.559 usec. But we see the BX 500 nsec after it happens and the L1_Acpt 200 nsec after it is issued by the L1 FW. So you would expect a spread of 3.259 usec of all was setup OK for 27 ticks between BX and L1 Accept. After moving the FW forward by 32 RF bucket we measure 3.200 to 3.250 usec. There is beam in a bunch of BX's so we are getting Fast-Z triggers on 7,8,9. I'm not really sure that I understand why this should happen. The jitter in the PCC is worse at 980 GeV and the G-Links are not staying locked. It is bad. Tapping the front of the PCC made things better. The VRB's in slots 16 and 17 loose sync most often - but you also see slots 10, 11, and 13 loose sync. Recall the current setup (i.e. pre 4-APR-01) of the Init_Post_Auxi Tick Select #0 AOT #251 M123B Slot 21 Chip 16 Reg 40 Write 21 Sel BX #24 Tick Select #3 AOT #254 M123B Slot 21 Chip 16 Reg 43 Write 22 Sel BX #25 Reading the Registers, the other two Tick Selects are not being setup right now Turn On SCL clock via VME I/O Write a 2 to address #1880 0004 Modify some of the Initilaize Trig FW control files Made a \rio\tts_select_tick_for_aoit_252.rii to setup Tick_Select #1 for BX #7 Made a \rio\tts_select_tick_for_aoit_253.rii to setup Tick_Select #2 for BX #10 for SMT. Edited \D0_Config\Init_Post_Auxi_L1FW.rio to now include the two files listed just above as well as the existing calls to the rii files for Tick Selects #0 & #3. Move to issuing the Current BX SCL information 6 ticks early: Edit \DCF\scl_helper.dci from 4_1 to 6_1 \DCF\tts.dci from 12_1 to 14_1 \DCF\l1_trm.dci from 3_1 to 5_1 How much faster is a full turn at 980 GeV than at 150 GeV ?? 150 GeV 53.10370 MHz = 18.83108 nsec revolution period = 20,958.99 nse 980 GeV 53.104709 MHz = 18.83072 nsec revolution period = 20,958.59 nsec revolution frequency = 47.713126 KHz Running with Current BX information going out "6 early" we have the following on the scope. BOT at +-+ CMC Frnt | | Panel ---+ +--------------------------------------------------------- Min-Bias +----+ AOIT | | -----------------------+ +---------------------------------- L1_Acpt +-+ SCL Rec | | Output --------------------------------------------------+ +---------- Everything is shown positive active (although some stuff is NIM and some is TTL). The BOT is just the BOT signal at the Carmen Master Clock Selector Front Panel. It is 132 wide. The min-bias AOIT is coming on 48 nsec of cable from the L0 Lum Fast-Z module. My understanding is that the output of the Fast-Z module starts right at 450 nsec after the BX takes place. The L1_Acpt is the output of an SCL Receiver through 56 nsec of cable. Call it 200 nsec after the L1_Acpt is issued by the Trig FW. Note that we are issuing the L1_Acpt for BX #7 i.e. P1 x A13. All times are leading edge to leading edge. min-bias AOIT to L1_Acpt is 3.08 usec BOT to min-bias AOIT is 2.86 usec BOT to L1_Acpt is 5.98 usec So I think that the L1_Acpt is issued by the Trig FW 3.38 usec after the BX in the center of D-Zero, i.e. 25.6 ticks after the BX. Meeting with Boris, Daniel, Bob DeMaat (from CDF) and Steve Chappa about the PCC. CDF uses raw master clock 53 MHz to run their silicon system and they are having the same problem that we are. A basicaly PLL only PCC is going to be designed and we will have another meeting to review it. During the meeting on Wednesday it grew lots of bells and wistles (VME controlled delay lines, error detectors, ). Wednesday late afternoon Steve brought over another PCC. It was worse, i.e. the SCL would not lock on with it at all. With it about 1/3 of the G-Links were flashing most of the time. In switching back and forth between this new one and the PCC that we have used for the past couple of months it is clear that they go through a "warm up". When the PCC that we have been using for the past couple of months was first plugged in the G-Links would have lots of trouble and after 5 minutes most of the trouble would go away and you only saw one or two G-Links re-syncing every 30 seconds or so. This leads me to believe that some adjustment of this PCC could be enough to make it work. It was clear that the PCC is quite microphonic. Small taps make the 53 MHz at the end of the 1113 move around by half a pulse width (9 nsec) or so. This would ring with a typical mechanical frequency. This is easy to imagine with the loose LC floating on this card. We ended up running with out the PCC for the second store. I had tried ths a couple of months ago and it did not work at all. Now it appears to be the best choice. Steve's LeCroy scope has a very nice thing that lets you look at a repetative waveform and it must do something like calculate the average period and then compare the period of each cycle to it and plot the difference. Or else its the difference in arrival time of the edge or something like that. Anyway, the raw 53 MHz right out of the Cable TV was clearly the best choice both from the viewpoint of this scope display and from the viewpoint of the SCL and G-Links. So far it looks OK at both 150 GeV and 980 GeV. Friday, this has continued to work well, i.e. no PCC. The store Thursday afternoon and Thursday night was done without the PCC. It looks fine so far. Current connection of Level 0 Luminosity to the Trig FW. The L0 Lum stuff is plugged into the block of And-Or Terms 208:223 And-Or Term Function ----------- ----------------- 208 not connected 209 not connected 210 not connected 211 not connected 212 Z(0) 213 Z(1) 214 Z(2) 215 Z(3) 216 Z(4) 217 Good Fast Z i.e. the min-bias trigger 218 not connected 219 not connected 220 not connected 221 not connected 222 P Bar Halo 223 Proton Halo Foreign Scaler #0 is Good Fast Z Foreign Scaler #1 is P Bar Halo Foreign Scaler #2 is Proton Halo Foreign Scaler #3 is Sync Gap Foreign Scaler #4:#9 are not connected. The Per Bunch Foreign Scaling of the Sync Gap returned from L0 Lum Land looked fine but a couple of their signals looked like they might be spread across the edge of two scaler ticks. Rich said the the boundaries (edges) of all their data and the Sync Gap were within 5 nsec of each other. Thus it is OK just to delay (or speed up) the whole set of signals from them. So make and "extender" cable from them. It is 24 ft long which should make it 36 nsec or so long. Inserting this cable caused the Tick Scalers being occupied by the Sync Gap signal to move from 4 through 20 to 5 through 21. So I think that it must have just barelly not falling off the end of 4. If so then what you would really like to do is to remove 20 nsec, not add 36 nsec, i.e. lots of setup time. Wednesday night, now that we are running with the current BX information going out 6 ticks early, the L1 Muon people were able to send on their And-Or Input Term cable Install a NIM signal on a small panel just below the Master Clock crate on the right hand side just above the RMI box. This is an 18 nsec pulse that happens at the same time as the real BX happens in the center of D-Zero. The leading edge of this pulse comes out of this connector within 5 nsec (or better) of the actual BX taking place in the detector. Verified this with Rich and had fun looking at the PMT signals. Labeled this connector and informed people. Connect this "Real BX time" signal to the Logic Analyzer along with the Master Clock BOT signal and make a file called REAL_BX_.DAT This is in timing analysis mode and triggers on BOT. It watched the normal test SCL Receiver with it 44 ft cable and puts "Real BX Time" onto the SCL Receiver Output stream. It says that the real BX (for P1 on A13 i.e. the BX that we say happens during Current BX #7) happened in the center of D-Zero when the output of your SCL Receiver said the Current BX number is $0d = 13. The SCL Receiver says it is Cur BX $0d for about 20 nsec when the real BX happens in canter of D-Zero. This sounds funny but it is the requested setup, "SCL Current BX information is 6 ticks early". I have checked all of this. On the Logic Analyzer trace the Real BX Time trace is labeled CMC_D0_BX. Also checked, The leading edge of the BOT signal from the master clock is about 2.375 usec ahead of the Real BX Time of the P1-A13 BX#7 crossing marker. Also made a Logic Analyzer trace of the normal test SCL Receiver signals but watched the sequence at the end of SCL Initialize. This is in file SCL_INIT.DAT Showed all this to Boris and Vladimar. Thursday night store, Look at L1 Cal Trig pick off signals. Watch and triggered on the pick off signal from L1 Cal Trigger Tower Index Eta +1, Phi 8 EM and also watched on the scope the signal that shows the time of the Real BX in the Center of D-Zero. Running single sweep and assuming the 2V is about 64 GeV I saw the following hits. Real BX Real BX Peak to Initial to Peak Height Rise of the Bump ------ ---------- ----------- 17 GeV 456 nsec 624 nsec 7 480 640 44 480 672 12 504 704 19 496 664 7 488 632 16 496 672 27 472 640 10 496 672 average 485 nsec 658 nsec difference = 173 nsec There were a similar number of scope single sweep triggers that were not related with a particular BX. Need to backup TCC files to MSU and Clean up TCC files. This is getting very bad. Philippe did the backup: - MSUL1A is up to date with respect to D0TCC1 - Took another archival snapshot of D0TCC1 "Run Files" (i.e all but "Log files", and "Executables", which are also archived, but separately). DATE: 29,30,31-MAR-01 At: Fermi TOPICS: PCC module replacement, FPGA's for a spread of 33, work with SMT and CFT, work with master clock setup. Talk with Boris about my concers about the Master Clock PCC module and he talks with people over at the high rise. Evidently they are planning to do something about a new PCC. He is setting up a meeting. This includes Bob DeMaat who works with Steve Chappa. Moving to a spread of 33 ticks between SCL Current BX Information and the L1 Decision BX. Change L1_TRM, TTS, and SCL_Helper FPGA's. Bring the following parts from desmo to d0tcc1. L1_TRM has been running 3.1 bring down 5.1 TTS has been running 12.1 bring down 14.1 SCL_Helper has been running 4.1 bring down 6.1 (m3.1 Tied) and 6.2 (m3.1 NOT Tied) Initial new FPGA's moved only to a spread of 32. These appeared to work OK. The Ver/Rev listed above are for the set that should make a spread of 33. We are still running the old stuff - nothing new installed yet. Big time consuming problem with the License Server setup for Mentor and Xilinx. See the notes in the Desmo logbook. So far I can not run Mentor and Xilinx m1.4 on the same machine. Worked with the ClockGui for this week and sent out new instructions for using it to load the master clock. Installed the 2nd Sequencer - its output is disabled and it is not currently being loaded. Cleaned up the directory setup for the master clock. SMT people want a Tick Select for bx=7 (I think). Work with CFT people to help find the LED signal. Make some measurments: start of bot at cmc to tl#17 at cmc is 3.1 usec tl#17 at cmc to L1_Acp out of SCL Receiver with 44 ft ?? cable is 4.4 usec CFT LED Pulse in platform to L1_Acp out of SCL Receiver in platform 4.1 usec This is a L1_acpt issued on Current BX = $33 for BX = $19. Does this all hang together ? DATE: 23-26-MAR-01 At: MSU TOPICS: DataLogger gets in trouble because the Lum Block Number jumps around. It seems like the readout of the LBN sometimes fails and this causes problems to the data logger which is trying to keep the events with the same LBN number in the same file. The first incident was reported for March 23rd where the LBN had a correct ffff upper word and a corrupted, much too small, lower word, but for only one event, as far as we were told. More frequent incidents occured on the 24-26th where it seems the upper word of the LBN was a repeat of the lower word instead of the ffff currently written. Note that the Shed TRM reads out its low word first. Maarten also reported that "They seem to occur one at a time, surrounded by good events, but all within a timespan of a few hours at most." Scott dumped the content of that VRB for a good and a bad event and Philippe examined the rest of the payload. No other problems are detectable. It is our understanding that the LBN is the only word out of the whole L1FW raw data that is sensitive to this kind of problem at the moment. Other events may have some other word(s) messed up and we wouldn't know it because no one looks at them. Unfortunately, they haven't been watching and testing for this kind of problem until last week. Maarten: "It is only since we switched to the V2 DAQ that we became susceptible to LBN errors: in the V1 DAQ the LBN was completely ignored (the event catalogs contain dummy values for testing the database; one could get the true values from the raw data files)." We strongly suspect and hope that this is caused by the D0 Master Clock not delivering a pure 53 MHz clock during accelerator studies. When the Master clock issue is resolved, these readout problems will hopefully disappear. ------------------------------------------------------------------------------- DATE: 21,22,23-MAR-01 At: Fermi TOPICS: Install D0TCC2 and new flat panel display, move to using the ClockGui with the new Time Line and Selector Fanout setup, Move from the C: drive to the D: drive for holding the executable, the logfiles and all the run support files for TRICS, VNC is now a service on D0TCC1. Repaired the GS end of SCL Status Cable for GS = 35. It was crimped on wrong - off by one wire. The ClockGui for loading the master clock is working well enough that we have moved to using it. The clock configuration file that we are running is the 23-MAR-01 version of clk_sequencer_1_14mar01.txt This is in /online/config/trg/samples/. This clock configuration file: gets rid of the the Run I Cal clock lines, moves the CFT LED Pulser Trigger Time Line from TL13 to the 6 dynamic TL's TL22:TL17, it adds 3 TL's for the L0 Luminosity system TL12, TL13, TL14, and it moves the Sub-System Strobe and Gap signals for the NIM Trigger inputs from strobe on TL14 to TL9 and gap on TL15 to TL10. This new setup should be easier to maintain. The current Time Line setup on Sequencer #1 is: Time Line Function Used By --------- ------------------------ ----------------------- TL0 FW Tick Clock Framework TL1 TRM Tick Clock Framework TL2 Beginning of Turn Marker FW & AO Net Input & SCL TL3 Interaction Marker AO Net Input & SCL TL4 Cosmic Gap Marker AO Net Input & SCL TL5 Sync Gap Marker FW & AO Net Input & SCL TL6 Spare Marker AO Net Input & SCL TL7 Helper Function Tick Clock Framework TL8 SCL Tick Clock SCL TL9 Subsystem Strobe "NIM" Trigger Input TL10 Subsystem Gap "NIM" Trigger Input TL11 TL12 L0_LUM_Live_BX_Clock L0_LUM TL13 L0_LUM_Tick_Clock L0_LUM TL14 L0_LUM_Gap_Signal L0_LUM TL15 TL16 TL17 CFT_LED_1 CFT_LED_Pulser_1 TL18 CFT_LED_2 CFT_LED_Pulser_2 TL19 CFT_LED_3 CFT_LED_Pulser_3 TL20 CFT_LED_4 CFT_LED_Pulser_4 TL21 CFT_LED_5 CFT_LED_Pulser_5 TL22 CFT_LED_6 CFT_LED_Pulser_6 To fit with these TL changes we had to change some of the Selector Fanouts. This is mainly in the first 3 Selector Fanouts on the left hand side and the Selector Fanout labeled SC124 that handles the Sub-System strobe and gap signals for the NIM Trigger Inputs. So the new setup is: SLF Ch CFT CFT L0 L2 SC SC SC FW FW FW FW Num LED LED LUM Help SCL 124 10A 10B 123 123 122 122 --- --- --- ---- ---- --- --- --- --- --- --- --- --- 0 19 15 11 2 0I 9 7 4 7I 3I 7I 3I 1 20 16 12 7 0I 10 2 5 6I 2 6I 2 2 21 17 13 3 0I 10 3 6 5 1 5 1 3 22 18 14 0 8 8 8 7 4I 0 4I 0 53 MHz I I I I I I --> Inhibit 8 SCL Receivers to Daniel Mendoza. Gave ALL our spare MCX connectors to Neal. We had 8 of them left. He was also looking for his crimp tool but found that his student had it. Gave a status report for Master Clock, Trig FW and L1 Cal Trig at the 12:30 Friday meeting. The content of the Short Rack on top of the air conditioner has been rearranged: TCC's old monitor, keyboard and mouse have been removed. (the keyboard+mouse are in the spare card rack; the monitor is currently in the corner between the sink and our tool cabinet). The Level 1 TCC (d0tcc1) has been moved up by ~2 inches which leaves a ~4.5 inch gap to the ceiling of the rack and ~2 inch clearance to the top of the rack's front opening. The new Level 2 TCC (d0tcc2) is right under with a 1.5 inch air gap between the two PC boxes. The logic analyzer has been moved to the bottom of the rack with a (not easy to reach) 5 inch gap left above the top of the air conditionner. There are currently about 13 inches left of open space between the logic analyzer and TCC2. Some of the space betweem TCC2 and the Logic Analyzer will be used for the bit3 PCI expansion box connected to TCC2 which has ears for mounting on a 19 inch rack. The PCI expansion box has not been installed at the moment (the L2 guys -e.g. Reinhard- have two PCI expansion boxes) Coming out of the back of TCC1 and TCC2 there are now two "CCP40" 4 meter Raritan cables that take the Keyboard, Mouse, Monitor signal to a 4-port Raritan Compuswitch KVM switch (KVM=Keyboard-Video-Mouse, I think) located on top the cable tray of M101 and held down with velcro. The inputs (from the PCs) to the KVM switch have a DB25 connector with all the K+V+M signals. The outputs (to the K+V+M) of the KVM switch have regular PS2 keyboard, PS2 mouse and HD15 monitor connectors. The new flat panel monitor is a NEC LCD 1525X. We use its Analog Input mode, but it still takes a special cable that goes from the HD15 to a special fancy connector on the monitor. There is also a little power converter pack located on top of M101 and stealing power from the power switch in the top of M100 to provide DC power to the monitor mounted to the front panel of M102. The power pack is velcroed to the back side of the cable tray. The monitor uses an ergotron wall mount fixture which attaches to the 75mmm VESA mounting holes on the back of the LCD monitor. There is a lever (quite hard to reach by squeezing your fingers under and behind the monitor) that must be swung to the left (the lever bar is then horizontal) to lock the monitor in place and swung to the right (the lever is then vertical) to unlock the mounting plate and be able to swing the bottom of the monitor out and the whole thing out of the stationary part of the mounting fixture. To reach the lever and unlock the monitor one has to squeeze his hand behind the monitor halfway up its left side. There is about 12 inch of rack panel space left unused above the top of the monitor. The L1CT Start/Stop switch box has been moved downward to the lower panel of M102, below the monitor and keyboard. The \Trics Directory containing the executable, the logfiles and all the run support files (dcf, exo, etc) has been moved from the C: Drive to the D: Drive. Trics itself did not need to be changed, but all the shortcuts pointing to the executables (Trics, Trigmon, etc) have been updated, including the autostart feature. The \Projects directory has also been moved to D:. The old \Trics and \Projects directories were left on the C: drive (for now) but renamed to \Trics_obsolete and \Project_Obsolete. The version of Trics that starts automatically is now V9.1 Rev I. VNC has been installed as an NT service, meaning that it is available all the time (not just when trigger is logged in or one explicitely starts the server). One can now use VNC to log on and log off as a different user, or even reboot remotely. VNC has been restricted to only answering to the following nodes tadpole.pa.msu.edu desmo.pa.msu.edu msul1a.pa.msu.edu fnal.gov This is done by adding the registry Value HKEY_LOCAL_MACHINE|SOFTWARE|ORL|WinVNC3|AuthHosts= -:+35.8.50.175:+35.8.48.25:+35.8.50.40:+131.225 [Note: Philippe got info from Stu to further restrict the fnal addresses] To prevent TCC to automatically start Trics when the account trigger logs on, one needs to hold the key down while the trigger accounts logs on. To prevent TCC to automatically logon the trigger account when TCC boots up (or also when you try to "close all programs and logon as a different user") one also needs to hold down the key during the end of the boot process. DATE: 14:17-MAR-01 At: Fermi TOPICS: More CTFE's from SiDet, Change rework instructions, Master Clock tests (Gui, wrt Tevatron, Freq Lock), Look at Muon L1 AOOIT's Spec Trig #4 wrt L3 Disable. Got back more CTFE cards from Jill at SiDet. Checked in the eta +01 cards. SN 117 +01,01 Resolder 1 X-Clk jumper SN 166 +01,02 OK SN 42 +01,03 OK SN 149 +01,04 OK SN 127 +01,05 OK SN 108 +01,06 OK SN 82 +01,07 OK SN 48 +01,08 OK, We did it. SN 165 +01,09 OK SN 155 +01,10 OK SN 39 +01,11 OK SN 169 +01,12 OK SN 123 +01,13 1x extra Cap soldered on SN 96 +01,14 OK SN 138 +01,15 1x Cap not soldered SN 106 +01,16 OK SN 153 +01,17 OK SN 145 +01,18 OK SN 54 +01,19 OK SN 27 +01,20 OK SN 160 +01,21 1x Cap not soldered SN 99 +01,22 OK SN 164 +01,23 OK SN 170 +01,24 OK SN 78 +01,25 OK SN 90 +01,26 OK SN 113 +01,27 OK SN 98 +01,28 OK SN 137 +01,29 OK SN 135 +01,30 OK SN 67 +01,31 2x grounders not soldered at one end SN 120 +01,32 OK SN 119 -01,28 OK We will store at SiDet all the eta > +1 and < -1 cards until we are ready for the 2nd half of the Run II ECO. Give Jill a paper copy of changes to the instructions (explain eta,phi label and keeping sorted in eta piles, pull don't cut lead save OpAmps, pull 7404 and jumper and dump, blob solder x-clk is OK, no need for rosin flux remover). I took 20 of the 18x18x18 boxes to her for card storage. So both the eta +1 and -1 racks are now re-stacked with cards that have the first part of the Run II ECO. Not yet shorts tested, verified pushed all the way in, or powered up. Got 30 SCL Receivers from Ted. All zero Clk to Data delay. 1 to Dean. Many tests of ClockGui. We can only use the Up For syntax and not the Up To syntax. Down loading Dynamic lines is OK but not Static lines. First look at where we are in aligning the Master Clock to the TeV. The leading edge of BOT is 12.48 usec before the P1 Bunch. It should be 6 time 132 nsec before the P1 Bunch and according to Boris we should send it out 732 nsec early and he would really like it 800 to 850 nsec early. This is basically 6 ticks earlier. Made a test of the PCC in Freq Lock mode and bringing TeV Sync around the PCC and into the Seq. It more or less worked OK - the PCC output looks more stable when you do not kick it 47k times a second. The issue is, "Is the phase of the PCC RF output in a fixed relationship with the TeV RF input phase when the PCC is in Freq Lock Mode ?". From watchin we think not and this could be due to either the funny divide by 100 counter in the 2nd PLL or is certainly a function of the divide by 2 counter at the ouput to go from 106 to 53 MHz. But this may still be an interesting way to run for early on: it would be withing +- 4 nsec of the right time and it may make a pure enough 53 MHz during ramping that the G-Links will stay locked. TeV RF Frequencies 150 GeV 53.10370 210 GeV 53.10440 980 GeV 53.104709 MHz = 18.83072 nsec revolution frequency = 47.713126 KHz Hand read the AOIT TRM for some L1 Muon Terms. Recall the loop to clean out the latched errors and then re-enable error checking in a L1 TRM FIFO is at Reg 8 write $0200 (clean errors and enable no error checking) then write $000F (enable all types of error checking). L1 Muon AOIT's were late getting to the L1 TRM and its Error Register (Reg 9) read $0104. Comparing the returning Muon L1 AOIT Gap signal to the Gap signal from the TOM front panel monitor we see that the Muon L1 signal is 3.94 usec after the TOM signal. But I think the TRM delays the TOM signal by 25 x 132 nsec plus 2 x 18.8 nsec = 3.333 usec before it uses it to check the arrival of the AOIT signal. Thus the L1 Muon signal is only 607 nsec "late". But, we still need to send stuff out early enough to that it gets to the Front Ends by the time the activity actually happens. Boris estimates this to be a delay of 732 nsec for Muon and would like it set in the 800 to 850 nsec range earlier. 850 nsec is 6 1/2 ticks this plus the current spread (current to L1 Decision) of 27 ticks is 33 1/2 ticks. Dug into the problem with Spec Trig #4 not obeying L3 Disable and found an open in the Rear_PB that takes the L3 Disables to the receiving TRM for the the Indiv Disable for 0 63:0. The open was in the same place that a couple of other Rear_PB's have had an open, i.e. from the resistor pack to the 160 pin connector. The trace from the 34 pin connector to the resistor pack and to the via by it are OK so it is a simple clean fix. Where are the Bodies, i.e. what all FPGA's have the knowledge of 25 ticks stored inside their logic. L1 TRM, Tick and Turn Scalers, SCL Helper Commissioning Meeting about "timing in". 7,8,9-MAR-2001 At: Fermi Topics: Work on Trig FW Readout, Master Clock, Start CTFE Chcek in from SiDet, L3 Disable for Spec Trig #4, Return VRB's On Moday of this week, the 5th, the master clock quit working in TeV Sync Mode. This was caused by either: cable tv people working in the accelerator rack, people moving around the lemo cables that provide the master clock timing signals, or the accelerator actually doing ramp studies (if this does in fact kill the PCC). All of these happened. Aside from the issue of Master Clock going bad and killing the SCL and the G-Links we also experienced lots of readout hangs in the Trig FW VIPA Readout crate. Work on the 7th pointed to the problem being slot 8 of that crate (not the VRB or the VTM or the source of optical signals going into slot 8, but rather slot 8 itself). The VRB and VTM and data going into slot 8 were all moved to slot 19 and the VBD read order set to keep the VBD's output in the same order, i.e. read slot 19 first and then slots 9, 10, ... The backplane is labeled "VRB New", Rev C. 5/99. Up date summary_of_fw_data_readout.txt and hsro_notes.txt with the detals of the readout setup using slot 19. After a couple of days of trouple free running, we are now convinced that getting out of slot 8 has fixed all our problems with VRB FIFO overrun and with VRB Readout Busy errors (i.e. the event is still comming in errors). The basic theory of the problem is that the VRB in slot 8 is sometimes not receiving the message from the VRBC telling it that there is a new event and telling it what buffer to store it in. There still maybe some issue with control of moving events out of the VRB's over VME and into the VBD. This shows up as ALL VRB's showing Scan Busy. We do not have this problem at all in VRBC single buffer mode so we are running that way. The point for now is to prove that all the FIFO overrun Readout Busy type errors are gone for ever. I did warn Marvin about had to debug backplanes. A number of temporary .vio files were made during the debugging of this problem in the Scratch directory. We should keep the slot 19 version of Read VRB Reg $38 and Read VTM Optical Power and move all the rest of the stuff to scratch/obsolete. Daniel made some test of readout speed with the VBD Diagnostic cable pulled off so that the VBD would always be free to send data out its Data Calbe Port. Using 100% L2_Acpt we could run the L1 Acpt rate at 7,056 Hz and the VBD could keep up. This was a pre-scale of just 1075 and the L1 Bz was 5.31% coming just from being buzy during sending data into the VRB's. The VBD did not start to use its second buffer until above 5 kHz. It would run smoothly at 7 kHz. Pausing it and looking at the data and it looked OK. Thursday, most of the time readout from the Trig FW was just fine. For about one period of 1/2 hour we had 10 or so hangs. All of these hangs showed all 9 VRB's stuck in Scan Busy. We were running about 20 Hz and the VBD's 2nd buffer was in use some of the time. What you would clearly see is: both the VRBC, VRB's, and VBD would be flashing along just fine, then the VBD would quit flashing, and shortly later the VRBC and VRB's would quit flashing and the VRBC would put on its red LED and it would be L1 Busy. It's like an event got stuck between the VRB's and the VBD and then the VRB's buffers filled up and it went L1 Busy. Running the VRBC in single buffer mode (i.e. waiting for VBD Finished before dropping L1_Bz) make this problem go away. For now will will run this way and only try other VRBC configurations when some one is here to watch it run. The master clock has been in freerun since Monday/Tuesday sometime. Some of its lemo cables have been played with. I put it back together, and verified that it's reference signals were lined up OK and we switched it to Normal Mode. All now ran fine with it. Once today, at about the time they did the first injection, it lost sync. I believe that they PCC put on its "RF Missing" and "RF Lock (Loss)" LED's and the Sequencer "Hold" Led was on. Aside from that it ran fine. No idea yet about what it will normally do during injection and ramp. Watched master clock during ramp. It looked OK but a couple of the G-Links in the Trig FW were needing to resync themselves perhaps once every 10 seconds. The SCL fiber channel links appeared to stay up OK. Returned the following non blue tag eco VRB's from the Trig FW readout to Mark Bowden SN# 300, 346, 367, 423, 424, 425, 426, 427, 437. Returned the following non blue tag eco VRB's to Mark SN# 326, 596. Returned the following blue tag VRB that people claim hangs the VME Bus to Mark SN 411. Returned a DRV11-J to Kevin Aicher in Prep. That ends Loan Agreement. Visited Ted Zmuda: returned preproduction SN# 15 VRB, talked about not having time now to finish SCL clean up work, got a tube of 26 pin connectors that go on the SCL Receiver PCB card. He has more. The PCB mount connector from the SCL Receiver is a P50E-026P-1-SR1-TG. We are using a P25E-026-S-TG on the cable. Sean is right. Something is wrong and we do not get the L3 Disable signal for Spec Trig #4. Need to check next week. Made a one hour test of the Clock Gui with Daniel, Michael, and Xiaonan Li. To start the gui: setup d0online, cd /online/config/trg/, ClockGui.py &. Meet again next Wednesday. I must have a config file ready, (add Ref lines, have all 23 TL, move CFT LED to top, pull out CAL, add Lum (132, BOT, Gap). Xiaonan will add base address of 2nd Sequencer. All of this is d0l1 Level1. We checked in the following CTFE Cards that we got back from SiDet. The idea is to go ahead and stack the cards in the racks for eta +1:+4 and -1:-4. We are setting this CC eta range cards to have an ADC Clock delay of 50 nsec by closing switches 2 and 5, all other switches are open. We will just store the other eta cards in their racks but not install them. SN 73 +05,24 OK SN 116 +05,23 no x-clk jumpers SN 122 +05,22 OK SN 86 +05,21 OK SN 103 +05,20 OK SN 53 +05,19 1x not soldered grounder, no x-clk jumpers SN 30 +05,18 OK SN 64 +05,17 resolder cap, bridge x-clk SN 114 +05,16 OK SN 161 +05,15 OK SN 44 +05,14 OK SN 95 +05,13 OK SN 97 +05,12 scraps of solder wick on the card SN 75 +05,11 OK SN 118 +05,10 OK SN 154 +05,09 resolder grounders, clip opamp pins SN 61 +05,08 resolder grounders SN 105 +05,07 OK SN 147 +05,06 OK SN 131 +05,05 OK SN 24 +05,04 OK SN 158 +05,03 OK SN 72 +05,02 OK SN 38 +05,01 OK SN 47 -01,32 OK SN 109 -01,31 OK SN 19 -01,30 OK SN 32 -01,29 OK SN ??? -01,28 ????? SN 130 -01,27 OK SN 81 -01,26 OK SN 43 -01,25 resolder some grounders SN 93 -01,24 OK SN 58 -01,23 OK SN 56 -01,22 OK SN 71 -01,21 resolder 4x grounders SN 29 -01,20 OK SN 88 -01,19 resolder grounders and x-clk bridge SN 87 -01,18 OK SN 36 -01,17 OK only 180 Ohms Vcc to Gnd SN 132 -01,16 missing grounder SN 31 -01,15 OK SN 26 -01,14 OK SN 25 -01,13 OK SN 33 -01,12 OK SN 34 -01,11 unsoldered cap SN 156 -01,10 OK SN 55 -01,09 OK SN 125 -01,08 OK SN 66 -01,07 OK SN 70 -01,06 OK SN 101 -01,05 OK SN 126 -01,04 resolder 1 grounder SN 152 -01,03 resolder 2x FADC caps SN 111 -01,02 resolder 3x grounders SN 151 -01,01 OK Re-stack all of -1:-4 except that the -1,28 CTFE Card must still be at SiDet. I forgot how long this takes. We need to find a way to store cards outside of the L1CT Racks. Bring to Fermi: Panduit Labels, Amp 8 pin connector part number to France, clip for Gnd Strap, Crimp Tool and wire and AMP Contacts, cable ties. 1,2,3-MAR-2001 At: Fermi Topics: VTM Optic Power, Status Cables from Dean Have made the "Read VTM Optical Power" and the "Read VRB Reg 38" .vio files in Scratch. Lots of various tests with Trig FW readout. Replaced the 9 VRB's in the Trig FW readout with new Blue Tag VRB's Dean has found 3 of the old Run I 40 conductor cables near his equipment that we can use for the Status Cables from his SCL Receivers for which we did not have real 25 mil cables. We need 7 of these so let's fit 3 Status Cable signals onto each 40 conductor and that will leave us 2 "spare". We need about 5 ft on his end. Geo Section end of the Status Cables have a Robinson-Nugent connector part number P25E-026S-TG The Hub end of the cables have T&B 311-026302 connector. Status Cable 4C repaired at the G.S. end. The connector was put on very obviously wrong. Returned to Sean the VBD that we have had a MSU for about 3 years that Dave Cutts sent to us when there were questions about getting a VBD into a VIPA backplane and that we used at the time of initial testing of VRB readout at MSU. DATE: 15:17-FEB-2001 At: Fermi Topics: Master Clock Gui, Test readig the optical power level, Test of VRBC, 2nd SCL cable up to Mike Utes in 3rd floor electronics area, Talk with Bob Kehoe about program to look at L1 Cal Trig data from Pulser Runs. Master Clock work, Visit SiDet for CTFE rework. A second test of the Master Clock Gui. There were some problems managing the various control registers. Sequencer Halted kept getting stuck ON. Xiaonan Li is going to work on the software some more and we test again next week. Talked with Stu about it and this is just supposed to be the program that you use to manually work with the clock. There will be something separate to load the current default configuration at power up and to make any necessary changes between in store and not in store. Work with the VTM Optical Power stuff. If you do not give any delay between issuing the commands to the VTM Control Register it clearly trashes the data that ends up in the VTM Power registers. It typically makes lots of the bits set ON, e.g. you read $ffff or $ff4f. Adding 1, 10, 100, or 1000 milliseconds of delay between each command seems to fix the problem - any of these delay valuses ends up with the same rational values in the VTM Power Registers. So for now I will use 10 milli second delay between commands. I will check with Mark Bowden to see what I need to do. Typical values from slot #8: $014f $034b $014b $0147 Typical values from slot #10: $0349 $0365 $034d $0101 The values are very stable. Why is the next to LSNible a 3 and not a 1 ?? Why does Ch #3 of Slot #10 show Signal Detect asserted ?? I asked Marc Bowden about "is there a required delay between VTM read adc command and reading the VTM Power register". He said yes, and the answer is 5 msec per each channel that you read. Edit the file \Trics\Scratch\Read_VTM_Optical_Power.vio so that it reads the optical power level from all 4 channels on all 9 VRB's. Tested VRBC and found the same NO L1 Busy problem when it is out of buffers. Talked with Marvin, Jae, and Daniel about it. Daniel is working on it and will test when ready. Installed the 2nd SCL cable to Mike Utes and Company on the 3rd floor electronics area. Long talk with Bob Kehoe about the Pulser Run analysis program for the L1 Cal Trig. Went through the description of buffering and readout in Run II and format of the L1 Cal Trig data. Pushed rational eta.phi for analysis and evolution of what questions we will want to ask of the data. Sent him pointers to the documentation. Master Clock What is in the TrgMgr account on D0ol02 about the Master Clock. The major problem is that none of the "c" source files for the various versions of the master clock program were ever kept. We have just the executables. The directory master_clock contains just the subdirectory config_files and it is this directory that contains the various versions of the executable, and the latest version of the "c program" source code which is called clkSetup.c. The clock_file_master_list.txt on the web in the framework timing directory contains a description of the various versions of the executable. There are no dates listed so it is hard to match up with the log book to see what these various versions were to be used for. The other clock related directory in TrgMgr is onl_clock. I think this gets made when you do the "cvs checkout onl_clock". onl_clock contains the directories: CVS, bin, doc, include, lib, src, ups, and the file: Makefile. The "c progrram" source file is in src/ioc/clkSetup.c but of course this is what comes out of cvs so we need to get our version of it from master_clock/config_files. The functions to control the Modes of the PCC and the Sequencer are visible in the clkPcc.s and clkSeq.c files in onl_clock/src/ioc. The files in onl_clock/src/ioc/ are: bitArray.c, bitArrayTest.c, clkPcc.c, clkPccTest.c, clkSeq.c, clkSeqTest.c, clkSetup.c, clkSfm.c, clkSfmTest.c, and timeline.c Master Clock continues to run just fine in PCC Normal Mode. ReWork of CTFE's for Run II Visited SiDet to talk about getting the re-work done on the CTFE cards. The person there who is in charge of this is Jill Calderon, jill@fnal.gov x8630. They are stacked up with work right now but should have some time available starting at the end of next week. So I will visit again next week either Thur or Friday. Right now they are continuity testing some boards with 12k vias. Need more 3/4" ID 7/8" OD CPVC pipe and cable ties to Fermi. DATE: 7:10-FEB-2001 At: Fermi Topics: Meetings, Master Clock, Cables up to 2nd MCH, VESDA, RPSS, Cooling water, BBA's, LED Pulser, Current VRBC. Talked with Jae about the first few stores. Master Clock in sync mode and software Xaionan Li. He will add stuff for a 2nd sequencer, and talk with Fritz about how to handle begin of store stuff. Meetings with LeDu and a new engineer from Orsay. Normal Machine RF looks like 53.10355 MHz on the counter here with the rotation frequency reading 47.71209 whitch do match On the PCC that we have been using, the PCLK in FreeRun typically looks like 52.86416 MHz. This is way wrong. A PCC should FreeRun at 53.10421 MHz. TeV RF at 210 GeV is 53.10421 MHz at 1 Tev it is something like 53.10470 PCC capture range is +- 530 Hz Friday noon, we get a replacement PCC and this one appears OK. Based on the FreeRun Frequency of the PCC that we had been using, Steve remembers that this is "the bad one from CDF". Now have 2 of the new Sequencer Modules. We can not plug in the 2nd one bacause it wakes up wanting to drive its signals out onto the bus. So we need to get it included in the C program and set its outputs to be disabled. Moved L2 Fiber optic out of the hole. Pass VESDA Test. VESDA sees the test smoke from M122 in 7 seconds. This is with the Cal Trig blower running. The trip is set for a 15 second delay. This was part of the contractors certification test. Got the Drip Detector working and the Photo-Helic re-installed. The full RPSS is now back working. M101,M102,M114 are now jumpered out of everything. The RPSS Rack Sensor Dummy Jumper Plug connects the following pins: 1 to 9 2 to 10 4 to 12 6 to 14 and 7 to 15 List of 7 "orthognal" BBA's for Run II -------------------------------------- 56 = 00111 000 Spare BBA 152 = 10011 000 Tier 2,3, MTG 168 = 10101 000 Tier 1 Upper Eta 1:8 176 = 10110 000 Tier 1 Lower Eta 1:8 200 = 11001 000 Tier 1 Upper Eta 9:16 208 = 11010 000 Tier 1 Lower Eta 9:16 224 = 11100 000 Tier 1 Eta 17:20 In each of these BBA's you use the sequence 1,2,4,7 as the lower 3 bits of the MBA. Water flow turned back on in M103, M104 and the 8 pack at M112/M113. The 8 pack in M102 has been running all along. Ran the Cal Trig Control Crate (i.e. the old Framework Expansion) and the 4 Tier 1 crate in M103 and M104. All power supplies look more of less Ok except for M103 Lower Tier 1 -4.5 Volt supply is drifting around and making noise. Did random register test in the 4 Tier 1 crate for millions of loops and all looks OK so we can keep this Ironics to Comint setup. Mitch Wayne came by asking for between 6 and 16 Master Clock time lines for LED pulser for CFT. Sent a note to him and Don suggesting SCL timing. I think that the VRBC that we have right now does not assert L1 Busy when it runs out of buffers. I think it just asserts L1 Busy during the transfer into the VRB. This runs at 20 OK with FW only. At 31 or 32 Hz it trashed the data after some minutes of running. I think that this VRBC does get inited by SCL Init and that it does not hang on L2 Rej. Ran about 8k looks of SCT testing everything and that was OK. DATE: 1-2-FEB-2001 At: Fermi TOPICS: Comm Crate and L1 Cal Trig CBus work, SCL Hub-End work, return power supply, Master Clock test, VRBC running, TRICS Rev H SCL Cables to the Platform The 6U Communications Crate in the bottom of M124 is now running on SCL Hub-End Crate power supply. Two runs of #6 wire with 25 Amp fuses are used to connect the Communications Crate with this Run II Framework Power Pan. Installed the 40 conductor twist and flat cables (9 sections long) to connect the COMINT Card with the Ironics Paddle Brd. Tests of CBus I/O look OK so far. Test of Vesda did not pass. The bast idea is that I need to remove the back tube and plug up most of the holes in the tube running across the top of the racks. Talked with Rick Hance about connecting power to the Cal Trig Blower. Ran the Cal Trig Blower and M103 Upper Tier 1 crate. Swapped in the CTFE "test card" for the normal Phi 8 card (CA=46) and ran the Serial DAC control at Fermi. Dean and I looked at readout noise. Could not look at signals (no argon, no HV, no Preamp power). The swing in the signal of the final design of the Term-Attn-Brd looks better than the proto-type. Got back Power Pan SN# 8 from the L2 Test Area. Stu needed a rack that they had stuck the supply in. It had not been used for some weeks. I did not test it yet. Installed 8 LMR-200 SCL Serial Data cables to the Platform. These are for the SVX Sequencers. This makes a total of 12 SCL serial data cables to the platform. Could not make the Master Clock Sequencer run from raw machine RF although it did work better than with PCC in Sync Mode. You get junk SCL data about once every 5 seconds using raw RF and Sync to control the Sequencer. The signals from the Free Run PCC going to the Sequencer look like the following: --------------- 18 ns ------------------- SYNC | | -------------- ------- ------- ------- RF | | | | | | ----- ------ ------ ----- This is NIM suff (so low is active). Sync goes low 3 nsec after RF goes low. RF goes hi 6 nsec after Sync has gone low. RF goes low 2 nsec before Sync goes hi. I assume that the active part is right at the end with the falling NIM edge of RF with Sync low. With the Sequencer running from the PCC in FreeRun mode the frequency was 53.104290 MHz. With the Sequencer running directly from TeV RF the frequency was 53.103557 MHz. Current setup of SCL Status flat cables to the Calorimeter ADC's i.e. this is how things are plugged in at the SCL Hub-End. Note that a couple have been moved. Geographic Is Currently Using Status Section Cable Labeled GS Number ---------- ------------------------- 40 --- * 41 --- * 42 ------------------ 4C 43 ------------------ 43 44 --- * 45 --- * 46 --- * 47 --- * 48 ------------------ 48 49 ------------------ 41 4A ------------------ 4A 4B ------------------ 4B 4C --- * 4D --- # 4E --- # 4F --- # * No Status Cable Plugged in at the SCL Hub-End # Not used by Calorimeter Work with Neal on SCL Hub-End. Verify that we can see that FanOut 9B in the slot that services Geo Sections 58:5F. We can see the problem with its Ch 7 stuck bit of value 2. We try swapping with a known good FanOut but it does not work at all. That is SCL Receivers will not sync with any channels on this known good SCL FanOut - so Neal takes it back. Try the production Hub Controller. We see junk data when we use it. For example the Current BX number is OK but the L1 Trig BX number is junk most of the time. So we switch back. So no changes, everything is put back the way it was. VRBC running. Had problems with the VRBC never telling the SCL Receiver to sync to the serial data, the system hanging L1 busy after about 3k events, and the wire-trace that loops the lock status back to the hub-end being on the wrong pins. Daniel is looking into the problems. Started running TRICS Rev 9.1.H and left H running with the note on the key boards saying run Rev H. Starting with Rev H TRICs does setup the VRB's for 16 buffers. DATE: 25,26-JAN-2001 At: Fermi Topics: Friday afternoon meeting in Harry's office about L1 Cal Trig status: Fire 2/3 of the people and blame the late delivery on those left, says that they will not accept help, misunderstand bringing an FPGA project to market and fixate on P-Terms, appear surprised at the list of Run I support software, lack understanding of resistors. Measure the cables from the Ironics to the COMINT should be 9 twisted sections long. The Run I BBB and MBA addresses used in the L1 Cal Trig are: for Tier 1: 168 with MBA's 169, 172, 170, 175 200 with MBA's 201, 204, 202, 207 224 with MBA's 225, 228 for Tier 2: 176 with MBA's 177 208 with MBA's 209 248 with MBA's 249 for Tier 3: 152 with MBA's 153 168 = 10101 000 200 = 11001 000 169 = 10101 001 201 = 11001 001 170 = 10101 010 202 = 11001 010 172 = 10101 100 204 = 11001 100 175 = 10101 111 207 = 11001 111 224 = 11100 000 176 = 10110 000 225 = 11100 001 177 = 10110 001 228 = 11100 100 208 = 11010 000 209 = 11010 001 152 = 10011 000 248 = 11111 000 153 = 10011 001 249 = 11111 001 DATE: 18,19-JAN-2001 At: Fermi Topics: Install crate in M103 top for L1 Cal trig timing distribution and CBus fanout. The top 6 slots are bussed in the "P4 ?" connector, i.e. the one furthest to the left when you view it from the back. The other 3 connectors are not bussed in the top 6 slots. The bottom 14 slots are not bused at all. But the 7th from the top connector has some of its pins cut off. Need to shorts check all of this. There was some epoxy on some pins but I think that I have chipped it all off. I think 10 slots are needed for timing fanout. This is 10 TLM cards. TLM cards are ECL only so they can use the slot near the bottom that has double ECL power and no Vcc power. I expect that the CBus part can be 1 COMINT and perhaps 3 BBB (e.g. upper Tier 1, lower Tier 1, and Tier 2&3). J4 J3 J2 J1 -------------------------------------------- 20. | ======== ======== ======== ======== | | | 19. | ======== ======== ======== ======== | | | 18. | ======== ======== ======== ======== | | |||||||| | 17. | ======== ======== ======== ======== | | |||||||| | 16. | ======== ======== ======== ======== | | |||||||| | 15. | ======== ======== ======== ======== | | | 14. | ======== ======== ======== ======== | | | 13. | ======== ======== ======== ======== | | | 12. | ======== ======== ======== ======== | | | 11. | ======== ======== ======== ======== | | | 10. | ======== ======== ======== ======== | | | 9. | ======== ======== ======== ======== | | | 8. | ======== ======== ======== ======== | | | 7. | ======== ======== ======== ======== | | | 6. | ======== ======== ======== ======== | | | 5. | ======== ======== ======== ======== | | | 4. | ======== ======== ======== ======== | | | 3. | ======== ======== ======== ======== | | | 2. | ======== ======== ======== ======== | | | 1. | ======== ======== ======== ======== | |__________________________________________| J4 J3 J2 J1 View from the Back of the Rack Bus Buffer Board COMINT Card TRG TO TO CBUS CBUS ACQ MBD MBD 2 TSS 1 SYNC _____________________________ _____________________________ ||___| |___| |___| |___| | ||___| |___| |___| |___| | | | | | | | | ^ v ^ ^ | | ^ V ^ V | | v v v | | | | | | | | | | |---<--| |---<--| | | | | TSS C BUS | | ^ ^ | | | | v v | | | | ___ _________ | | | || | | | | ----------------------------- ----------------------------- VMX TCC Front Top View Front Top View CTMBD Card BACK CBUS TSS LOGIC PLANE IN IN PROBE CBUS _____________________________ ||___| |___| |___| |___| | | | | v ^ | | v v v | | | --->----->---+ | | | | | | ---->----->----->--- | | | | | | | ----------------------------- Front Top View DATE: 4,5-JAN-01 At: Fermi TOPICS: New And-Or Input Term, Tests of Master Clock, SCL Status Cables to Cal, SCL meeting with Ted and Neal, TDS3054 view of trigger pickoff noise, talk with Daniel about known VRBC issues. The standard clock setup that we have been running is #33. This has the PCC in FreeRun mode and the Sequencer in Sync mode. Version #34 is the same standard time-lines but moves the PCC to Normal mode (Sequencer remains in Sync mode). Review what the LED look like using the version #33 file: PCC Function LED Sequencer Function LED ------------------ --- ------------------ --- Free Run ON Sequencer Halted OFF Sync Lock OFF Freq Lock OFF Sync Missing OFF Normal OFF Sync Hold OFF BC Phase ON Sync Missing OFF Clk Parity OFF Sync Timing OFF PCLK Missing OFF RF Missing OFF MCLK Missing ON RF Lock OFF Sync Ref OFF Sync Delay Setting 0 BC Ref OFF MCLK Delay Setting 0 Low Parity ON High Parity ON Clock ON ON Recall: Output Enabled ON PCLK is 53 MHz Step Mode OFF MCLK is 106 MHz Free Run OFF Sync ON Group A On ON Group A Selected ON Group B On OFF Group B Selected OFF Worked trying to run the Master Clock from Tevatron signals. The NIM processed Tev RF and TeV Sync were jumping around wrt each other. I think the problem was simply that the AND logic had the TeV RF arriving first and then the TeV Sync so that the assertion of the AND was controlled by the arrival of the Tev Sync instead of by the Tev RF. Straightened this out but when trying to run from Tev signals again the SCL would still not stay locked. But the big problem was when returning to PCC FreeRun mode the PCC was puting out the wrong frequency - it was 52.9?? MHz. Files in the boot directory: clkSetup_Norm_Sync_04JAN01 and clkSetup_std_in_use_04JAN01. Only difference is the mode of the PCC. All Time Lines are the normal standard setup. Current setup of SCL Status flat cables to the Calorimeter ADC's i.e. this is how things are plugged in at the SCL Hub-End. Geographic Is Currently Using Status Section Cable Labeled GS Number ---------- ------------------------- 40 --- * 41 --- * 42 ------------------ 43 43 --- * 44 --- * 45 --- * 46 --- * 47 --- * 48 ------------------ 48 49 ------------------ 41 4A ------------------ 4A 4B ------------------ 4B 4C ------------------ 4C 4D --- # 4E --- # 4F --- # * No Status Cable Plugged in at the SCL Hub-End # Not used by Calorimeter Connected another temporary And-Or Term. This one is: AOIT # 6 requested name ICD_TEMP_COSMIC Put the list of "currently connected And-Or Terms" on the web at: http://www.pa.msu.edu/hep/d0/ftp/l1/framework/andor_terms/ connected_andor_term_list.txt Meeting with Ted and Neal about final details of SCL. Minutes from the meeting. I need to return SCL FanOut SN #9B to them. It is the one with the broken bit in its Ch #7. We are officially putting further attempts to use the production Hub Controller on hold until this becomes the hottest fire. DTACK* from 2 of the Status Concentrators. First try a swap of the FanOuts in these slots to see if that fixes the problem. If that does not fix it then scheduled at a time when Neal can come help if that is necessary: Uncable slots 20 and 21 and test two spare Status Concentrators to prove that we have working spares. Uncable as far a the first slot with that does not DTACK* (this is the 9th Concentrator vme slot 14) and try a known good spare concentrator. If this works go ahead and also replace the concentrator in vme slot 7 i.e. the 3rd Concentrator. If this does not work, i.e. if the problem appears to be related to the slot then call Neal. The scan to see over what range of relative phase between the 7 MHz and the 53 MHz will the system work (it is about a 5 nsec range) does fit with what Ted and Neal expect. Neal will review the front panel hardware signals and VME bus cycles involved with the Interrupt function of the SCL Hub-End and some time in the future we will talk about it. Known VRBC issues: The production firmware version that we have stops at 3k events. The single buffer version hangs L1_Bz when it gets an L2_Rej. The signle buffer version hangs L1_Bz if it is waiting for a the VBD DONE when it gets an SCL Initialize. Look at Trigger Pickoff noise on channel EM 1,8 Most of the time the biggest non readout noise is 25 mV base to peak. There is some 132 nsec stuff that is typically 10-15 mV. Readout related stuff (much slower time scale than real signals) is mostly below 45 mV. At times the noise is much bigger. Some readout cycles appear to have bigger noise and there is some non readout noise that at time is big. All of this comes and goes and I assume it is related to all the activity in the hall. From unix the printer on the 1st floor is called; dab1_hp8000