D-Zero Hall Log Book for 2002 ------------------------------- The most recent entries are near the beginning of this file. This file begins in January 2002. Earlier D-Zero Hall Log Books are on the web either in the directory with this file or else at: http://www.pa.msu.edu:80/hep/d0/ftp/run1/l1/inventory_logs. DATE: At: Fermi TOPICS: DATE: At: Fermi TOPICS: ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ DATE: 17:20-DEC 2002 At: Fermi Topics: Work on Cal Trig high eta readout, See the TFW readout stop, Power Supplies, VESDA, Watter System startup. System Restart We have built up a long list of things that we need to do by hand to re-start the system. After Master Clock is running, turn on TFW and Cal Trig then Configure FPGA's By hand configure the RM FPGA's Init TFW and CT Tell TRICS to completely ignore the CT By hand execute the cio file to wake up the eta 13:20 part of CT By hand using VME Access load the CT Gains for eta 1:12 By hand using VME Access load the CT Pedestals for eta 1:12 By hand using VME Access load the CT Gains for eta 13:20 By hand using VME Access load the CT Pedestals for eta 13:20 Tell TRICS that it has control of the CT again Init the TFW and CT verify that it is a clean init of all parts Then either by hand tell the TFW not to bypass L2 Global or tell COOr to issue a "initl1fw" which will tell TFW not to bypass L2. The file to configure the RM FPGA's is Scratch\Dave_Configure_All.dcf The file to wake up the eta 13:20 part of the Cal Trig is D0_Config\Init_L1CT_HighEta.cio The current Gain anf Ped files for eta 1:12 are D0_Config/Run_II_l1CT_Bob_7_Gain.tti;1 D0_Log/Find_DAC_V3_1_h_20021211.tti;1 The current Gain and Ped files for eta 13:20 are D0_Config/Gains_13_20_1_8_rev_a.tti D0_Log/Find_DAC_V3_1_h_20021218_Edited.tti;1 Readout from TFW. This week we finally had an occasion of a readout problem from the TFW while I was here to see what happened. TFW was 100% missing in the readout. L2 was happy making L2 Decisions (i.e. TFW was feeding L2 or alse L2 would have stopped you could also see that the TFW to L2 Glb input buffer was happy). I looked at the last event that the SBC had and that was OK. Look at the TFW's VRBC and its SCL Receiver's yellow LED is out. OK, this fits in with everything else that I see. So do nothing except a VRBC reset and everything starts working OK again. We have had a power quality tester in the M124 rack for the past week. It has picked up "transits > 500 Volts" a couple of times now. This is just a simple 110 V plug in thing. They are going to bring over a fancy tester. More stuff about the TFW readout issue is in last weeks notes. Files changed this week to add the high eta readout M101_all.dcf This was edited so that it now configures all 10 Spark/Bougies for Cal Trig readout. Note that this files name is not correct because it does not configure all FPGA's in M101 - the RM FPGA's are not configured by this file. Init_Post_Auxi_CT.rio This was edited so that it now sets up the control registers in all 10 Spark/Bougies. Init_Post_Auxi_CT.vio This was edited so that it now sets up the first VRB to enable all 4 channel pairs and it sets up the new 3rd VRB to have its first 2 channel pairs enabled and it sets up the SBC/VBD to readout 3 VRB's (not just the previous 2 VRB's). Installed the equipment to turn on readout from the 4 highest eta racks. This took a long time put there were not many problems. The timing bus is setup as described in the June work. CTMBD's are setup the same. Daniel did all the work on the CTMBD's and the Distributor Caps. All the timing cables are in including the one to the high eta Tier 2. We started up the power pans for the Upper Tier 1 in the last 4 racks with the variac. 3 of the 4 were OK but the pan for M110 did not have its -5.2 Volt brick start up. Pull PDM-18 from M110 Upper T1 install PDM-19 from the spares cabinet. PDM-18 had the following bricks: +5.0 SN# 18 14-FEB-92 -2.0 SN# 56 21-JAN-92 -4.5 SN# 60 7-JAN-92 -5.2 SN# 59 7-JAN-92 The -4.5 brick had bad regulation and 60 mV of ripple. Replaced with SN# 57 The -5.2 brick was dead. Replaced with SN# 87. PDM-18 then passed all tests and was setup to match the Tier 1 specification. It is now in the storage cabinet at Fermi. Take a look at PDM-09 the dead pan from last week. PDM-09 had the following bricks: +5.0 SN# 6 15-OCT-90 -2.0 SN# 25 15-MAR-91 -4.5 SN# 27 15-MAR-91 -5.2 SN# 26 15-MAR-91 The -4.5 brick is very bad (low voltage and 500 mV ripple) and was pulled out. The -2.0 brick is very bad (low voltage and 100 mV ripple) and was pulled out. The -5.2 brick should be checked under toster load. Under crate load its voltage was OK but it had 15 mV of ripple. We have at Fermi spare bricks for the -2 and for the -4.5. But that is all the spare bricks at Fermi. If the -5.2 needs to be replaced I need to find a working 200A brick. The following 6 Pioneer Magnetics 5V 200A brick all of the "new" type are being retured to MSU for repair. They are all bad and need to quickly go to Pioneer for repair. SN# 25 27 59 60 97 98. Water is now turned on M109 M110 M111. So far they look OK. When I turned the fan back on after having it off for the high eta work a small amount of water blew out from under M105. Scott saw some water in this area. Scott Snyder's log book entry is: Mopped up a small amount of water from MCH1, in front of the trigger framework. No obvious source, although the door on the rightmost rack has some dried mineral deposits on the outside -- no telling when they were made though. Temperature inside is 72deg, RH is 49%. Will look in again in another hour or so. And then from Jae. Date Created: Thursday, December 19, 2002 9:14:54 PM CST Operator(s): Jae Yu Lars noticed three large water puddles on the floor in between the racks in MCH1 under the second light fixture from the door on the right. Stefan felt water on the channel along the edge of the light fixture. Spoke to Pete Simon. He indicated possible leak from MCH2. Contacted Bill Frank to investigate the possible leak. I have looked in M105 and around there and it looks OK. It could be a leak in the header under the lower Tier 1 pan in M105. While the Cal Trig fan was off (after a couple of hours) the vesda went into excess air flow trouble state. This has not happened before. We ended up calling the fire techs. They did the PM on it and it then was happy. While test smoking it, they could not get it to respond to smoke from M122-M124. I have verified this piping and it all looks I found BLS cables +7,5 and +8,5 crossed. Thanks Global Monitoring. I did not test the De-Mux card as I promissed that I would. ------------------------------------------------------------------------------ DATE: 10:13-DEC 2002 At: Fermi Topics: Work on Trigger Towers, Work on Cal Trig, Investigate TFW readout, Cal Trig Power Supplies, L2 De-Mux Card, TFW Readout Guastaaf proves that, over the network, telling the TFW SBC to re-boot does not cause a SYSRESET to be issued in the TFW readout crate. Doug removes that jumper that causes the SBC to re-boot when SYSRESET is asserted in the TFW readout crate. While the SBC is pulled out of the crate he also verifies that the SBC is not jumpered to issue a SYSRESET when it boots. Dan cuts the trace on the Vertical Interconnect that goes to pin C12 i.e. to the SYSRESET pin. Then demonstraited that pushing the Vertical Interconnect front panel Reset button no longer caused a SYSRESET in the crate. Thursday morning the SCL Hub-End switched from normal running to its mode of not sending out any data. It still sends its link clock so all the SCL Receivers stayed in sync. I have never seen this happen. You could tell that it happened because the Yellow LED on all of the 16 SCL Fanout Cards went out. Could this have been caused by a random SYSRESET in that crate ?? Just ran the FW Post Init Auxi VIO file to turn the SCL Hub-End back on and everything started up. Thursday, put a voltage drop out monitor on the power in rack M124. Could this be a power glitch ?? I doubt it but we have possibly seen SYSRESET from outer space in both crates in that rack. The breaker in the panel on the wall for that rack is not hot. Bring 126 tested Term-Attn-Brd's to Fermi. L1 Cal Trig Work in the current eta coverate (first 6 racks) Term-Attn-Brd's with pedestal control problem (have been Excluded) Action TT CHANNEL RACK Reason for Excluding Today ----- -------- ---- ----------------------- ----------- -11,19 EM M108 No control of pedestal Replaced TAB -11,19 HD M108 No control of pedestal Replaced TAB -6,9 HD M106 No control of pedestal Replaced TAB +10,27 EM M107 No control of pedestal Replaced TAB Term-Attn-Brd's with other problems Action TT CHANNEL RACK Term-Attn-Brd Problem Today ----- -------- ---- ----------------------- ----------- -11,7 EM M108 No EM output signal Replaced TAB -9,22 HD M108 Possible HD Noise Replace TAB -2,28 EM M104 EM output 145% of expected Repaired TAB -1,4 HD M104 HD- = HD+ but only 60% of expected Replaced TAB -1,25 EM M104 EM+ input looks 50% low Repaired TAB -1,28 EM M104 EM- signal is dead Repaired TAB +8,12 HD M105 No HD output signal Replaced TAB +9,20 EM M107 No EM output signal Replaced TAB Special Term-Attn-Brd's needed to fix other problems Reason for the Date of TT CHANNEL RACK Special Term-Attn-Brd this Entry ----- -------- ---- ----------------------- ----------- -2,1 HD M104 Broken BLS Backplane Modify TAB center conductor pin GB +in 84 Ohm to Gnd Special 2x Gain TAB GB -in to BLS Cable BLS HD- signal is OK. no attn just 84 term. -2,5 HD M104 Broken BLS Backplane Modify the TAB center conductor pin GB -in 84 Ohm to Gnd Special 2x Gain TAB GB +in to BLS Cable BLS HD+ signal is OK. no attn just 84 term. All of the replacement TAB's have the correct R3 and R80 and have been tested. Because of the correct R80, the following EM channels ( for even eta's >5 ) will need to have their Gain turned back up to the nominal correct value. -12,7 EM -12,19 EM -10,22 EM -6,9 EM +8,12 EM +10,20 EM +10,27 EM This is the Bob_Gains_7 file. Stop Excluding any channels. Run Find_DAC and it finds a pedestal for all TT's. Then Exclude just -9,22 HD and +3,26 EM both because of too much noise on thier BLS signals. The files to use to start Cal Trig from power up are: D0_Config/Run_II_l1CT_Bob_7_Gain.tti;1 D0_Log/Find_DAC_V3_1_h_20021211.tti;1 I have seen water in front of M105. Is the old water from a previous leak from the 2nd floor or is there a leak in the L1 Cal Trig. So far I can not see a leak in the Cal Trig. This water was under the lower "C" channel of the build out in front of M105. We have a number of failing power supplies in the L1 Cal Trig. Last weekend we had some readback errors from the Lower Tier 1 crate in M106. It has a failing -2V brick and a failing -4.5 V brick. In M106 Lower Tier 1 pull PDM-09 and install PDM-17. Then Survey of the Tier 1 Power Supplies M103 Upper Tier 1 M103 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.045 0 5.056 0 -2.0 V 2.105 V 2.058 0 1.975 55-155 -4.5 V 4.610 V 4.556 0 4.439 125-260 -5.2 V 5.230 V 5.248 0 5.224 5-30 M104 Upper Tier 1 M104 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.049 0 5.059 0 -2.0 V 2.105 V 2.103 0 2.106 0 -4.5 V 4.610 V 4.604 0 4.607 0 -5.2 V 5.230 V 5.238 0 5.232 0 M105 Upper Tier 1 M105 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.056 0 5.066 0 -2.0 V 2.105 V 1.972 80-180 2.105 0 -4.5 V 4.610 V 4.605 0 4.450 120-270 -5.2 V 5.230 V 5.225 7-40 5.229 1 M106 Upper Tier 1 M106 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.040 0 5.056 0 -2.0 V 2.105 V 2.016 20-85 2.102 0 -4.5 V 4.610 V 4.372 300-440 4.536 70-170 -5.2 V 5.230 V 5.219 3-20 5.275 21-90 M107 Upper Tier 1 M107 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.056 0 5.053 0 -2.0 V 2.105 V 2.108 0 2.105 0 -4.5 V 4.610 V 4.614 0 4.431 270 -5.2 V 5.230 V 5.221 0 5.224 14 M108 Upper Tier 1 M108 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5.056 0 5.062 0 -2.0 V 2.105 V 2.000 32-112 2.105 0 -4.5 V 4.610 V 4.607 1 4.459 125-260 -5.2 V 5.230 V 5.226 9-55 5.234 4-30 Form M1 Upper Tier 1 M1 Lower Tier 1 Nominal -------------------- -------------------- Supply DC Output DC Output Ripple mV DC Output Ripple mV ------ --------- --------- --------- --------- ---------- +5.0 V 5.055 V 5. 0 5. 0 -2.0 V 2.105 V 2. 0 2. 0 -4.5 V 4.610 V 4. 0 4. 0 -5.2 V 5.230 V 5. 0 5. 0 Drew Baden was here this week. He has a new firmware for the DeMux board. It is ready to try. This gives 150 plus nsec of delay between the last data change and the strobe. The strobe lasts for 500 nsec. He has a TFW power supply upstairs to run his DeMux card in the L2 Test Stand. Make a first look at the BLS signals in the rack for eta +17:+20. Use a 48 nsec cable for the BX Marker signal. Use a 16 nsec cable to get the ADC Clock which is coming from the rack for +9:+12 If the ADC_Clk is before the peak of the input signal then this time is labeled with a "+". If the ADC_Clk is after the peak of the input signal then the time is labeled with a "-". In the following table all of the cable length delays have been taken out. Eta +9:+12 ADC Input ADC Clk Peak BX Marker Falling Edge Eta,Phi EM/HD Amplitude WRT Input Peak WRT Input Peak ------- ----- --------- -------------- -------------- +17,17 EM 150 mV 720 ns -36 ns EM 275 mV 732 ns -28 ns EM 250 mV 736 ns -24 ns +17,17 HD 120 mV 684 ns -76 ns HD 150 mV 676 ns -84 ns HD 120 mV 680 ns -80 ns +19,17 EM 200 mV 724 ns -36 ns EM 225 mV 720 ns -40 ns EM 325 mV 760 ns 0 ns EM 275 mV 736 ns -20 ns EM 300 mV 776 ns +16 ns +19,17 HD 675 mV 692 ns -64 ns HD 850 mV 692 ns -64 ns HD 725 mV 692 ns -68 ns HD 725 mV 692 ns -64 ns +20,17 EM 250 mV 756 ns -4 ns EM 250 mV 772 ns +16 ns EM 275 mV 772 ns +12 ns EM 275 mV 760 ns 0 ns +20,17 HD 275 mV 740 ns -12 ns HD 400 mV 752 ns -4 ns HD 450 mV 720 ns -36 ns HD 255 mV 776 ns +16 ns I have 3 scope pictures of +17,17 EM and 2 scope pictures of +19,17 HD that I will add to the collection on the web. The ICD looks nice and big and clean and always the same shape and always the same point in time wrt the BX marker. The MG signals look, well let's say that they do not look like ICD signals. +19,17 EM (an MG signal) most noise small signals +20,17 EM (an MG signal) least noise small signals +20,17 HD (an MG signal) middle noise bigger signals Do we have any idea where to set the Term-Attn-Brd gains for the ICD and MG signals ? For all the normal calorimeter signals we have a starting point just from the geometery. Were are we going to set the CTFE timing in eta 17:20 ?? Center to Center the SCL Patch Panel SMA bulkhead connectors are 1 1/8" apart. SCL runs to STT $70:$75 checked. Installed patch cords and label the 3 new SCL runs to L2 Test Stand. Installed Tick Clk on the 3rd channel of the converter to FPD and labeled the cables at the CMC end. Connectors and cable setup for FPD And-Or Terms. We have seen a couple of time when all phi's at eta -7 light up in the L1 Cal Trig Examine. This is EM only. This shows up a little bit in the sum of the Et for many events and it shows up more in the "hit count" i.e. the number of times a give channel has more than some low threshold of energy in it. This comes in short bursts once every couple of hours or so. Is this the old ring of fire ? Talked with Harry. Need to contact Dean. ------------------------------------------------------------------------------ DATE: 6-Dec 2002 At: MSU Topics: Update Excluded_Trigger_Towers.msg \\d0tcc1\Trics\D0_Config\Excluded_Trigger_Towers.msg was updated to add the exclusion of HD(-9,22). This file was copied back to \\msul1a. ------------------------------------------------------------------------------ DATE: 3-Dec 2002 At: MSU Topics: Backup of Trics Log and Run Files Take snapshot of all current Trics Run Files in \\d0tcc1\trics\ A copy of D0_Trics_II_Run_2002_12_03.zip was put on \\d0server4.fnal.gov\users\laurens\d0tcc1\D0_Trics_II_Run_Files\ All new Run Files were also copied to \\msul1a\Trics and Windiff was run to verify that all current files were captured. Grab a copy of all November Trics Logfiles from \\d0tcc1\Trics\D0_log\ for archival. ------------------------------------------------------------------------------ DATE: 2-Dec 2002 At: MSU Topics: Remotely Restart Trics V10.1.B Call the control room to restart Trics before the next store. ------------------------------------------------------------------------------ DATE: 25-Nov 2002 At: MSU Topics: Find_DAC and stop Excluding 5 TT's Bob has repaired the 5 BLS cards that were making constant 30 GeV sawtooth oscillation. So now this evening from MSU we can run Find_DAC on these TT and if all looks OK stop Excluding them. I asked for L1 Cal Trig to be taken out of the global Zero-Bias run and then using VNC get connected to TCC1. I found TRICS with the "VME Direct Access" menu displayed. It was setup to run the "Init_Post_Auxi_L1CT.vio" file. No one told me that they have needed to do this. Edit the D0_Config\ Excluded Trigger Tower list file to stop Excluding the 5 towers that we will work on. Initialize the Cal Trig to get these 5 TT's back running. Tell TRICS to Totally Ignore the Cal Trig so that we can work from VME Access. Run Find_DAC on single Trigger Towers at a time. They are: +5,27 HD +5,30 HD +6,10 HD +6,29 HD +6,31 HD Creating no output files I ran Find_DAC 2 times on each of these TT's I then ran it a 3rd time making just the Histogram output file. All passes got almost the same Pedestal DAC value: 3657 3779 3635 3670 3627 3656 3779 3633 3670 3627 3657 3779 3633 3671 3628 A very tight pattern considering that these are HD towers and that one Pedestal DAC count is only about 1/13 of a ADC count. The histograms for the 5 runs of Find_DAC that made output files looked OK. So Edit the current Pedestal File D0_Log/Find_DAC_V3_1_h_20021119_Edited.tti;1 to add these 5 TT's. Load Gains. Load Pesestals. Tell TRICS that it once again has the Cal Trig. Initialize L1 Cal Trig. Watch TT_ADC_Mon for a while. It looks OK. Call the Control Room and ask them to put the Cal Trig back in the global Zero-Bias run. After it is back in and Zero-Bias is running again, use the VME Access to look at the HSRO Cal Trig data to verify that it all looks OK. The files to use to start Cal Trig from power up are: D0_Config/Run_II_l1CT_Bob_6_Gain.tti;1 D0_Log/Find_DAC_V3_1_h_20021119_Edited.tti;1 ------------------------------------------------------------------------------ DATE: 19:21-Nov 2002 At: Fermi Topics: Work on Trigger Towers, Help Levan with CTT And-Or Terms, talked with Nirmalya about Cal SCL, talked with Steve Chappa about Master Clock, talked Andrew about FPD And-Or Terms. Tuesday we had a 11 hour access and all 4 of us worked on repairing TT's. This included fixing BLS, fixing cables, and making lots of tests. All details are in the TT Repair Log Book. Also worked on some Term-Attn-Brd's. Brought tested Term-Attn-Brd's from MSU and installed them in: +4,17 EM +5,9 HD +5,27 HD +5,30 HD +6,10 HD +6,29 HD +6,31 HD I then ran FIND_DAC one at a time on just those TT's and I think it was happy with all of them. BUT I think that the Gain File had not been loaded since the power was off in these crates. They looked OK so load the BOB_6 Gain file and then run FIND_DAC over the whole eta,phi. It does not find good pedestals for: +5,27 HD +5,30 HD +6,10 HD +6,29 HD Look at the histograms and they all look the same, i.e. for each of the tried values of the pedestal dac these channels readout values in the range 0:100 with a standard deviation of typically 30. Just junk all over the place. Why this tight group of HD channels ? +6,31 HD did find a good pedestal value and its histograms look normal. But when I looked at TT_ADC_Mon it was showing values in the range 24 and 25. I have no idea what is going on with this TT. Unfortunately the new Term-Attn-Brd's only fixed 2 of these TT's. +4,17 EM and +5,9 HD now appear OK and are no longer Excluded. Next day look at the BLS signals for these TT's and the real problem with +5,27 HD +5,30 HD +6,10 HD +6,29 HD +6,31 HD is 30 GeV of noise coming to it from the BLS. We need to fix these 5 BLS's. Worked with Levan on the And-Or signals from the CTT. Setup the ECL scope box. The signals on their cable now look stable and have a full tick of slack time making it to the TFW. The problem was that they did not have a strobe signal. The cause of this was a non connecting pin on the trigger manager card that they are using. That was fixed and then things look OK. Talked with Nirmalya and he said that there have been no additional problems with the 3rd floor Cal SCL runs since this was straightened out Saturday night 9-NOV-2002. I talked with Steve Chappa. Since the scope was installed in the Master Clock rack at the end of July, Steve has been watching the RF used by the PCC vs the PD pickup. Since he started tracking this in August he thinks that the CMC has moved 2 nsec earlier wrt PD. Is this drift or a seasonal move ? Which moved the fiber optic RF that runs direct from the RF building or the PD pickup that has about 600 or 700 ft of cable ? I will let Dmitri know. Talked twice with Andrew Brandt and company about getting And-Or terms from the FPD control room. They want to start doing this because the trigger from L0 Luminosity system that they want is not ready. They wanted to just send some NIM signal. I passed them the appropriate documents and I think that they now understand what needs to be done. They do have copies of the necessary timing signals in their control room so that they can generate the standard And-Or Term signal set. They would use another NIM-ECL box in their control room and run another differential ECL cable to the MCH. The files to use to start Cal Trig from power up are: D0_Config/Run_II_l1CT_Bob_6_Gain.tti;1 D0_Log/Find_DAC_V3_1_h_20021119_Edited.tti;1 ------------------------------------------------------------------------------ DATE: 14-Nov 2002 At: MSU Topics: Restart Trics V10.1.B Call the control room to restart Trics between stores. ------------------------------------------------------------------------------ DATE: 9-Nov 2002 At: Fermi Topics: Find front door to M108 not latched, Work on SCL cables, Arrived and found the front door to L1 Cal Trig rack M108 not latched. Investigating a problem with Cal $42. They had swapped the SCL Serial Data Cables for $42 and $43. They swapped by pulling very tight the LMR-100 patch cord for $43. I found loose SMA on the LMR-200 for $42 and $43 (mostly $43). Is this left over from the extender cords to adjust the timing of some of the Cal Geo Sections ? I tightened the SMA's on the LMR-200 and put everything back the way that it should be. So far The Status Cable for GS $34 has some kind of problem. So right now we are using the Status Cable for Muon TFC module GS $0E Status Cable to service $34. This makes everything run OK. Level 3 Routing Master has been running in M101B since 5-NOV-02. So far it is OK. Notes sent about SCL Cable work and about the L1 Cal Trig power control vs Level 3 Routing Master issue. Note sent to Nikos about power supply. ------------------------------------------------------------------------------ DATE: 29-OCT 1-Nov 2002 At: Fermi Topics: Work on TT's, New Gains and Find_ DAC, Plug TT's back in, Work on TFW<->L3 Interface, Trouble restarting TRICS, SCL Cables shorten and install, Shoua Moua will work on SCL and shorted BLS, Swap 2 SCL Hub-End FanOut cards Make a Bob_5 Gains file to add the following to the current Bob_4 Gains setup. There are more EM channels in the eta 5:20 range with the correct value R80. These are: -12,5 -12,9 -12,21 -10,5 -10,9 -10,10 -8,10 +6,20 +10,4 +12,6 Add these 10 TT's to the set that get their gain cranked back up to the nominal value. We are running low frequency filtering in the following 8 TT's: eta -1:-4 phi 17 and phi 31. The gain of these Term-Attn-Brd channels is only about 75% of their nominal value. So, for now, we would like to increase the EM & HD gain of these 8 TT's by a factor of 1.33 Plug back in: -9,19 -8,8 -6,9 -6,23 -4,25 -3,32 -1,9 +3,25 +3,26 +5,23 +6,10 +6 23 +6,24 +8,28 +9,31 These 15 TT's have looked OK in the two recent studies that Joe has made and Bob is anxious to get them plugged back in. 24 hours later, +9.31 goes nuts while Joe is watching it with the trigger Examine. It was firing his 7 GeV threshold at order of 100 Hz. We pull +9,31 back out. Yes, we can see its noise on a scope. It spikes HD to a couple of hundred mV and then oscillates with a period of about 3 usec. Put +9,31 back on the official list of unplugged TT's. Early Friday morning, Nov 1st, about 36 hours after it was unplugged, +6,23 EM blew up. It has a continuous oscillation with an amplitude of order 100 mV and a period of about 1.5 or 2 usec. Yesterday it had been just very noisy but not oscillating. Put +6,23 back on the official unplugged list because of EM oscillation. Wednesday make a Find_DAC run. It found a value for all TT's. This Find_DAC run was done with the Bob_5 gains loaded and with the 15 TT's plugged back in. So the current files to load are: \D0_Config\Find_DAC_V3_1_H_20021030.tti;1 \D0_Config\Run_II_L1CT_Bob_5_Gain.tti Later hand edit \D0_Config\Find_DAC_V3_1_H_20021030.tti;1 to move +6,23 EM from a zer of 3653 to a zer of 3679. +6,23 EM was just plugged back in and it is quite noisy. Find_DAC had picked a value for it that was about 2 FADC counts too high. Work on TFW<->L3 Interface to understand why the top 64 bits of the Fired Mask have not made it to Doug. OK, it's because the cables that carry these 64 bits from the FM Latch in M122B to the patch panel on top of the TFW were never plugged into the FM. Take care of this. Thursday afternoon do the normal re-start of the TRICS program. As the new instance of TRICS started up it got through I$ Creating Objects for L2 Helper Function Card I$ Creating Objects for All Cards of the L2 FW and then E$ Memory Map This Vme Segment / bt_map: : ERROR: Insufficient Resources E$ Error Mapping @ Master bla Slave foo ... and these pairs for messages would repeat for a long time and finally result in a TRICS that would not work or else they appeared to go on forever. I tried 3 times. During the 2nd and 3rd try I not sure how far it actually got before the error messages started. These will all be TRICS logfiles from 31 Oct. I then ran shutdown and booted TCC1. It woke up and all was fine. Dean would like 3 of his SCL cables shortened. They are GS # 44, 47, 4A. The idea is to pull out the LMR-100 patch cable, put a MCX on the long LMR-200 that runs to these GS's, and to shorten the LMR-200 at the SCL Hub-End as much as possible. I need to order some RG58 size 90 degree MCX connectors. Talked with Tom Regan. Shoua Moua will install the 3 new SCL cables that run to the L2 Test Stand. I have given him all the parts for this. Shoua Moua is also going to work on the repair of the shorted BLS cables out on the platform. Narmalya or Bob will show him what cable to work on. Thursday afternoon as the protons were being loaded, official decision to swap two SCL Hub-End FanOut cards. This was supposed to fix a problem with GS $34. Swapped the card for $28:$2f with the card for $30:$37. The card for $28:$2f currently has no used channels. This did not fix the muon problem. It took about 2 hours to get all detector systems running again. Friday morning we had the first meeting with Ron Lipton and Vince Pavlicek about getting help to make the CHTCR mezzanine for the Quadrant Region Terms. I'm supposted to get the next level of detailed information back to Vince by the middle of the week after the trigger workshop. ------------------------------------------------------------------------------ DATE: 15:18-OCT-2002 At: Fermi Topics: Work on TFW<->L3 Interface, BLS Trig Pickoff Test Stand, CTFE Cards at Checkin, Master Clock Sequencer #1 file, Trigger Tower work. Trigger Tower Work: -10,5 EM had the reported problem of seeing only about 50% of the expected signal. The "problem" is it has a correct value R80. So this channel needs to have it gain turned back up to the nominal value --> Bob_5 +11,4 in M107 had been listed as unplugged for an unknown reason starting on 10-Sep-2002. While working on the system on 18-OCT-02 it was noticed that +11,4 was in fact plugged in but that +11,3 was unplugged. +11,3 had never been listed as being unplugged, i.e. needing to be unplugged. +11,3 was checked on the scope and looked OK. +11,3 was plugged back in. So now both +11,3 and +11,4 are plugged in. +1,17 EM and HD has "non-Dean" capacitors installed at both the BLS Driver and in the Term-Attn-Brd. This test modification is not the way forward so we need to return these to the normal parts, i.e. replace the BLS Drivers and put Dean Caps on the Term-Attn_Brds. Made and installed the cables to carry the L3 Disable signals from the DAVE THE-Cards in M101B to the L3 Disable input on top of M123. These are 13 twisted sections long. Doug has tested L3 Disables 0:63 and he knows how to plug and unplug these cables from the patch panel on top of M123. While I was checking the cables for L3 Disables 64:127 I noticed that the signal from Trig 64 was not working. This is the MSA_Out_0 signal from the THE-Card in Slot #9. The direct side of MSA_Out_0 was sitting at -2.0 V. I checked the card, looking for a broken trace between the driver output pin and the pull down or a short to -2.0 but all looked OK. A cooked output ? So I pulled and labeled AONM Build A SN#8 and installed AONM Build A SN#25. Note that AONM Build A SN#8 could still be used as a Bougie/Spark for I'm not going to dig into what its problem is right now. Got the switch "Pulser Switch Box" from Tom Regan and setup the BLS Trigger pickoff exerciser at the side of the 5k Test Stand. At this time (after repairing a bunch of them) all 48 channels on the switch box are working. This uses the Pulser from MSU and two scopes from Tom. I have shown Bob, Joe, and Daniel how it works. Work on the 22 CTFE Cards that had noted problems at checkin. In these 22 cards, found 2 more with pinched wires, that had not been noted as having pinched wires. The cards that were checked in are: Eta +-1, Phi 4:32 and Eta +-17, Phi 1:32. So we still need to check in Eta +-1, Phi 1:3 and the 8 spare cards that recently came back from SiDet. After my checking, the following 22 cards are labeled either as: OK to Stack or OK for Solo Test. +1,12 SN# 169 OK to stack Repair the pinched cable that had been noted at checkin. This was a Blk wire in pin 13 pinch. -1,08 SN# 125 OK to stack Repair the pinched cable that had been noted at checkin. -1,15 SN# 31 OK to stack 8.3k Ohm Vee "short". When applying low current -5V this looks OK. I don't know where the 8.3k Ohm is coming from +17,04 SN# 176 OK to stack Repair the pinched cable that had been noted at checkin +17,09 SN# 188 OK for a solo test 21 Ohm Vee "short" is in the analog section. Applying low current -5 moves it to 270 Ohms. Assume it is a Cap. +17,17 SN# 281 OK for solo test 43 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 58 Ohms. Assume it is a Cap. 325 Ohm Vee "short" is in the digital section. Applying low current -5 moves it to 290 Ohms. Assume it is a Cap. +17,18 SN# 266 OK for solo test 3 Ohm Vcc short is in the digital section. Applying low current +5 moves it to 6 Ohms. Assume it is a Cap. 280 Ohm Vee "short" is in the digital section. Applying low current -5 did not move it. I don't know the cause of this "short". +17,23 SN# 285 OK for a solo test Black wire pinched under pin 13. Repaired with super glue. 60 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 57 Ohms. Assume it is a Cap. +17,24 SN# 342 OK for a solo test 170 Ohm Vcc "short" is in the digital section. Applying low current +5 does not change the resistance. +17,25 SN# 340 OK for a solo test It was not noted-recorded on the check in sheet but this card has a black wire pinched under pin #13. Repair it with super glue. 26 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 29 Ohms. Assume it is a Cap. Ignore the 42k Ohms Vee "Short" for now. +17,26 SN# 290 OK for a solo test Pull off the scotch tape that had been left on this card from the glueing operationl. 200 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 175 Ohms. Assume it is a Cap. 45 Ohm Vee "short" is in the digital section. Applying low current -5 moves it to 20 Ohms. Assume it is a Cap. +17,27 SN# 347 OK for a solo test It was not noted-recorded on the check in sheet but this card has a black wire pinched under pin #12. Repair it with super glue. 478 Ohm Vcc "short". Applying low current +5 perhaps moved it to 480 Ohm. Don't really know the source of this Vcc "short". +17,30 SN# 311 OK for a solo test 124 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 122 Ohms. Don't really know the source of this Vcc "short". +17,32 SN# 321 OK for a solo test 242 Ohm Vcc "short" is in the digital section. Applying low current +5 moves it to 160 Ohms. Assume it is a Cap. -17,01 SN# 221 OK for a solo test Pull off the scotch tape that had been left on this card from the glueing operationl. 97 Ohm Vee "short" is in the digital section. Applying low current -5 moves it to 58 Ohms. Assume it is a Cap. -17,05 SN# 296 OK for a solo test 40k Ohm Vee "short" - have no way to investigate this -17,06 SN# 315 OK for a solo test 168 Ohm Vee "short" is in the analog section. Applying low current -5 moves it to 340 Ohms. Assume it is a Cap. -17,09 SN# 295 OK to stack 620 Ohm Vee "short". Applying low current -5 moves it to > 20k Ohms. Assume it is a Cap. -17,22 SN# 225 OK to stack Move, fix, screw. -17,24 SN# 195 OK to stack Move, fix screw. 5 k Ohm Vee "short" can not tell where it is. It looks polarized. -17,26 SN# 348 OK to stack 15 k Ohm Vee "short" can not tell where it is. It looks polarized. -17,28 SN# 213 OK to stack 15 k Ohm Vee "short" can not tell where it is. It looks polarized. Edit the Master Clock #1 Sequencer file so that BC_REF is moved 2 RF Buckets earlier. We started generating BC_REF on about 18-SEPT-02. It is the time line type signal that you can compare with the actual beam pickup. The guess at its location was about right but it was happening about 38 nsec after the center of the PD signal. ------------------------------------------------------------------------------ DATE: 2:4-OCT-2002 At: Fermi Topics: Work on Trigger Towers During access on Wednesday, work on BLS signals in platform: -11,6 which is in PN13 BLS Cable was tested and it is OK. -6,21 which is in PC00 BLS Cable was tested and it is OK. -5,3 which is in PC05 repair a -HD shorted cable at BLS end +7,11 which is in PS00 BLS Driver Hybrid was in backwards. This BLS cable was also tested and is OK. +7,21 which is in PS08 BLS Driver Hybird was in backwards. This BLS Cable was also tested and is OK. Modify the Term-Attn-Brds for eta -1:-4 phi 17 and phi 31 so that these 8 Trigger Towers have 470 pFd series capacitors in the input "T" network for both the EM and HD channels. Bob will compare the pedestal widths of these channels with their widths before this change was made. Meetings with Dean, Marvin, Rick and Tom Regan about getting the TT's all working. Results: Victor and Ben can help with BLS cable repair. I'm to work with them on the next cable problem that we find. Tom and company will make a 48 channel Pulser Switch Box so that we can test the trigger pickoff section of BLS cards. We will use a slot in the 5k Test Stand to do this. Moving the TT debugging files to: www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/trig_tower/ For now these files are: bls_rack_map.txt Just shows the location of the racks in the platform. bls_work_list.txt As we identify BLS cards that need work they go on this list. tt_repair_procedure.txt Description of how to diagnose and repair a Trigger Tower. disconnected_tt.txt The official list of BLS cables that are not plugged into the L1 Cal Trig. excluded_trigger_towers.txt The official list of TT's that have been excluded by TRICS. next_access_tt_work_list.txt List of what to do during the next access. trigger_tower_repair_log.txt The chronological log of the debug and repair work that was done to each TT. I have salvaged what information I could from the previous debugging work. There was not very much information that made any sense or was even self consistent. That means that some entries in the "next_access_tt_work_list" may not be correct (I have filtered out the obvious garbage) and that I'm just starting completely over with the "trigger_tower_repair_log". ------------------------------------------------------------------------------ DATE: 25:27-SEPT-2002 At: Fermi Topics: L1_Acpt Timing Change for TFW and L1 Cal Trig, Test the new prescaler, Master Clock verify BC REF, VME Access vs TRICS Serail DAC Programming, Obey_L2, 16x CTFE Wednesday early AM moved the timing of the L1_Acpt later by 2 ticks. Put clk_sequencer_1_11APR02.txt into obsolete_files Move clk_sequencer_1_18SEPT02.txt from test_files into /master_clock and load it into Sequencer #1. This moves the First BX in Super Bunch and the Last BX in Super Bunch and the Liver Crossings in the Cosmic Gap And-Or Terms to their new locations. Verify that these have moved and are correct by using one of them for a trigger and seeing where the L1 Accept is issued. The new EXO files that will be used are the following: Spread = 35 Spread = 37 FPGA Version Version Installed Locations -------------- ----------- ----------- ---------------------------- TTS _16_1 _17_3 M123B Slot 21 Site 1:16 L1_TRM _6_1 _7_1 M123T Slots: 2,3,9,10,16,17 M123B Slots: 2,3,5,6 Sites 1:16 SCL_Helper _7_1 _8_1 M122B Slot 21 Site 13 L2_Helper _17_1 _18_1 M122B Slot 20 Site 4 CT_Read_Helper _10_1 _14_1 M101M Slot 21 Site 4 Tied the CMC front panel D-Zero BOT marker up to the logic analyzer. It is at Cur BX 9a L1 BX 77 i.e. a spread of 35. Measure this again after all the changes and it is not at Cur BX 9a L1 BX 75 i.e. a spread of 37. Look at the TRM FIFO Depth: L1 Cal Trig now 7,8 after all changes 9,19 Dean now 19 after all changes 21 L0 Rich now 18,19 after all changes 20,21 Muon now 0,1 after all changes various 1 through 4 Trigger on BOT. With all current FPGA's it fires on L1_BX 01. Swap just SCL Helper and it fires on L1 BX 03 Swap TTS and now it fires on 01. The spread is 37. Test the Tick Selects and they are OK. Verify that triggering from: BOT, Tick_sel #3, First in SB, Last in SB, Live BX in Cosmic Gap, Live Accelerator BX are all OK. Observed 29 of the 36 with no errors. Watch about 75 L2_Decisions to verify that the new L2_Helper is correct. Edit : CT_Readout_Helper.dci fomppl_miguel.dci l1_tdm.dci L2_Helper.dci SCL_Helper.dci TTS.dci And now a full Configuration of the 1,634 FPGA's in the TFW to prove that it will deadstart OK. Edit the Boot_Auxi.mcf to add Send_Msg_To_Self: "TrgMgr_Time_Zone_Spread 37" Michael check the Exposure Group Per Bunch scalers and they now look OK. Verified that the Foreign PBS still look OK. Wednesday 4PM Meeting with Daniel Major effort on Wednesday to get the L1 Cal Trig to readout the correct data for all BX in a super bunch. The CT_Readout_Helper_11_1 did not work with the L1_Acpt delayed by 2 ticks. It needed a LookBack constant of 25 i.e. lookback 7 for the first 10 BX in a super bunch and a LookBack constant of 24 i.e. lookback 8 for the last two BX in a super bunch. It finally makes sense that with the L1_Acpt delayed by two BX what we need to do is to delay it by 1 more to keep it in the same spot wrt the 396 L1 Cal Trig & ERPB clocking. I was trying to save it 2 ticks delay in the CT_Readout_Helper but that did not work. So instead delay it by 1 tick. Now you can readout the correct Cal Trig data for all BX with the LookBack constant of 24. So we are using CT_Read_Helper_14_1.exo and have edited Init_Post_Auxi_L1CT.rio to have the last value set in the Manual Control Register be $0078. It had been $0079. This is what controls the LookBack constant alone with other stuff in the ERPB's. Details are in FPGA log book #5 on pages starting at 185. CT_Read_Helper_11_1 _12_1 and _13_1 are all junk. Tested this in the normal way of using the hand pulser and adjusting its timing wrt the BOT so that we test all 12 BX in the first super bunch to verify that the L1 Cal Trig asserts its AOT's for the correct ticks and reads out data from the correct ticks. All 12 BX were tested and look OK in both respects. AOT's are centered on the correct BX, i.e. asserted for ticks 6,7,8. Also verified that when the French pulser was set for tick 10, that the Cal Trig issued AOT's for tick 10 and that the Precision Cal Readout looked OK and reported that it came from tick 10 and that the L1 Cal Trig readout looked OK. Thursday afternoon test of the new pseudo random prescaler. This is TDM_25_2 and it ran with TRICS V10.2 A There were DAQ problems at the time but basically the prescaler appears to be fine. There may be an issue of +-1 count of what gets loaded into the comparator ref value but this effects it operation only at the two limits of 0000 and ffff. After the test return to TDM_24_1 and TRICS 10.1 B Friday during store. Now that we are running clk_sequencer_1_18SEPT02.txt we have a BC_REF signal. BC_REF is visible on a front panel Lemo and it runs the "phase comparator" that can watch the timing of the real BX vs this CMC generated signal and issue an alarm if they are apart. I checked the relative timing of PD and BC_REF and found that the center of PD is about 38.4 ns before the leading (falling) edge of BC_REF. So I should move BC_REF about 2 RF buckets earlier. Another big discovery this week is the difference in the length of time that is required to program the Term-Attn-Brd DAC's via VME Access vs TRICS. It takes VME Access about 70 seconds to do 6 racks of either Pedestals or Gains. It takes TRICS 4 seconds for either. Head scratch. Ah the difference is the way that VME Access uses the Bit_3 vs how TRICS uses it. But there may be a problem. When doing an ititial setup after power was off, a couple ot TT's did not program correctly. The one that I know of that did not program correctly are: eta -2, -3, -4 phi 25 HD. This is very strange. I assume it is a problem with that card and not a problem with the fast programming. So at the next opportunity, program fast using TRICS look at the result and then do it with VME Access and check again. Want to verify that fast is OK and fix any problems with using fast. Note the fast time using TRICS is not far off from the original 2 sec for the whole system calculation - and we know that we could make it faster by doing a whole string at once. So although this is not important now, in the long run we can think about putting it back DAC setup into the Initialize process. Need to make sure that Find-DAC is still OK, i.e. test it. 16 CTFE cards came back from SiDet. This makes a total of 136 CTFE cards to be used to populate the last 4 racks. See 21:23-Aug-02 for the details of the first 120 that came back from SiDet. They still have the dremel tool. Gave timing change report to the Friday operations meeting. Important Note: Remember, currently, anytime after a manual TFW Initialize the TFW will be set to not Obey_L2. So you need to remember to manaual set it to Obey_L2 (the state that you most likely want). The good abstract algebra book is "Abstract Algebra and solutions by radicals" by Maxfield and Maxfield. ------------------------------------------------------------------------------ DATE: 18:20-SEPT-2002 At: Fermi Topics: Installed Trics V10.1.B L1CT PROM run on full coverage (single page) Prescaler Meeting, work on CTFE Install Trics V10.1 Rev B cf. www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/000_trics_ii_revision_notes.txt Summary of important new features: + Catch up with VME_Access features: - Event dump updated for VBD->SBC changes - Execute TTI files to load Gain and Pedestal - Find_DAC (but probably still want to continue using VME_Access) + New PROM checker with selection of test coverage + Now executes Boot_Auxi.mcf once at startup + Change default/initial coverage to eta -12:+12 + Switch to most recent ITC v02-18-03 Tested Px and Py Prom for Page #0 for TTeta(-12:+12) TTphi(1:32) Px (-1,24) \ These towers are all on the same CTFE. Px (-2,24) | In common= CTFE summer/driver, CAT2 operand/receiver. Px (-3,24) | One or a few bits intermitently wrong; mostly bit(256) Px (-4,24) / Note that the eta=-2 test produced a fixed output Px (+5,2) \ Output is twice the input (NOT twice the intended output) Py (+5,2) / Output same as input (instead of long steps for sin(phi)~1) Guess: problem could be wire selecting 8/9 bit vs 4/8 pages wild guess: energy PROM instead of momentum PROM Py (-5,25) Zero for all inputs. Guess: PROM blank, pin missed socket, backwards, etc Px (+11,9) The tests claims the PROM says 7 everywhere but this really only means the test finds the same value everywhere, and asumes it is 7. The initial 4xTT sum for input=0 is found low by 7 counts. This means the response of this Px prom for input=0 which should be output=7 (i.e. cos(phi) is small) is in fact zero and remains zero for all inputs. Px (- 9,29) \ These towers are all on the same CTFE. Px (-10,29) | In common= CTFE summer/driver, CAT2 operand/receiver. Px (-11,29) | Bit of value 16 is always ON. Px (-12,29) / Tested EM and HD Prom for Page #7 for TTeta(-12:+12) TTphi(1:32) Zero Problem detected. Improvements noted to be made to PROM test code Add explicit "Done" screen message to signal end of test Add a red message to repeat the tower coordinates after after PROM has failed Put loop on eta before loop on phi, which will test channels on a CTFE together Meeting with Michael and Ron about the TFW PreScaler and Exposed Luminosity Calculation. Recall the goals: Make absolutely certain that we can calculate the Exposed Luminosity for each L1 Trigger. Make the PreScaler knob more convienient to use. Current problems with the PreScaler include: Magic prescale values that you need to stay away from: 3, 53, ... The prescaler beats against the beam structure, i.e. phase locked to the accelerator. The prescalers can make the L1 Triggers "shadow" each other, i.e. the prescalers are phase locked to each other. New points discovered during the meeting: The formula DeCorrelated Enable x SUM over Exposed is wrong for the Zero_Bias and Min_Bias triggers by the amount of deadtime that these triggers introduce into the system. Prescale counter moves only when the trigger is enabled, does this fix everything ? or does it just make another luminosity dependent bias problem. For normal triggers (i.e. triggers that use a L1 Muon or L1 Cal Trig Term) given a totally random stream of 1's and 0's from the prescaler, is the effect of "normal natural unbiased" shaddowing all taken care of the the SUM over Exposed part of the standard formula ? For normal triggers, compared to a prescaler that makes a fully random stream of 1's and 0's how much of an error is caused by using a "skip every Kth" straight count down prescaler, i.e. break the phase lock but still just enable every "Pth" BX ? Yes, it gives even exposure to all ticks, but it is not random. Modified the DTACK* circuit on the TOM card that hold the SCL in the DAVE L3 Interface Crate. This delays the DTACK signal coming from the THE-Cards to the SBC. The details are in the DAVE section of the TFW FPGA notebook. Relpace the cooked choke on CTFE 212 and the cooked serial data cable. It is ready to try using again Trigger Tower repair work on the platform during an access. +5,20 and +6,20 both EM and HD At the BLS end the cable was not plugged in. -11,21 and -12,21 both EM and HD At the BLS end the cable was plugged into the wrong connector. +11,31 and +12,31 both EM and HD At the BLS end the cable was not plugged in because of a bent pin. ------------------------------------------------------------------------------ DATE: 11:13-SEPT-2002 At: Fermi Topics: Work on Cal Trig, Survey SMT readout noise pickup, DAVE VME vs SBC Tundra problem VRBC SCLR problem, HubController to Ted, Unplug yet another TT. Script for moving to BX to L1_Acpt Spread to 37 Spread = 35 Spread = 37 FPGA Version Version -------------- ----------- ----------- TTS _16_1 _17_3 L1_TRM _6_1 _7_1 SCL_Helper _7_1 _8_1 L2_Helper _17_1 _18_1 L2_Helper_Save series CT_Read_Helper _10_1 _11_1 Things that need to change & what to verify: Alignment of the Exposure Groupe per Bunch Scalers and the Foreign per Bunch Scalars. See the log book entry for 19:21-SEPT-2001 the annotation from 8-OCT-2001. Alignment of the CMC directly generated And-Or Terms, i.e. AOIT's TL20 Tick 43,57,96,110 first last Cosmic Gap AOIT #241 TL21 First Interaction in Super Bunch AOIT #249 TL22 Last Interaction in Super Bunch AOIT #250 See 8:10-AUG-2001 and note that I do not think that some of the comments are correct. Increasing the value of the positive offset means that it takes longer for the CMC to output this signal and thus there is less setup time in the L1_TRM for this direct in AOIT. Verifying the change: See the log book entry from 12:16-JUNE-01 for details. Fire on the BOT AOIT then swap just the SCL_Helper and see that the move is correct. Check AOIT TRM FIFO Depth before and after. Put the CMC BOT into the logic analyzer before and after. Try just the L1_TRM and see how much things change in the AOT FIFO Depth Analyzer. Try the Tick and Turn Scaler. Checkubg just the Current vs L1 BX numbers on the SCL Receiver. Check that the Tick Selects are still working. To check the SCL Helper do the following. Change just it, run a trig based on one of the markers, e.g. BOT and see where it fires. The log book entry from 21:23-AUG-2002 which has a review of the currently in use parts (i.e. spread of 35 parts). The other TFW FPGA change that we need to make permanent is the FOMpp that makes the much longer, but just two instances of, Skip_Next_N. The FOM++ that makes the Skip_Next_N signals is Crate M123 Mid Slot 16 FPGA Site 11. This fpga site should start to be configured with FOMppl_4_4. Let's configure just this site with the new FOMpp design. See the log book for: 27:30-AUG-2002. Make a Find_DAC Run on Wednesday. Compare this with the August 28th run. Make this the file to load at Cal Trig dead start. Change the sign. \D0_Config\Find_DAC_V3_1_H_20020911.tti;1 \D0_Config\Run_II_L1CT_Bob_4_Gain.tti Survey of Noise Induced into the Trigger Tower Signals by SMT Readout This noise starts around 8.5 usec after the L1_Acpt and lasts until about 16 usec after the L1_Acpt. Often there is a smaller but visible burst of noise at about 3.6 usec after L1_Acpt. HD channels typically have 2 or 3 times more noise than EM channels. The noise is basically everywhere. This was done looking at the CTFE Lemo test outputs. TT eta -1 Some of the HD channels show a little bit of the SMT pickup. Amplitude is 20 to 50 mVpp. Phi 8 is one of the channels with the most pickup. Phi 17:24 have none. All the EM channels show a dip of 10 to 20 mV at about the same time as the SMT noise. The dip starts at about 12 usec after the L1_Acpt and the dip is over by about 26 usec after the L1_Acpt. TT eta -2 Can see a little bit of SMT noise pickup in most HD channels in the phi range 1:8 and 25:32. Can not see any SMT pick up noise in phi 9:24 HD. The EM channels just show the little dip as at eta -1. TT eta -3 Can see SMT pickup in just a few HD channels, e.g. phi 8, 9, 10, 27, 28, 29. The EM channels just show the little dip as at eta -1. TT eta -4 Can see the SMT pickup in some HD channels. Can see it at Phi 2, 4, 6, 7, 8, 9, 10, 27, 28, 29, 30, 31, 32 The EM channels just show the little dip as at eta -1. TT eta -5 I can just barely see the noise on one channel phi 24 HD. Can not see the SMT noise on any EM channels - you can just barely see the dip. TT eta -6 You can see it on all 32 HD channels. Phi 8 is worst, 150 mVpp. Can not see it on any eta -6 EM channels. TT eta -7 All 32 HD channels have it, typically between 50 and 100 mVpp. Phi 9 and 10 are worst with 200 mVpp Phi 7, 8, 24 are examples of 100 mVpp. You can just barely see it on some EM channels 10 20 mVpp. Examples of the channels that you can just see it on are phi 8, 22, 23, 24, 25, 26, 31. TT eta -8 Can see it on all 32 HD channels. Phi 9 is worst 200 mVpp. Other channels with a lot are phi 5, 24, 25 all with about 100 mVpp. You can see it on all 32 EM channels. On many EM channels it is pretty small 20 mVpp. Phi's 9 and 24 have the most in the range of 50 mVpp TT eta -9 Can see it in all the HD channels. Phi 9 and 10 are worst and it is about 200 mVpp. It is small in the EM channels but it is basically in all 32 of the channels. TT eta -10 Can see it in all the HD channels. Phi 9 is worst with an amplitude of 200 mVpp. It is small, sometimes very small but it is in almost all the channels. TT eta -11 Can see it in all 32 HD channels. Phi 9 and 12 are worst. Phi 12 is 400 mVpp. Can see it in 9, 10, 22, 23 Is probably there in some others a very low level. TT eta -12 Can see it in all 32 Phi. 9 and 10 are worst 150 to 200 mVpp. Not very clear in any channels. It is most likely there in 22, 23, 24. Scope Pictures taken will making the above survey. Disk 1 file 0 -1,8 EM yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -1,8 EM CTFE Lemo 10 usec/div Disk 1 file 1 -1,8 HD yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -1,8 HD CTFE Lemo 10 usec/div Disk 1 file 2 -9,10 HD yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -9,10 HD CTFE Lemo 10 usec/div Disk 1 file 3 -9,10 HD yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -8,9 HD CTFE Lemo 10 usec/div Disk 1 file 4 -9,10 HD yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -7,7 HD CTFE Lemo 2 usec/div Disk 1 file 5 -9,10 HD yellow is L1_Acpt Blue-Pink are -8,8 HD raw BLS signals Green is -7,7 HD CTFE Lemo 400 nsec/div While looking at all these Trigger Tower signals to survey for SMT pickup noise I noticed that channel -6,19 HD is a channel with a problem. It has about 75 mV of noise that is there all the time. It is not SMT pickup. UnPlug yet another Trigger Tower. Thursday about 17:45 UnPlug +5,23 because its EM was running at a high rate. Send a note to Bob and Daniel. Wednesday late afternoon Doug came to see me because the SBC in the RM crate was periodically hanging while trying to do VME cycles with the DAVE THE-Cards in that crate. What you would see is that the Center LED in the 2nd row on the TOM was ON and the VME Board LED was ON. Looking at pins 33 = AS* and 34 = DTACK* on the TOM showed that AS* was asserted and that DTACK* was not asserted. OK, for some reason the THE-Card recognized that it was being addresses, i.e. that a VME cycle was underway to it, but it never DTACKed. So either the slot #1 Controller should have "Timed Out" the cycle by asserting Bus_Error or else the SBC Master should have done this. I know that the slot #1 Controller, i.e. the Vertical Interconnect Slave, is doing the arbitration of Bus Mastership, so I think it is also supposed to time out broken cycles. We did this test a number of times and it always hung on the THE-Card in slot 9. Typically it would hang after Doug executed the "init routine" about 5 or 6 times. So we swapped the cards in slots 7 and 9. It still hung on the card in slot 9 --> its not a problem with the card. So we moved the card in slot 9 to slot 20 (leave its address switch unchanged). Now after Doug executed the "init routine" about 20 times the card in slot 7 hung in the standard way. So its not the slot. Its not clear what the problem is. The one think that I did notice is that the rock in TOM (that in this case is used to generate the P1_TS_0 is 12 MHz and not the standard 50 MHz. So the VME cycles on the THE-Cards in this crate are going to be very slow. If Doug does something to waste time between each VME cycle (e.g. puts in a print statment) then the system never hangs. So individual cycles must always complete OK. The problem must has something to do with how long it takes the THE-Card VME IF to "cool down" at the conclusion of cycle N before it is ready to start cycle N+1. We have never see this problem with TCC but it is both running slower cycles Bit3 --> Vertical_Interconnect and all the rest of the crates run at 53 MHz. Is there a reason why this crate was at 12 MHz ? The other problem is why didn't this cycle time out, or is there a problem with the way that the SBC handles cycles that terminate with a time out ? I checked to verify how the timing in the RM DAVE crate works. It uses normal CMC 53 MHz to run the VME interface state engine and it uses normal CMC BX Clock as its basic clock in the DAVE logic. So everything is normal here. My guess remains that the SBC Tundra just starts the N+1 cycle so close to the end of the Nth cycle that the THE-Card VME IF gets into trouble. The other possible issue is that the SBC Tundra is running on a TOM "extension board". Friday 4x SCL Receivers to Ted and the spare SCL Hub Controller SN# 010 to Ted. Also got to talk with him about the VRBC support and the hangs that this card sometimes has. Brought 2.49 K Ohm 1206 SMD to Fermi for Term-Attn-Brd repair. ------------------------------------------------------------------------------ DATE: 4:6-SEPT-2002 At: Fermi Topics: Work on Cal Trig, Test TRICS, SCL cables, Bob pulled the following 2 TT's Wednesday morning. It's not clear how noisy they are but they were the noisiest ones that they could find with the examine during the previous store. +6,23 EM and -8,8 EM The complaint was that the rates were fluctuating. Spent all Thursday afternoon looking at SMT induced noise. What I was trying to do was understand what was wrong with -8,8 EM. Nirmalya and I started by focusing on the wrong BLS card. The lessen here is that until we get better at translating Cal Trig Eta,Phi Index into precision cal coordinates we need to manually check that we have the correct BLS. I.E. turn off BLS power, pull the BLS that we think we should be working on, turn the BLS power back on, and verify that there is no signal at the Cal Trig End. This work was during global zero bias running. There was noise on basically all the TT's at eta -7 and down. Because of this noise it was not possible to look at any "low level" noise problem that -8,8 may have. Lessens: it is hard to debug noise problems during global zero bias running and I absolutely must map out and characterise the SMT induced noise. Basically nothing was learned about -8,8 and nothing was learned about the SMT noise except that there is a lot of it. Talked with Victor Martinez about the LMR-100 SMA MCX patch cords for which I gave him the parts 2 weeks ago. He will have time to make them soon. I let him know that Daniel will be contacting him about repairing the 2 LMR-200 cables on the 2nd floor MCH. As of Tuesday or Wednesday of this week, Daniel is officially back with us for the next 3 months. So to dead start the Cal Trig, the current files to use with VME_Access are: \D0_Config\Find_DAC_V3_1_H_20020828.tti;1 \D0_Config\Run_II_L1CT_Bob_4_Gain.tti Test of TRICS 10.1-A PROM Checker. TRICS 10.1-A running for about 1 hour Thursday afternoon with no problems that I saw. People were running triggers in the TFW and I played with the Cal Trig checking PROM's. I checked a couple of random EM and HD PROM's and then focused on Px and Py. At fixed phi's of 9 and 31 I checked both the Px and Py PROM's for all 24 installed eta's. At fixed eta of +11 I checked all 32 phi's of Px. At fixed eta of -7 I checked all 32 phi's of Py. The only problem is with the Px PROM at +11,9 which looks completely sick. Perhas it is in the socet wrong. You can verify that the PROM Checker can find problems, by telling it to test a page other than the page that the hardware is pointing to. Note that because the CAT2's are only clocked for the first lookup, you do not need to do any thing to lock down on a page, rather the only data that the PROM Checker program sees is from the first lookup. Brought 84R5 Ohm 1206 SMD to Fermi for Term-Attn-Brd repair. Order cutters to clip Term-Attn-Brd pins. ------------------------------------------------------------------------------ DATE: 27:30-AUG-2002 At: Fermi Topics: Work on Cal Trig, Master Clock, Long min space between L1_Acpts, FPGA's for spread 37 Bob spots in the calibration data that the BLS cables for eta -9:-12 phi's 5 and 6 were swapped at the L1 Cal Trig end. They are now plugged into the correct CTFE cards. The FOM++ that makes the Skip_Next_N signals is Crate M123 Mid Slot 16 FPGA Site 11. Its Register 128 is loaded with $0018 to tell it to output Skip_Next_N signals. Its Register 129 right now controls Skip_Next_0 and Skip_Next_1 and is loaded with $0012. Its Register 130 right now controls Skip_Next_2 and Skip_Next_3 and is loaded with $0000. Thursday morning configure FOMppl_4_4 into just site 11. Run it for a time with the standard $0012 loaded into Reg 129. $0012 is 18 which implies Skip 20, i.e. Skip 20 x 131.8 nsec = 2.6 usec. Then load $0104 = 260 which implies Skip 262, i.e. Skip 262 x 131.8 nsec = 34.5 usec. The operation looked as it should. I will leave FOMppl_4_4 configured at this site. Reg 129 has been returned to $0012. Recall that the register to control Skip_Next_N_0 is: M123 Mid Slot 16 Site 11 Reg 129 You skip 2 more ticks than the value in this Register. I have not edited the DCF to use FOMppl_4_4. If they dead start the TFW, then we are back to the standard version. Wednesday during the day all BLS cards were pulled out to work on the power supply filter that will fix the noise at L1_Acpt time problem. I think this was putting the correct value resistor into this RC filter, i.e. the value that Dean had designed to be there. Start Find_DAC Wednesday night. It runs from 21:40:22 to 00:16:13 which is a duration of 2:35:51. The results are in the file: \D0_Log\Find_DAC_V3_1_H_20020828.tti;1 This Find_DAC run was done with the "Bob_4" gains file loaded. Thursday morning load this new Ped file and the "Bob_4" gains files. The big question is, how many BLS channels have been broken and are now oscillating or making noise ?? Set up EM Ref Set 0 for 10.0 GeV and its Count Comparator 0 for => 1 TT. Set up Tot Et Ref Set 0 for 15.0 GeV and its Count Comparator 0 for => 1 TT. Watch rates: EM Hz 1.29 1.8 1.35 1.54 0.48 HD Hz 2.93 6.5 5.14 5.27 6.5 sec 31 31 110 310 31 Lower the Ref Sets Set up EM Ref Set 0 for 7.5 GeV and its Count Comparator 0 for => 1 TT. Set up Tot Et Ref Set 0 for 10.0 GeV and its Count Comparator 0 for => 1 TT. Watch rates: EM Hz 1.30 1.20 1.77 1.61 3.50 1.92 HD Hz 7.13 9.04 10.30 9.54 12.90 7.55 sec 21 134 108 217 186 42 Because of other things that needed to get done I did not do any more of this. But it was clear that I could "see" the rates change when the system was reading out vs when it was not reading out. But these are raw AOIT rates. So really need to map them onto the 36 live BX to know what is happening. Need to make a com file to set all all 8 Ref Sets and Count Comps of 1. Thursday morning excitement. SCL Hub-End had red LED flashing on the fanouts for 50:57 and 78:7F. 78:7F flashed red most often, once every 5 to 10 seconds. I think that every time that 50:57 flashed, 78:7F also flashed. This was about once every 30 seconds. I also saw the counter on the Master Clock rach flash to 999999 instead of its normal 1.00000 Common flashing in SCL Hub, and 99999 makes me think Master Clock problem. Steve came over and checked things out. Master Clock signals look OK on the scope. You can make the counter read either 1.00000 or 999999 by setting the threshold on the counter inputs to just the right point. When the counter get to automatically set its input thresholds then it always read 1.0000 So the Master Clock is happy. OK so it is a drift in the relative timing of the 53 MHz and the 7.5 MHz signals from the Master Clock to the SCL Hub-End. As it was running there was a 10" delay cable in the 7.5 MHz cable from the Master Clock to the SCL Hub-End. Increase this from a 10" delay cable to a 14" delay cable and now a bunch of SCL FanOuts have there red LEDs on. From previous notes this is what you would expect for additional delay in the 7.5 MHz. Then replace the 10" delay cable with a 5 3/4" delay cable. No more SCL FanOut red LED flashing and check the SCL data and it looks fine. Detailed notes about the previous adjustment of the phase between 53 and 7 MHz to the SCL Hub-End are in the log book 26:29-MAR-02. The numbers for Steve Chappa are: his office x3477 his secretary x4800 another person near his office Mark Larwill x3551 I think Mark may be his boss. Official meeting on Thursday to define the timing change. It will be 2 ticks, i.e. announce the L1_Acpt two ticks later. Note also that if L1 muon needs more time we can probably get them 50 or 60 nsec from the routing of their AOIT cable in the MCH-1. Have worked on the FPGA's to implement this shift of 2 ticks. SCL_Helper_8_1.exo is now on TCC1 and L2_Helper_18_1.exo (from the L2_Helper_Save series) is also on TCC1. ------------------------------------------------------------------------------ DATE: 29-AUG-2002 At: MSU Topics: Update L2 TCC's VNC access restrictions to allow access from our MSU machines Repeat the same operation as 24-AUG on L2 TCC to allow VNC access from tadpole, msul1a and desmo, but using L1 TCC as intermediate VNC step. Note when using a double VNC hop, the window contents are not well updated and it is sufficient to grab the top of the window and drag it by 1 mm to force an update. Note also that one should avoid using the "full-screen" mode when using a double-hop VNC connection, as this may have been the cause of a freeze of the VNC connection from MSU to L1 TCC and of the VNC server on L1 TCC. L2 TCC seemed to be not affected, but the VNC window on L1 TCC could not be closed even from L1 TCC's console and had to be killed using the Task Manager. Things return to normal afterwards. ------------------------------------------------------------------------------ DATE: 24-AUG-2002 At: MSU Topics: Update L1 TCC's VNC access restrictions to allow access from our MSU machines The L2RS application on L2 TCC most likely filled up the page file and caused the "Out of virtual memory" error at 4am. The L2 expert Marc Buehler called Daniel M. but never called Dan or Philippe. Daniel clicked/acknowledged the error messages, and Marc restarted L2RS around 5am, then caused himself a lot of grief when he decided to reboot some alpha administrator which then wouldn't reboot. Two hours of beam were lost. http://www-d0.fnal.gov/~d0run/d0_private/operations/downtime/downtime.html We could no longer VNC from MSU to L1 TCC because the IP addresses of our MSU nodes had changed from 35.8.* to 35.9.*. The VNC server on L1 & L2 TCC require that the IP address of the client be either 131.225.* (i.e. fnal) or desmo, msul1a, or tadpole. Philippe was able to VNC (via ssh tunnel) to d0ntmsu7 then VNC from d0ntmsu7 to d0tcc1 and use C:\winnt\system32\regedt32.exe to modify the registry key: HKEY_LOCAL_MACHINE/SOFTWARE/ORL/WinVNC3:AuthHosts of type REG_SZ to "-:+131.225:35.9.71.12:35.9.71.15:35.9.71.152" After this change the VNC server was remotely stopped via the VNC connection and restarted by a shifter via start|Programs|vnc|Administrative Tools|Start WinVNC Service. Note that the Fnal address window could possibly be tightened to something in the range 131.225.224-227 ------------------------------------------------------------------------------ DATE: 21:23-AUG-2002 At: Fermi Topics: Work on Cal Trig, Check FPGA Versions, Parts back from SiDet, Check Power Supplies Current non Cal Trig job list includes: "fix" the prescaler, time change of increasing the spread by 2 ticks, Skip_Next_"N" change from 8 bit ot 16 bit. Moving the spread now involves: Version FPGA FPGA Log Book Currently in Use -------------- ----------------- ----------------- TTS pg 257 17-Jan-02 _16_1 L1_TRM pg 209 7-June-01 _6_1 SCL_Helper pg 209 7-June-01 _7_1 L2_Helper pg 283 1-July-02 _17_1 CT_Read_Helper pg 293 1-Aug-02 _10_1 On Becane_Too add xhost kepler and desmo - add to Becane_Too log book. Checked +10,23 +12,4 +12,6 +12,8 All except +12,6 do have correct resistors installed at R80. So maked a "Bob_3" gains file that cranks up the 3 TT's with correct R80 by the standard factor of 1.45 This makes a tota of 55 EM TT's in the eta 5:12 range that have the correct R80 and that we have now cranked the gain back up on. The "rectangle" in eta phi that is still unplugged because of what was a bad BLS supply is: eta -7:-12 phi 9 and eta -7:-10 phi 10. See the log book entry for 9:13-July-2002 for details. Now make a Find_DAC run. It finds a pedestal for all TT's. This file is \D0_Log\Find_DAC_V3_1_H_20020821.tti;1 Then on Thursday, per conversation with Bob, for both eta +7 and -7, and for both EM and Had, decreases the gain so that it is 2/3 of the value that we have been running. This new gain file is "Bob_4". The pedestals for eta +-7 still look OK in the TT_ADC_Monit display so I have not done a new FIND_DAC run. Any store starting after 18:00 Thursday will have this new gains file. So to dead start the system, the current files to use with VME_Access are: \D0_Log\Find_DAC_V3_1_H_20020821.tti;1 \D0_Config\Run_II_L1CT_Bob_4_Gain.tti Daniel brings back more CTFE's from SiDet. So have he has brought back: 29, 27, 32, and 32 which is 120. There are still 15 more CTFE at SiDet. We are storing these out on the sidewalk. He also brough back a box full of cleaned and erased PROM's. Daniel checked 3 Cal Trig Power Pans from the from the spare supplies cabinet. These had not been run in many years so they were brought up on the 3 phase variac first. The supplies tested are: Tier 1 PDM-12 Tier 1 PDM-19 Tier 2,3 MM-8 The spare power pan cabinet also has Tier 2,3 MM-7 which was tested on 10-JULY-02. So we 2 tested Tier 1 Power Pans and 2 tested Tier 2,3 Power Pans in the storage cabinet. Need to bring a set screw for the input terminal strip on the MM-8 power pan. From Bob. Here's the list in eta,phi of bad towers with the specific problem that they see about 50% of the energy of other towers at their same eta (but different phi). EM 1,-30 EM 5,-3 EM 11,-14 EM 1,-30 HD 1,-4 HD 2,-5 HD 3,-7 HD 4,-7 HD 12,-22 We will start the individual TT debug on these 9 TT's. ------------------------------------------------------------------------------ DATE: 13-AUG-2002 At: Fermi Topics: Directors Review, Work on Cal Trig, Use the Philips RCL meter to look at the eta 5:20 Term-Attn-Brd's that have lower than normal gain on their even eta EM channels and thus may have the correct resistor installed at R80. Check the couple of channels from Bob's list from 2 weeks ago: -10,32 +10,32 +12,32 +8,32 +6,32 +6,9 -8,25 These all show the correct 84.5 Ohm resistor for R80. So ask Bob for the full list. He has 53 even eta EM TT's that he guesses may have correct R80's. I checked all 53 with the bridge and all but +10,21 had good R80's. In the standard L1 Cal Trig coordinate system, the 52 EM TT's that have correct value R80's and thus their gain was cranked up by a factor of 1.45 are the following: -6,6 +6,9 +6,17 +6,18 +6,19 +6,21 +6,22 +6,23 +6,32 -8,6 +8,17 -8,8 +8,18 +8,19 +8,20 +8,21 +8,23 +8,32 -10,1 +10,3 -10,3 +10,6 -10,7 +10,9 -10,15 +10,12 -10,18 +10,13 -10,20 +10,15 -10,21 +10,32 -10,22 -10,26 -10,28 -10,30 -10,32 -12,1 +12,2 -12,10 +12,12 -12,13 +12,13 -12,18 +12,15 -12,22 +12,16 -12,23 +12,32 -12,24 -12,26 -12,29 This new Gain File is called "Bob_2". Dean now has a full BLS crate with the power supply filtering (decoupling) setup to get rid of the bump at the time of the L1 SCA to L2 SCA transfer. In TT coordinates this is BLS crate covers: eta's +1:+4 at phi 6, eta's +1:+6 at phi 7, and eta's +1:+6 at phi 8. I checked some of these channels and they look much better. I ran out of time before checking all of them and writting down some quantitative information about the remaining small bumb. I need to do this next trip and get some scope pictures. During the Store that started Tuesday night Dean had to pull another BLS cable. It is -6,23 and the problem is EM7 the 4th EM layer. It makes about 10 GeV pulses at rates up to kHz. This shows up in both the Cal Trig readout and the Precision Cal readout - so the problem is probably preamp. It looks like the pedestal shifts on the BLS cards caused by L1_Acpt's and L2_Decisions can be fixed on the BLS cards themselves and thus we most likely will not be changing the coupling capacitors on the Term-Attn-Brd's. Thus there is no reason to wait on fixing the wrong value R80 resistors on the Term-Attn-Brd's of the type for eta 5:20. So bring back to MSU the Q = 182 eta 5:20 Term-Attn-Brd's so that they can go back to Hughes electronics to fix their R80's. ------------------------------------------------------------------------------ DATE: 7-AUG-2002 At: Fermi Topics: More ADC_Clk Timing Numbers These are more ADC_Clk timing numbers from Joe. We had stable beam all day yesterday, and I spent a lot of time with the scope. Here the list of measurments for you. I did +3,24 EM and HD and -3,5 and -3,24 EM. The list format is a little different, but I didn't want to type the numbers twice. This is how I read the numbers into my analysis program. eta phi EM/HD Pk wrt wrt (0/1) Volt ADC BX 3 24 0 500 -8 732 3 24 0 550 -6 732 3 24 0 500 0 732 3 24 0 400 0 730 3 24 0 450 -10 732 3 24 0 500 -12 730 3 24 0 400 -6 732 3 24 0 500 -10 730 3 24 0 450 -4 732 3 24 0 450 0 730 3 24 0 1000 -8 730 3 24 0 400 -6 732 3 24 0 500 -12 732 3 24 0 500 -6 732 3 24 0 600 -8 732 3 24 0 400 -4 732 3 24 0 600 -6 732 3 24 0 500 -2 732 3 24 0 400 -8 730 3 24 0 800 -8 730 3 24 1 550 68 730 3 24 1 500 74 732 3 24 1 600 52 730 3 24 1 500 78 730 3 24 1 500 74 730 3 24 1 450 42 730 3 24 1 400 86 732 3 24 1 400 70 732 3 24 1 400 28 732 3 24 1 900 62 730 3 24 1 550 36 730 3 24 1 450 72 732 3 24 1 500 72 732 3 24 1 650 76 730 3 24 1 400 56 732 3 24 1 350 22 728 3 24 1 400 80 730 3 24 1 350 68 730 3 24 1 400 66 730 3 24 1 350 82 730 -3 5 0 1000 -10 720 -3 5 0 550 12 720 -3 5 0 600 -2 720 -3 5 0 500 8 718 -3 5 0 400 -10 720 -3 5 0 400 0 718 -3 5 0 1250 -2 720 -3 5 0 450 -6 720 -3 5 0 650 0 720 -3 5 0 700 4 720 -3 5 0 500 8 718 -3 5 0 550 8 718 -3 5 0 500 6 718 -3 5 0 450 6 718 -3 5 0 400 8 720 -3 5 0 450 0 720 -3 5 0 550 4 718 -3 5 0 550 4 720 -3 5 0 400 -4 720 -3 5 0 450 8 718 -3 24 0 400 -2 724 -3 24 0 500 -8 726 -3 24 0 500 0 724 -3 24 0 700 -8 726 -3 24 0 800 -4 724 -3 24 0 600 6 726 -3 24 0 500 4 726 -3 24 0 450 -14 726 -3 24 0 500 2 724 -3 24 0 700 -4 726 -3 24 0 350 -6 724 -3 24 0 550 -6 724 -3 24 0 1100 -6 724 -3 24 0 400 -8 726 -3 24 0 500 -10 724 -3 24 0 600 -8 726 -3 24 0 600 -6 724 -3 24 0 400 0 726 -3 24 0 550 -8 724 -3 24 0 700 -4 724 -3 24 0 400 -8 724 ------------------------------------------------------------------------------ DATE: 31-JULY, 1,2-AUG-2002 At: Fermi Topics: Work on Cal Trig, Work on and Check Master Clock timing, Cal Trig VRBC SCL Receiver, Check more TT's, eta 5:20 Term_Attn Brd news, Move Cal Trig ADC_Clk Work on the Master Clock Rack: Pull out the upper NIM bin and install the LeCroy Scope. This also gave us a chance to remove the old no longer used NIM And-Or Term inputs. We did have to save the NIM stuff that feeds Forward Proton and the L1_Acpt signal to the 3rd floor - this stuff is now in the lower NIM crate along with the modules that supply TeV RF and Sync to the PCC. The line cord to the Power Distribution box was cleaned up and the slack is now properly tied up and a proper housing is on the connector. The lemo cables to trip the power distribution are now setup properly and this was all tested including testing the smoke detector. Got labels on the Power Distribution box switches. The clock powered back up and downloaded without trouble. The pulser for CFT is now plugged into the back and not into the instrument outlets on the front panel. The upper NIM bin from the Master Clock rack is now a spare NIM bin for the Master Clock and is labeled and on the 6th floor. Update the instructions for power control and downloading of the Master Clock. Update this on the web and in the printed shifters folder. Check the Master Clock timing vs PD. It is 166 nsec plus 2x 396 nsec. This is fine. Previous check was 19:25-JULY-2002 and before that 19:21-JUNE-02. The RMI for M101 Cal Trig and the power supply for the TCC flat screen display are now plugged into a non-switched outlet on the contactor box for M101. They no longer get power from the Master Clock Power Distribution box. Edit www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/rack_crate/ power_panel_and_contactor_boxes.txt to indicate these new connection from the M101 Contactor Box. Reinhard needed the SCL cables for GS $24 and $25 brought to life but I do not have any more of the SCL Fanout to Patch Panel patch cords nor do I yet have the cable parts to make more. So for now we are using the patch cord for GS $0b to feed the long cable for GS $24 and the patch cord for GS $0c to feed GS $25. This is OK for now because there are no long cables running from the patch panel for either GS $0b or $0c. So I need to get more patch cords and at some point run more long cables from the patch panel to the L2 test stand for GS $ob $oc $od. Thursday afternoon have had a couple of incidents of the VRBC in the L1 Cal Trig loosing SCL lock. It comes back OK with a VRBC Init. But then (as normal) some one pushed the VME System Reset on the slot 1 Vertical Interconnect. I have now tried power cycling the crate to see if that will get it back to a normal happy condition. It failed again. End up swapping the SCL Receivers in the VRBC. After that it lost lock one more time and then started running OK. I do not actually think it was an SCL Receiver problem. The original one had a GND jumper installed - the new one does not. I have put the old one in the OK box. I should try a shorter coax on this run and see if it helps. Friday afternoon, re-configure the SCL Receiver FPGA in the L1 Cal Trig's VRBC with the June 2002 code from Ted. Move the L1 Cal Trig ADC Clock timing 56 nsec later. This involved changing Sequencer #2 from clk_sequencer_2_19JUN02.txt to clk_sequencer_2_1AUG02.txt changing the CT_Readout_Helper from _8_1.exo to _10_1.exo and edit the \DFC\CT_Readout_Helpe.dci so that it will use _10_1.exo The Sequencer #2 clk_sequencer_2_1AUG02.txt took a little extra work at the last minute because the location of the Sub-System Strobe and Gap had never been adjusted to fit the Run II Timing_&_Control Distribution that was installed about 5 weeks ago. Things have been running right on the edge. Now it is nice: Gap has about 94 nsec of setup and 38 nsec of hold, the AOT's from Counter Tree CAT3 have about 77 nsec of setup and 55 nsec of hold. Verified that the AOT's from the CAL Trig are seen by the TFW as asserted for one before the live BX, the live BX, and one after the live BX e.g. 6,7,8. Used the hand pulser and verified for all 12 BX in the first super bunch that the L1 Cal Trig was asserting its AOT's to cause the TFW to issue a L1_Acpt for the correct BX and that it was reading out to L3 the TT data from the correct BX. The lower Tier 1 crate in M104 (eta -1:-4) now shows that the falling edge of its ADC_Clk is about 730 nsec after the falling edge of the Master Clock BX marker. This is with a 16 nsec cable to the ADC_Clk and a 24 nsec cable to the Master Clock public BX Marker output. Before (using these cable lengths) it measured 668 nsec from the BX Marker to the ADC_Clk. This would indicate that the ADC_Clk is now 62 nsec later. I do not know what it does not show up as exactly 3 x 18.83 = 56.5 nsec. In CC TT's eta +-3 phi 5 and 24 would be good TT's to study timing on. Their signals look completely OK so the timing information that we get should be accurate. Measure some more TT signals during a store. The following table includes only the new data points taken this week. See the 19,20,22,23,24,25-JULY-2002 log book entry for a description of measurment cable lengths and such. The ADC_Clk is always after the BX Marker. If the ADC_Clk is before the peak of the input signal then this time is labeled with a "+". If the ADC_Clk is after the peak of the input signal then the time is labeled with a "-". ADC Input ADC Clk Falling Edge Peak ---------------------------- Eta,Phi EM/HD Amplitude WRT Input Peak WRT BX ------- ----- --------- -------------- ------------ -2,24 EM 600 mV -18 ns 730 ns -2,24 EM 650 mV -16 ns 730 ns -2,24 EM 600 mV -10 ns 730 ns -2,24 EM 450 mV 0 ns 730 ns -2,24 EM 550 mV -16 ns 730 ns -2,24 EM 700 mV -10 ns 730 ns -2,24 EM 450 mV 0 ns 732 ns -2,24 EM 550 mV -20 ns 730 ns +3,5 EM 400 mV -12 ns 720 ns +3,5 EM 300 mV -16 ns 720 ns +3,5 EM 450 mV +4 ns 722 ns +3,5 EM 500 mV +12 ns 722 ns +3,5 EM 450 mV +16 ns 722 ns +3,5 EM 450 mV +14 ns 720 ns +3,5 EM 1300 mV + 6 ns 722 ns +3,5 EM 450 mV -2 ns 722 ns +3,5 EM 550 mV 0 ns 722 ns +3,5 EM 600 mV +4 ns 722 ns +3,5 EM 600 mV 0 ns 720 ns +3,5 EM 650 mV +12 ns 722 ns +3,5 EM 1000 mV +6 ns 718 ns +3,5 EM 650 mV -8 ns 720 ns +3,5 EM 800 mV +2 ns 722 ns +3,5 EM 1000 mV +10 ns 720 ns +3,5 EM 650 mV +14 ns 720 ns +3,5 EM 600 mV 0 ns 720 ns +3,5 EM 700 mV +10 ns 722 ns +3,5 EM 600 mV 0 ns 720 ns +3,5 EM 900 mV +6 ns 722 ns +3,5 EM 600 mV +6 ns 720 ns +3,5 EM 700 mV 0 ns 722 ns +3,5 EM 950 mV +14 ns 722 ns Notes about the eta 5:20 Term_Attn_Brds Many of the eta 5:20 Term_Attn_Brds have the wrong resistor installed at R80 and thus cause the even eta EM signals to be screwed up. We are living with this by turning down the gain on these even eta EM channels. But Bob finds some of these channels with lower than normal signals. Could it be that these channels have the corect resistor installed at R80 ? Next week bring the impedance bridge and check these channels. Bob provided the following list of channels to check: Read low and thus may have the correct R80 resistor: -10,32 +10,32 +12,32 +8,32 +6,32 +6,9 -8,25 Read "normal" (i.e. high) and thus have the wrong resistor at R80: -10,31 +10,31 +8,31 +6,31 +6,8 +6,10 -8,24 -8,26 The other eta 5:20 Term_Attn_Brds news is that Dean may be able to take care of all the readout noise problems at the BLS end. In that case we can stay with the 0.47 uFd coupling caps. Thus the only thing that we would need fixed is the R80 resistor and we could immediately send the cards back to Hughes to get this done. Still Need to bring a 9V battery for the Fluke meter. The following is a full COOR load of the Global Physics Triggers. This was Global Cal Muon version ? Time Stamp 23-Jul-2002 15:53:53.825 EM Et RefSet #0 for TT Eta( -12:12) Phi( 1:32) Thresh= 1.50 GeV EM Et RefSet #1 for TT Eta( -12:12) Phi( 1:32) Thresh= 5.00 GeV EM Et RefSet #2 for TT Eta( -12:12) Phi( 1:32) Thresh= 10.00 GeV EM Et RefSet #3 for TT Eta( -12:12) Phi( 1:32) Thresh= 15.00 GeV TOT Et RefSet #0 for TT Eta( -12:12) Phi( 1:32) Thresh= 5.00 GeV TOT Et RefSet #1 for TT Eta( -12:12) Phi( 1:32) Thresh= 7.00 GeV TOT Et RefSet #2 for TT Eta( -12:12) Phi( 1:32) Thresh= 10.00 GeV TOT Et RefSet #3 for TT Eta( -12:12) Phi( 1:32) Thresh= 3.00 GeV EM Et RefSet #0 Comparator #0 Count Thresh= 2 EM Et RefSet #0 Comparator #1 Count Thresh= 3 EM Et RefSet #1 Comparator #0 Count Thresh= 1 EM Et RefSet #1 Comparator #1 Count Thresh= 2 EM Et RefSet #2 Comparator #0 Count Thresh= 1 EM Et RefSet #2 Comparator #1 Count Thresh= 2 EM Et RefSet #3 Comparator #0 Count Thresh= 1 TOT Et RefSet #0 Comparator #0 Count Thresh= 2 TOT Et RefSet #0 Comparator #1 Count Thresh= 3 TOT Et RefSet #0 Comparator #2 Count Thresh= 4 TOT Et RefSet #0 Comparator #3 Count Thresh= 1 TOT Et RefSet #1 Comparator #0 Count Thresh= 2 TOT Et RefSet #1 Comparator #1 Count Thresh= 4 TOT Et RefSet #1 Comparator #2 Count Thresh= 3 TOT Et RefSet #2 Comparator #0 Count Thresh= 2 TOT Et RefSet #3 Comparator #0 Count Thresh= 2 TOT Et RefSet #3 Comparator #1 Count Thresh= 1 Expo Group #0 Require And-Or Term(s) # 243 -247 255 Expo Group #0 Digitize Geo Sect(s) # 0:7 10:13 16 19 22:25 31:37 48:59 64:76 80:83 96:107 126:127 Expo Group #1 Require And-Or Term(s) # -221 243 -247 255 Expo Group #1 Digitize Geo Sect(s) # 0:7 10:13 16 19 22:25 31:37 48:59 64:76 80:83 96:107 126:127 Expo Group #2 Require And-Or Term(s) # -220 243 -247 255 Expo Group #2 Digitize Geo Sect(s) # 0:7 10:13 16 19 22:25 31:37 48:59 64:76 80:83 96:107 126:127 Expo Group #3 Require And-Or Term(s) # -220:-221 243 -247 255 Expo Group #3 Digitize Geo Sect(s) # 0:7 10:13 16 19 22:25 31:37 48:59 64:76 80:83 96:107 126:127 SpTrg #0 Follows Exposure Group #0 SpTrg #0 Require And-Or Term(s) # 217 243 -247 255 SpTrg #1 Follows Exposure Group #0 SpTrg #1 Require And-Or Term(s) # 243 -247 255 SpTrg #2 Follows Exposure Group #0 SpTrg #2 Require And-Or Term(s) # 128 243 -247 255 SpTrg #3 Follows Exposure Group #0 SpTrg #3 Require And-Or Term(s) # 132 243 -247 255 SpTrg #4 Follows Exposure Group #0 SpTrg #4 Require And-Or Term(s) # 129 243 -247 255 SpTrg #5 Follows Exposure Group #0 SpTrg #5 Require And-Or Term(s) # 129 243 -247 255 SpTrg #6 Follows Exposure Group #0 SpTrg #6 Require And-Or Term(s) # 129 136 243 -247 255 SpTrg #7 Follows Exposure Group #0 SpTrg #7 Require And-Or Term(s) # 133 243 -247 255 SpTrg #8 Follows Exposure Group #0 SpTrg #8 Require And-Or Term(s) # 133 243 -247 255 SpTrg #9 Follows Exposure Group #0 SpTrg #9 Require And-Or Term(s) # 130 243 -247 255 SpTrg #10 Follows Exposure Group #0 SpTrg #10 Require And-Or Term(s) # 130 243 -247 255 SpTrg #11 Follows Exposure Group #0 SpTrg #11 Require And-Or Term(s) # 130 133 243 -247 255 SpTrg #12 Follows Exposure Group #0 SpTrg #12 Require And-Or Term(s) # 130 136 243 -247 255 SpTrg #13 Follows Exposure Group #0 SpTrg #13 Require And-Or Term(s) # 130 137 243 -247 255 SpTrg #14 Follows Exposure Group #0 SpTrg #14 Require And-Or Term(s) # 130 138 243 -247 255 SpTrg #15 Follows Exposure Group #0 SpTrg #15 Require And-Or Term(s) # 131 137 243 -247 255 SpTrg #16 Follows Exposure Group #0 SpTrg #16 Require And-Or Term(s) # 134 243 -247 255 SpTrg #17 Follows Exposure Group #0 SpTrg #17 Require And-Or Term(s) # 131 243 -247 255 SpTrg #18 Follows Exposure Group #0 SpTrg #18 Require And-Or Term(s) # 139 243 -247 255 SpTrg #19 Follows Exposure Group #0 SpTrg #19 Require And-Or Term(s) # 139 243 -247 255 SpTrg #20 Follows Exposure Group #0 SpTrg #20 Require And-Or Term(s) # 139 243 -247 255 SpTrg #21 Follows Exposure Group #0 SpTrg #21 Require And-Or Term(s) # 139 243 -247 255 SpTrg #22 Follows Exposure Group #0 SpTrg #22 Require And-Or Term(s) # 136 243 -247 255 SpTrg #23 Follows Exposure Group #0 SpTrg #23 Require And-Or Term(s) # 136 243 -247 255 SpTrg #24 Follows Exposure Group #0 SpTrg #24 Require And-Or Term(s) # 140 243 -247 255 SpTrg #25 Follows Exposure Group #0 SpTrg #25 Require And-Or Term(s) # 144 243 -247 255 SpTrg #26 Follows Exposure Group #0 SpTrg #26 Require And-Or Term(s) # 141 243 -247 255 SpTrg #27 Follows Exposure Group #0 SpTrg #27 Require And-Or Term(s) # 139 148 243 -247 255 SpTrg #28 Follows Exposure Group #0 SpTrg #28 Require And-Or Term(s) # 145 243 -247 255 SpTrg #29 Follows Exposure Group #0 SpTrg #29 Require And-Or Term(s) # 80 217 243 -247 255 SpTrg #30 Follows Exposure Group #0 SpTrg #30 Require And-Or Term(s) # 81 217 243 -247 255 SpTrg #31 Follows Exposure Group #0 SpTrg #31 Require And-Or Term(s) # 82 217 243 -247 255 SpTrg #32 Follows Exposure Group #0 SpTrg #32 Require And-Or Term(s) # 83 217 243 -247 255 SpTrg #33 Follows Exposure Group #0 SpTrg #33 Require And-Or Term(s) # 80 129 243 -247 255 SpTrg #34 Follows Exposure Group #0 SpTrg #34 Require And-Or Term(s) # 80 148 243 -247 255 SpTrg #35 Follows Exposure Group #0 SpTrg #35 Require And-Or Term(s) # 84 217 243 -247 255 SpTrg #36 Follows Exposure Group #0 SpTrg #36 Require And-Or Term(s) # 85 217 243 -247 255 SpTrg #37 Follows Exposure Group #0 SpTrg #37 Require And-Or Term(s) # 86 217 243 -247 255 SpTrg #38 Follows Exposure Group #0 SpTrg #38 Require And-Or Term(s) # 87 217 243 -247 255 SpTrg #39 Follows Exposure Group #0 SpTrg #39 Require And-Or Term(s) # 85 129 243 -247 255 SpTrg #40 Follows Exposure Group #0 SpTrg #40 Require And-Or Term(s) # 85 143 243 -247 255 SpTrg #41 Follows Exposure Group #0 SpTrg #41 Require And-Or Term(s) # 85 139 243 -247 255 SpTrg #42 Follows Exposure Group #0 SpTrg #42 Require And-Or Term(s) # 85 148 243 -247 255 SpTrg #43 Follows Exposure Group #0 SpTrg #43 Require And-Or Term(s) # 85 143 243 -247 255 SpTrg #44 Follows Exposure Group #0 SpTrg #44 Require And-Or Term(s) # 243 -247 255 SpTrg #45 Follows Exposure Group #1 SpTrg #45 Require And-Or Term(s) # -221 243 -247 255 SpTrg #46 Follows Exposure Group #1 SpTrg #46 Require And-Or Term(s) # 139 -221 243 -247 255 SpTrg #47 Follows Exposure Group #2 SpTrg #47 Require And-Or Term(s) # -220 243 -247 255 SpTrg #48 Follows Exposure Group #2 SpTrg #48 Require And-Or Term(s) # 139 -220 243 -247 255 SpTrg #49 Follows Exposure Group #3 SpTrg #49 Require And-Or Term(s) # -220:-221 243 -247 255 SpTrg #50 Follows Exposure Group #3 SpTrg #50 Require And-Or Term(s) # 139 -220:-221 243 -247 255 Time Stamp 23-Jul-2002 15:54:42.976 ------------------------------------------------------------------------------ DATE: 19,20,22,23,24,25-JULY-2002 At: Fermi Topics: Work on Cal Trig, Check Master Clock timing Joe has provided some more data points about the CTFE ADC Clk vs the peak of the Trigger Pick Off Signal. The table below is the total collection so far. BX Marker to scope is a 24 nsec cable. ADC_Clk and ADC_Input to scope are 16 nsec cables. ADC Input ADC Clk Falling Edge Peak ---------------------------- Eta,Phi EM/HD Amplitude WRT Input Peak WRT BX ------- ----- --------- -------------- ------------ +2,5 EM 450 mV 50 ns early 666 ns after +2,5 EM 750 mV 48 ns early 666 ns after +2,5 EM 500 mV 50 ns early 668 ns after +2,5 EM 550 mV 52 ns early 666 ns after +2,5 EM 450 mV 48 ns early 664 ns after +2,5 HD 350 mV 84 ns early 666 ns after +2,5 HD 300 mV 102 ns early 666 ns after +2,5 HD 400 mV 6 ns late 668 ns after +2,5 HD 500 mV 152 ns early 666 ns after +2,5 HD 400 mV 214 ns early 668 ns after +2,24 EM 400 mV 28 ns early 676 ns after +2,24 EM 400 mV 52 ns early 674 ns after +2,24 EM 700 mV 52 ns early 674 ns after +2,24 EM 400 mV 50 ns early 674 ns after +2,24 EM 250 mV 54 ns early 676 ns after +2,24 EM 450 mV 42 ns early 676 ns after +2,24 HD 300 mV 124 ns early 674 ns after +2,24 HD 900 mV 122 ns early 676 ns after +2,24 HD 400 mV 114 ns early 674 ns after -2,5 EM 350 mV 58 ns early 662 ns after -2,5 EM 400 mV 54 ns early 664 ns after -2,5 EM 500 mV 52 ns early 662 ns after -2,5 EM 500 mV 58 ns early 662 ns after -2,5 EM 400 mV 62 ns early 664 ns after -2,5 HD 1050 mV 154 ns early 664 ns after -2,5 HD 750 mV 124 ns early 662 ns after -2,5 HD 500 mV 132 ns early 662 ns after -2,5 HD 450 mV 124 ns early 662 ns after -2,5 HD 450 mV 120 ns early 662 ns after -2,24 EM 500 mV 66 ns early 668 ns after -2,24 EM 450 mV 48 ns early 668 ns after -2,24 EM 450 mV 40 ns early 670 ns after -2,24 EM 450 mV 52 ns early 668 ns after -2,24 EM 450 mV 60 ns early 668 ns after -2,24 HD 750 mV 122 ns earl 668 ns after -2,24 HD 1150 mV 102 ns early 668 ns after -2,24 HD 650 mV 118 ns early 668 ns after -2,24 HD 350 mV 128 ns early 670 ns after -2,24 HD 500 mV 124 ns early 668 ns after +8,5 EM 0 mV 0 ns early 0 ns after +8,5 HD 0 mV 0 ns early 0 ns after +8,24 EM 0 mV 0 ns early 0 ns after +8,24 HD 0 mV 0 ns early 0 ns after -8,2 EM 450 mV 58 ns early 656 ns after -8,2 EM 550 mV 56 ns early 658 ns after -8,2 EM 500 mV 56 ns early 658 ns after -8,2 HD 300 mV 46 ns early 660 ns after -8,2 HD 550 mV 60 ns early 660 ns after -8,2 HD 950 mV 44 ns early 658 ns after -8,2 HD 550 mV 52 ns early 658 ns after -8,2 HD 500 mV 46 ns early 658 ns after -8,8 EM 450 mV 36 ns early 658 ns after -8,8 EM 550 mV 36 ns early 658 ns after -8,8 EM 650 mV 34 ns early 658 ns after -8,8 HD 350 mV 18 ns early 662 ns after -8,8 HD 500 mV 10 ns late 660 ns after -8,8 HD 650 mV 14 ns early 660 ns after -8,13 EM 600 mV 42 ns early 660 ns after -8,13 EM 450 mV 40 ns early 660 ns after -8,13 EM 500 mV 46 ns early 660 ns after -8,13 EM 500 mV 52 ns early 660 ns after -8,13 EM 550 mV 40 ns early 660 ns after -8,13 HD 450 mV 8 ns early 658 ns after -8,13 HD 500 mV 16 ns early 660 ns after -8,13 HD 500 mV 0 ns early 660 ns after +10,5 EM 250 mV 58 ns early 690 ns after +10,5 EM 200 mV 50 ns early 690 ns after +10,5 EM 200 mV 56 ns early 690 ns after +10,5 EM 300 mV 52 ns early 690 ns after +10,5 HD 300 mV 44 ns early 690 ns after +10,5 HD 250 mV 64 ns early 692 ns after +10,5 HD 300 mV 46 ns early 690 ns after +10,5 HD 250 mV 56 ns early 692 ns after +10,5 HD 400 mV 48 ns early 692 ns after +10,24 EM 500 mV 90 ns early 700 ns after +10,24 EM 500 mV 84 ns early 698 ns after +10,24 EM 350 mV 76 ns early 700 ns after +10,24 EM 650 mV 76 ns early 700 ns after +10,24 EM 450 mV 84 ns early 700 ns after +10,24 HD 350 mV 36 ns early 700 ns after +10,24 HD 600 mV 38 ns early 700 ns after +10,24 HD 350 mV 38 ns early 698 ns after +10,24 HD 350 mV 40 ns early 702 ns after +10,24 HD 300 mV 42 ns early 700 ns after -10,5 EM 500 mV 58 ns early 630 ns after -10,5 EM 650 mV 62 ns early 628 ns after -10,5 EM 550 mV 60 ns early 630 ns after -10,5 EM 450 mV 54 ns early 632 ns after -10,5 HD 500 mV 54 ns early 632 ns after -10,5 HD 450 mV 46 ns early 630 ns after -10,5 HD 550 mV 32 ns early 632 ns after -10,5 HD 450 mV 52 ns early 632 ns after -10,24 EM 1050 mV 74 ns early 642 ns after -10,24 EM 600 mV 84 ns early 640 ns after -10,24 EM 600 mV 76 ns early 644 ns after -10,24 EM 450 mV 68 ns early 640 ns after -10,24 HD 500 mV 40 ns early 642 ns after -10,24 HD 450 mV 26 ns early 642 ns after -10,24 HD 550 mV 36 ns early 644 ns after -10,24 HD 600 mV 4 ns early 642 ns after -10,24 HD 600 mV 12 ns late 644 ns after -10,24 HD 700 mV 38 ns early 640 ns after +11,5 EM 400 mV 64 ns early 692 ns after +11,5 EM 600 mV 62 ns early 692 ns after +11,5 EM 300 mV 70 ns early 690 ns after +11,5 EM 350 mV 70 ns early 690 ns after +11,5 EM 350 mV 66 ns early 692 ns after +11,5 HD 600 mV 120 ns early 690 ns after +11,5 HD 700 mV 54 ns early 690 ns after +11,5 HD 750 mV 52 ns early 690 ns after +11,5 HD 300 mV 50 ns early 690 ns after +11,5 HD 300 mV 49 ns early 690 ns after +11,24 EM 300 mV 76 ns early 700 ns after +11,24 EM 400 mV 80 ns early 700 ns after +11,24 EM 350 mV 84 ns early 700 ns after +11,24 EM 350 mV 82 ns early 700 ns after +11,24 EM 400 mV 84 ns early 700 ns after +11,24 HD 300 mV 60 ns early 700 ns after +11,24 HD 350 mV 10 ns late 700 ns after +11,24 HD 500 mV 34 ns early 702 ns after +11,24 HD 300 mV 70 ns early 700 ns after +11,24 HD 500 mV 30 ns early 700 ns after -11,1 EM 500 mV 76 ns early 630 ns after -11,1 EM 700 mV 60 ns early 632 ns after -11,1 EM 600 mV 72 ns early 630 ns after -11,1 EM 450 mV 62 ns early 632 ns after -11,1 EM 450 mV 66 ns early 630 ns after -11,2 EM 450 mV 74 ns early 636 ns after -11,2 EM 400 mV 62 ns early 636 ns after -11,2 EM 700 mV 72 ns early 632 ns after -11,2 EM 700 mV 72 ns early 634 ns after -11,2 EM 500 mV 70 ns early 634 ns after -11,2 EM 400 mV 76 ns early 634 ns after -11,2 EM 400 mV 72 ns early 638 ns after -11,3 EM 450 mV 56 ns early 630 ns after -11,3 EM 600 mV 52 ns early 630 ns after -11,3 EM 700 mV 56 ns early 632 ns after -11,3 EM 600 mV 54 ns early 630 ns after -11,3 EM 500 mV 58 ns early 630 ns after -11,3 HD 400 mV 46 ns early 630 ns after -11,3 HD 550 mV 74 ns early 630 ns after -11,3 HD 400 mV 66 ns early 630 ns after -11,3 HD 400 mV 86 ns early 630 ns after -11,3 HD 450 mV 88 ns early 630 ns after -11,4 EM 400 mV 72 ns early 630 ns after -11,4 EM 400 mV 66 ns early 630 ns after -11,4 EM 650 mV 68 ns early 630 ns after -11,4 EM 450 mV 64 ns early 628 ns after -11,4 EM 500 mV 72 ns early 630 ns after -11,5 EM no signal -11,6 EM 500 mV 52 ns early 632 ns after -11,6 EM 400 mV 62 ns early 630 ns after -11,6 EM 550 mV 58 ns early 630 ns after -11,6 EM 650 mV 52 ns early 632 ns after -11,6 EM 450 mV 52 ns early 630 ns after -11,7 EM no signal -11,7 HD 400 mV 56 ns early 630 ns after -11,7 HD 500 mV 32 ns early 632 ns after -11,7 HD 500 mV 44 ns early 630 ns after -11,7 HD 350 mV 76 ns early 632 ns after -11,7 HD 600 mV 46 ns early 628 ns after -11,24 EM 450 mV 56 ns early 640 ns after -11,24 EM 400 mV 62 ns early 640 ns after -11,24 EM 600 mV 66 ns early 640 ns after -11,24 EM 450 mV 64 ns early 638 ns after -11,24 EM 400 mV 54 ns early 640 ns after -11,24 EM 450 mV 64 ns early 638 ns after -11,24 EM 400 mV 60 ns early 640 ns after -11,24 EM 600 mV 62 ns early 640 ns after -11,24 EM 500 mV 62 ns early 638 ns after -11,24 EM 500 mV 68 ns early 640 ns after -11,24 EM 1000 mV 58 ns early 640 ns after -11,24 EM 700 mV 56 ns early 640 ns after -11,24 EM 950 mV 62 ns early 638 ns after -11,24 EM 450 mV 58 ns early 638 ns after -11,24 EM 650 mV 58 ns early 640 ns after -11,24 EM 500 mV 64 ns early 640 ns after -11,24 EM 500 mV 62 ns early 640 ns after -11,24 EM 1100 mV 52 ns early 640 ns after -11,24 EM 500 mV 54 ns early 640 ns after -11,24 EM 450 mV 62 ns early 638 ns after -11,24 EM 400 mV 64 ns early 640 ns after -11,24 EM 750 mV 60 ns early 640 ns after -11,24 EM 450 mV 64 ns early 640 ns after -11,24 EM 450 mV 48 ns early 640 ns after -11,24 EM 450 mV 60 ns early 638 ns after -11,24 EM 800 mV 52 ns early 640 ns after -11,24 EM 500 mV 62 ns early 640 ns after -11,24 EM 550 mV 58 ns early 640 ns after -11,24 EM 450 mV 58 ns early 640 ns after -11,24 EM 550 mV 62 ns early 642 ns after -11,24 HD 350 mV 62 ns early 638 ns after -11,24 HD 400 mV 30 ns early 640 ns after -11,24 HD 450 mV 50 ns early 640 ns after -11,24 HD 450 mV 30 ns early 640 ns after -11,24 HD 450 mV 36 ns early 638 ns after -11,25 EM 450 mV 62 ns early 640 ns after -11,25 EM 650 mV 64 ns early 640 ns after -11,25 EM 500 mV 58 ns early 640 ns after -11,25 EM 500 mV 58 ns early 638 ns after -11,25 EM 600 mV 62 ns early 638 ns after -11,26 EM 450 mV 82 ns early 642 ns after -11,26 EM 550 mV 76 ns early 642 ns after -11,26 EM 900 mV 76 ns early 642 ns after -11,26 EM 550 mV 76 ns early 642 ns after -11,26 EM 500 mV 82 ns early 642 ns after -11,31 EM 300 mV 70 ns early 642 ns after -11,31 EM 600 mV 68 ns early 642 ns after -11,31 EM 400 mV 64 ns early 642 ns after -11,31 EM 550 mV 64 ns early 644 ns after -11,31 EM 400 mV 62 ns early 642 ns after -11,32 EM 400 mV 68 ns early 644 ns after -11,32 EM 400 mV 74 ns early 644 ns after -11,32 EM 500 mV 66 ns early 644 ns after -11,32 EM 550 mV 78 ns early 642 ns after -11,32 EM 600 mV 68 ns early 642 ns after +2,5 EM averages 49.6 nsec early +2,24 EM averages 50.0 nsec early -2,5 EM averages 56.8 nsec early -2,24 EM averages 53.2 nsec early -8,2 EM averages 56.7 nsec early -8,8 EM averages 35.3 nsec early -8,13 EM averages 44.0 nsec early +10,5 EM averages 54.0 nsec early +10,24 EM averages 82.0 nsec early -10,5 EM averages 58.5 nsec early -10,24 EM averages 75.5 nsec early +11,5 EM averages 66.4 nsec early +11,24 EM averages 81.2 nsec early -11,1 EM averages 67.2 nsec early -11,2 EM averages 71.1 nsec early -11,3 EM averages 55.2 nsec early -11,4 EM averages 68.4 nsec early -11,6 EM averages 55.2 nsec early -11,24 EM average of 1st 5 60.4 nsec early -11,24 EM average of 2nd 5 63.2 nsec early -11,24 EM average of 3rd 5 58.4 nsec early -11,24 EM average of 4th 5 58.8 nsec early -11,24 EM average of 5th 5 59.2 nsec early -11,24 EM average of 6th 5 58.4 nsec early -11,24 EM average of all 30 59.7 nsec early -11,25 EM averages 60.8 nsec early -11,26 EM averages 78.4 nsec early -11,31 EM averages 65.6 nsec early -11,32 EM averages 70.8 nsec early The following is a sketch of what we are measuring. Note which edges of the signals we are measuring. Master Clock -------+ +---------------------------------------- BX Marker | | +----+ |<-- BX to ADC Clk -->| +----+ | | ADC Clock ------------------------+ +----------------------- |<-- ADC Clk to Input -->| ^ / \ ADC Input ___________________________________________/ \_____ Change the timing of the CTFE ADC Clk The goal is to move the CTFE ADC Clk later by 3 RF buckets, i.e. later by 3 x 18.83 nsec = 56.49 nsec. But we can not move it that much later just by itself because to do so would not give the ADC's enough time to convert and setup their data at the inputs to the F399's before the falling edge of the Latch-Shift signal. So we need to move everything. But we do not want to disturbe the operation of the ERPB readout stuff. So the plan is: Move all Tier_1, Tier_2, and Tier_3 Timing_&_Control signals, except for the ADC_Clk, later by 7 RF_Buckets Move the ADC_Clk later by 3 RF_Buckets (yes, this makes the ADC_Clk happen 4 RF_Buckets earlier in the processing cycle but that is still at a good safe place. Stall Geographic Section L1_Acpt AND L1_Period signal in the Cal_Trig_Readout_Helper FPGA by one full BX_Clk tick. This leaves the L1_Acpt and all of the DC-ERPB timing_&_control signals in the same phase relationship as they are now. Move both the AOIT Strobe and Gap signals later by 132 nsec. This is just to make them match up with the new time location where the Cal Trig will be producing its output. Do not disturbe the timing signal that is sent to the Forward Proton system/room. The new Sequencer_2 file is ready in the test directory and the new exo file (9_1) is ready for the ct_readout_helper. CT_Read_Help has been loaded just for a test run. All the timing numbers are in the #4 FPGA notebook. There are some issues to think about. Major problem Sat night / Sun morning July 20,21. L1 Cal Trig was 100% L1_Busy. I have not idea what all things they tried to do to fix it. At some point they called Daniel. He first asked them to "reset" the SBC in that crate. This "SBC reset" is a standard thing that DAQ shifters know how to do. At some point he asked them to do a "VME System Reset" in that crate. That appears to have cleaned up the L1_Busy but L3 was in some way not happy. A "reset" of COOR fixed that problem. What Daniel may have forgotten again is that a VME System Reset wipes out the setup in the VRB's and the VRBC. You then need to do an Cal_Trig_Initialize to write the setup back into these modules. This was "N" hours of lost beam. I think Daniel only talked by phone and did not actually come in. Returned Monday afternoon and people were running around saying there was a problem with Cal Trig. Both Tier 1 Power Pans in M107 were off. One was turned off and one had tripped off. The breaker in the wall panel that feeds this rack was also tripped. I have no idea what happened or who turned off the one Power Pan. Everything turned back on OK. They had Configured FPGA's on Monday afternoon at about 4:?? PM I do not know why or who did this. I checked the 2 Power Pan's in M107. The upper one read at its test points: +5.054V -2.106V -4.613V -5.228V lower +5.050V -2.105V -4.520V -5.228V On Saturday before leaving it looked like the count from Tot_Et Ref Set #3 was sitting at 1 instead of at 0. I do not know if they use Tot_Et Ref Set #3 during global physics running. No one has said anything about a problem. Monday evening I dug into it and this "1" is coming from the upper CHTCR in the upper Tier 1 crate in M106. This is eta -5:-8 phi 1:8. Read this CHTCR by hand MBA = 175, CA =2, FA's 28:31 for TOT_Et Ref Set #3. Find that FA 30 always reads $40. I think this bit corresponds to TT -7,2 For the store that is starting Monday evening I pull the Tot_Et output cable from this CHTCR. For the next store I used a cable will some missing wires (only 16 pairs) so that Tot_Et_Ref_Sets 0,1,2 are connected from this CHTCR to the Counting Tree but not Tot_Et_Ref_Set_3. I assume this is a 16V8 PAL problem so I need to bring on to Fermi. In the store on Monday evening I checked the Master Clock timing agains PD. It was 164 or 165 nsec from the falling edge of BX marker to the next PD signal. This corresponds to 995 or 996 nsec from the Master Clock BX marker to the center of the PD marker (i.e. 2x 396 = 790.90 nsec plus 164 or 165). On 19:21-JUNE-02 it was 956 or 957. Need to bring a 9V battery for the fluke meter (some one left it turned on). ------------------------------------------------------------------------------ DATE: 9:13-JULY-2002 At: Fermi Topics: Work on Cal Trig We have had 4 Trigger Towers that looked OK at the ADC output but readout zero in the HSRO readout to L2 L3. These 4 TT's are: +8,7 EM +6,22 EM -8,27 HD -9,29 EM. Joe and I pulled these 4 CTFE cards and Joe checked these PROM's. All 4 were blank. He programmed them and then verified that we now see readout data from these Trigger Towers. We have had a problem that we could not generate Total Et (aka Jet) triggers from the eta,phi range +9:+12 , 9:16 because if we included the Tot Et output from the CHTCR that covers this renge in the Counter Tree then all the Tot Et triggers just fired all the time. See 19:21-JUNE-02 Well the problem was just that the Tot Et cable from the output of this CHTCR card had been plugged in backwards. Watch the cable color code or the hand labeled black dot and triangle to get this cable plugged in correctly. Joe and Daniel worked on the BLS crate from which all TT's had big random noise. This crate is TT's -7:-12 phi 9 and -7:-10 phi 10. It had a power supply problem that Dean was able to see on a scope. This power supply was replaced. Now the big random noise for all TT's in this crate is gone but there is some new, lower level noise, that is associated with the L1_Acpts that happens on perhaps 5% of the L1_Acpts. Joe is investigating. Tuesday night made a pedestal run. The result of this run is in \D0_Log\Find_DAC_V3_1_H_20020709.tti;1 and .hst;1 This find dac run did find a value for all TT's. So currently the files to use with VME_Access: \D0_Log\Find_DAC_V3_1_H_20020709.tti;1 \D0_Config\Run_II_L1CT_Bob_1_Gain.tti Watched running last night with the current version of multibuffer VRBC. This was with a L1 Accept rate of 235 Hz, and a L2 Accept rate of 65 Hz. What I saw was: Cal Trig about 0.55% L1_Busy and TFW about 0.35% L1_Busy. This implies that with each L1_Acpt the VRBC is asserting the L1_Buzy for about: 23 usec for the Cal Trig and 15 usec for the TFW. Brought 71 more of the 5:20 Term-Attn-Brds to Fermi. See 19:21-JUNE-2002 for a more complete inventory of Term-Attn-Brds. Finally get the documentation written and on the web for the Cal Trig Timing and Control signal Distribution setup that was installed a couple of weeks ago. Very happy that this is fanally documented in www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/timing/cal_trig_timing_generation_ii.txt Meeting with Neal and Ted about SCL and a fast L1_Acpt path. Two basic possibilities. 1. save about 40 nsec by pulling the L1_Acpt signal out of the Receiver ahead of all the error checking and that type of stuff. 2. Jump around the whole serialize deserialize system by using one of the 485 pairs. This could save something like 200 nsec. Notes to Ron and the interested groups. A little after 11 Wednesday night I noticed that all 8 channels on the CTFE card at -9:-12 phi 17 were showing a Zero Energy Response of $00 instead of $08. Trying a L1 Cal Trig Init just made things worse. The Cal Trig Init had errors trying to talk to this CTFE card registers 80 and 82 - and the Init bailed out at that point leaving the system in a state that could not run. So pull out CTFE -9,17 which was CTFE SN# 356. Its problem was a pinched Red wire in the cable harnes from U235 to the Term-Attn-Brd. The red wire was pinched under the MC10319's pin 13 and it appears that the Vee has killed that section of U235. This would explain the problem with FA 80. For -9,17 replace CTFE SN# 356 with CTFE SN# 111. On CTFE SN# 356 replace chip U235 - but the Chip Kit at Fermi has no 74ALS990's in it - need to bring some 74ALS990 next week. Tier 2 Tier 3 Power Pan MM7 has been put back together and tested and is back in the spare Power Pan storage cabinet. MM7 is now using: +5.0V is SN# 89 from 15-SEPT-93, -2.0V is SN# 35 from 25-APR-91, -4.5V is SN# 30 from 7-FEB-92, -5.2V is small linear. The 600 Amp -4.5V brick was replaced. I did not get varistors added to this Power Pan. Tier 1 Power Pan PDM-17 was put back together. It now has bricks: +5.0V is SN# 7 from 18-DEC-90, -2.0V is SN# 54 from 21-JAN-92, -4.5V is SN# 61 from 7-JAN-92, -5.2V is SN# 62 from 7-JAN-92. The 600 Amp +5.0V brick was replaced. PDM-17 now tests more or less OK. the -4.5V and the -5.2V supplies do not have the best regulation. I did add varistors to this Power Pan. During the store on Thursday Friday, Joe and I check a number of Trigger Towers to examine the ADC timing wrt the ADC input signal. Used 8 nsec cables to the the ADC Input signal and the ADC Clock signals from the CTFE card. Used a 24 nsec cable to get the BX signal from the Master Clock Rack public access BX monitor jack. Look at TT's from all the major different cabling layouts: +2,5 +2,24 -2,5 -2,24 +8,5 +8,24 -8,5 -8,24 +10,5 +10,24 -10,5 -10,24 For each TT look at EM and HD. ADC Input ADC Clk Falling Edge Peak ---------------------------- Eta,Phi EM/HD Amplitude WRT Input Peak WRT BX ------- ----- --------- -------------- ------------ +2,5 EM 450 mV 50 ns early 666 ns after +2,5 EM 750 mV 48 ns early 666 ns after +2,5 EM 500 mV 50 ns early 668 ns after +2,5 EM 550 mV 52 ns early 666 ns after +2,5 EM 450 mV 48 ns early 664 ns after +2,5 HD 350 mV 84 ns early 666 ns after +2,5 HD 300 mV 102 ns early 666 ns after +2,5 HD 400 mV 6 ns late 668 ns after +2,5 HD 500 mV 152 ns early 666 ns after +2,5 HD 400 mV 214 ns early 668 ns after +2,24 EM 400 mV 28 ns early 676 ns after +2,24 EM 400 mV 52 ns early 674 ns after +2,24 EM 700 mV 52 ns early 674 ns after +2,24 EM 400 mV 50 ns early 674 ns after +2,24 EM 250 mV 54 ns early 676 ns after +2,24 EM 450 mV 42 ns early 676 ns after +2,24 HD 300 mV 124 ns early 674 ns after +2,24 HD 900 mV 122 ns early 676 ns after +2,24 HD 400 mV 114 ns early 674 ns after -2,5 EM 0 mV 0 ns early 0 ns after -2,5 HD 0 mV 0 ns early 0 ns after -2,24 EM 0 mV 0 ns early 0 ns after -2,24 HD 0 mV 0 ns early 0 ns after +8,5 EM 0 mV 0 ns early 0 ns after +8,5 HD 0 mV 0 ns early 0 ns after +8,24 EM 0 mV 0 ns early 0 ns after +8,24 HD 0 mV 0 ns early 0 ns after -8,2 EM 450 mV 58 ns early 656 ns after -8,2 EM 550 mV 56 ns early 658 ns after -8,2 EM 500 mV 56 ns early 658 ns after -8,2 HD 300 mV 46 ns early 660 ns after -8,2 HD 550 mV 60 ns early 660 ns after -8,2 HD 950 mV 44 ns early 658 ns after -8,2 HD 550 mV 52 ns early 658 ns after -8,2 HD 500 mV 46 ns early 658 ns after -8,8 EM 450 mV 36 ns early 658 ns after -8,8 EM 550 mV 36 ns early 658 ns after -8,8 EM 650 mV 34 ns early 658 ns after -8,8 HD 350 mV 18 ns early 662 ns after -8,8 HD 500 mV 10 ns late 660 ns after -8,8 HD 650 mV 14 ns early 660 ns after -8,13 EM 600 mV 42 ns early 660 ns after -8,13 EM 450 mV 40 ns early 660 ns after -8,13 EM 500 mV 46 ns early 660 ns after -8,13 EM 500 mV 52 ns early 660 ns after -8,13 EM 550 mV 40 ns early 660 ns after -8,13 HD 450 mV 8 ns early 658 ns after -8,13 HD 500 mV 16 ns early 660 ns after -8,13 HD 500 mV 0 ns early 660 ns after +10,5 EM 250 mV 58 ns early 690 ns after +10,5 EM 200 mV 50 ns early 690 ns after +10,5 EM 200 mV 56 ns early 690 ns after +10,5 EM 300 mV 52 ns early 690 ns after +10,5 HD 300 mV 44 ns early 690 ns after +10,5 HD 250 mV 64 ns early 692 ns after +10,5 HD 300 mV 46 ns early 690 ns after +10,5 HD 250 mV 56 ns early 692 ns after +10,5 HD 400 mV 48 ns early 692 ns after +10,24 EM 500 mV 90 ns early 700 ns after +10,24 EM 500 mV 84 ns early 698 ns after +10,24 EM 350 mV 76 ns early 700 ns after +10,24 EM 650 mV 76 ns early 700 ns after +10,24 EM 450 mV 84 ns early 700 ns after +10,24 HD 350 mV 36 ns early 700 ns after +10,24 HD 600 mV 38 ns early 700 ns after +10,24 HD 350 mV 38 ns early 698 ns after +10,24 HD 350 mV 40 ns early 702 ns after +10,24 HD 300 mV 42 ns early 700 ns after -10,5 EM 500 mV 58 ns early 630 ns after -10,5 EM 650 mV 62 ns early 628 ns after -10,5 EM 550 mV 60 ns early 630 ns after -10,5 EM 450 mV 54 ns early 632 ns after -10,5 HD 500 mV 54 ns early 632 ns after -10,5 HD 450 mV 46 ns early 630 ns after -10,5 HD 550 mV 32 ns early 632 ns after -10,5 HD 450 mV 52 ns early 632 ns after -10,24 EM 1050 mV 74 ns early 642 ns after -10,24 EM 600 mV 84 ns early 640 ns after -10,24 EM 600 mV 76 ns early 644 ns after -10,24 EM 450 mV 68 ns early 640 ns after -10,24 HD 500 mV 40 ns early 642 ns after -10,24 HD 450 mV 26 ns early 642 ns after -10,24 HD 550 mV 36 ns early 644 ns after -10,24 HD 600 mV 4 ns early 642 ns after -10,24 HD 600 mV 12 ns late 644 ns after -10,24 HD 700 mV 38 ns early 640 ns after +2,5 EM averages 49.6 nsec early +2,24 EM averages 50.0 nsec early -8,2 EM averages 56.7 nsec early -8,8 EM averages 35.3 nsec early -8,13 EM averages 44.0 nsec early +10,5 EM averages 54.0 nsec early +10,24 EM averages 82.0 nsec early -10,5 EM averages 58.5 nsec early -10,24 EM averages 75.5 nsec early Average of the EM's looked at so far is that the ADC Clock is 56.2 nsec early. Is there a phi effect in the high eta samples ? OK, want to move the ADC Clock 56 nsec i.e. 3x 18.83 nsec later. But there is not enough slack in the system to move just the ADC Clock. Cal Trig must move also, and thus so must ERPB and Strobe-Gap for AOIT. The concern is moving ERPB and screwing up getting the correct data for the correct BX. So need to look at this and also look at and verify that the current Cal Trig to ERPB alignment is optimal. Could move ADC Clock later by 3 RF Buckets and everything else later by 7 RF Buckets, i.e. 1 full Tick. On a 5:20 Term-Attn-Brd check the gain of the two sides. Do this in M108 phi 17 using the "hand pulser". Use VME_Access to set all the Gains to 128 before making this test. CTFE LEMO Monitor Output Voltage with CTFE -------------------------------------------------- Eta Pulser Outputs Only + Pulser Only - Pulser Channel + & - Driven Output Driven Output Driven ------- -------------- ------------- ------------- -9 EM 896 mV 452 mV 452 mV -9 HD 920 mV 452 mV 452 mV -10 EM 1300 mV 432 mV 864 mV -10 HD 888 mV 448 mV 448 mV -11 EM 884 mV 440 mV 448 mV -11 HD 908 mV 456 mV 456 mV -12 EM 1290 mV 432 mV 860 mV -12 HD 932 mV 468 mV 468 mV OK so the EM side of the upper channel on each Term-Attn-Brd is screwed up. Inspect the cards and see that Hughes has installed a 5621 value resistor for R80 instead of a 84R5 value resistor. They appear to have done this on all 550 of the Term-Attn-Brds. This makes the even number EM channels have about 1.43 time the gain that they should have. Oh joy. ------------------------------------------------------------------------------ DATE: 1:2-JULY-2002 At: Fermi Topics: Work on L2_Helper and L1AL2_Scaler, New slot 1 processor code for the Master Clock Problems with the L2_Helper issuing both a L1_Acpt and a L2_Decision in the same SCL Frame. For now this is fixed by correctly adjusting the mask of 36 ticks where the L2_Helper will never try to issue a L2_Decision. This will eliminate this problem for beam running. Note that this is a patch to the old May 2000 design of the L2_Helper which is in /L2_Helper_Save_Uber/. This is just a change to the live bx shift register in the Input_Buffer sheet - 25 step to 34 step. The UCF timing was tightened and this was built under M1.4 L2_Helper is M122 Bottom Slot 20 FPGA Site 4. It is called from L2_Helper.dci which was changed from 15_2 to 17_1. Problem with the L1AL2 Scaler. When you have a L1_Acpt and a L2_Decision on adjacent SCL Frames (in either order) this scaler does not count correctly. There maybe some cabling problems but there is also clearly some sloppy logic in this scaler. On Desmo clean up this logic and tighten the ucf and build this under M3.1 L1AL2 is M123 Bottom Slot 19 FPGA Site 16. Edit the L1AL2_GS.dci to change from 3_2 to 4_2. Correcting the logic in the L1AL2 Scaler involved latching its input control lines (i.e. L1_Acpt and L2_Decision) with IDF's so that they would be stable during the time that the counter was trying to do its: hold, inc, or decrm. The point is that this puts the contents of this scaler one tick behind where it had been. So the BX History Shift Register needs to be "tapped" one tick earlier. This is controlled by register 32. The contents of this register had been "1". Now when I set it to "0" on triggered CMD's I see a coutn of 1. I can fix this for now by changing what is in this register with a Init_Post_ _Auxi_FW.rio but I did not do this on this trip based on the "don't change something right before you exit rule". Reinhard wants G.S. $24 and $25 tied up and he wants more SCL Coax to the L2 Test Stand. But I'm out of LMR-100 patch cords. I had 2 in the box above the desk and they are gone. All the LMR-100 cable and the SMA connectors for it are gone. There are only about 2 or 3 MCX connectors left. I need to purchase enough of everything to make 10 more patch cords, i.e. 15 part sets. Thank you one and all for shopping in the TFW cabinet. When I got here on Monday one of the TFW racks had its back door open, M123. I know it was closed on Friday when I left. Did some zero bias running with L1 Cal Trig and its data looked OK. Based on information from Fritz and Geoff that the EPICS problem that caused the Master Clock to be overwritten has now been fixed, I have plugged the Master Clock back into its Ethernet cable and booted its slot 1 processor. So far it is OK. ------------------------------------------------------------------------------ DATE: 26:28-JUNE-02 At: Fermi Topics: Work on L1 Cal Trig, and Edit the Nominal_Gains file to creat a new gains file called, Run_II_L1CT_Bob_1_Gain.tti that implements Bob's 21-JUNE-2002 changes to the EM calibration. No changes to the HD calibration were implemented at this time. So the following gains are setup by this file: EM Section HD Section --------------------------------- ------------------------------- Nominal Resulting Nominal Boost Eta Req'd EM Energy New DAC Req'd for BLS New DAC Index Gain Over Estm Gain Code Gain Resistors Gain Code ----- ------- --------- ---- ---- ------- --------- ---- ---- 1 1.54 1.2 1.28 156 1.54 1.0 1.54 183 2 1.48 1.2 1.23 151 1.48 1.0 1.48 176 3 1.37 1.2 1.14 142 1.37 1.0 1.37 165 4 1.24 1.2 1.03 131 1.24 1.0 1.24 152 5 1.08 1.2 0.90 117 1.08 1.6 1.73 202 6 0.93 1.9 0.49 75 0.93 1.6 1.49 177 7 0.76 1.2 0.63 90 0.76 1.6 1.22 150 8 0.66 1.9 0.35 61 0.66 1.6 1.06 134 9 1.53 1.2 1.27 155 1.53 1.0 1.53 182 10 1.26 1.6 0.79 106 1.26 1.0 1.26 154 11 1.05 1.2 0.87 114 1.05 1.0 1.05 133 12 0.87 1.6 0.55 82 0.87 1.0 0.87 114 Notes: So far North and South are the same. Nominal Required Gain is just from the Geometery. EM Gain has been modified to fit Bob's calibration numbers from 21-JUNE-2002. HD Gain has only been modified to fit the BLS resistor problem because so far HD calibration looks OK in Bob's plots. Make a Find_DAC run the result of which is in the file: \D0_Logs\Find_DAC_V3_H_20020626.tti:1 This run of Find_DAC did not fail on any channels. Run the French Pulser and check the CTFE card ADC monitor connectors with a scope to look at the waveform. The pulser was set to fire all patterns with a Pulser DAC Amplitude of 1200 and a Delay of 100. The pulser was set to fire at a fixed Bunch. The intent was to get some idea if the calibration looks OK and to get some feel for what the L1 Cal Trig Pulser program will have to work with. In some cases the indicated phi was not available because it is disconnected so an adjacent phi was used. These measurements were made after loading the Bob_1 Gains. The voltage is measured wrt the -1V absolute "0" input level to the ADC. So the voltage during statick conditions would measure about 0.03 EM at Phi 10 ------------- +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 1.65 1.50 1.50 1.40 1.20 0.80 0.50 1.05 0.72 0.70 0.52 0.55 Time 60 64 60 48 64 64 112 104 64 60 52 44 Smpl V 1.45 1.35 1.40 1.25 1.10 0.75 0.35 0.80 0.65 0.65 0.50 0.53 EM at Phi 25 ------------- +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 1.80 1.75 1.75 1.50 1.40 0.95 0.45 1.05 0.75 0.75 0.56 0.50 Time 56 60 52 52 68 68 144 140 96 92 76 100 Smpl V 1.65 1.65 1.55 1.45 1.35 0.85 0.35 0.75 0.60 0.61 0.50 0.42 EM at Phi 10 ------------- -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 1.70 1.70 1.65 1.40 1.30 0.90 0.55 1.20 0.89 0.82 0.62 0.42 Time 64 64 64 60 64 60 24 28 48 40 24 44 Smpl V 1.60 1.60 1.55 1.30 1.20 0.85 0.50 1.15 0.84 0.78 0.60 0.40 EM at Phi 25 ------------- -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 1.15 1.45 1.45 1.30 1.15 0.80 0.40 0.70 0.68 0.64 0.50 0.46 Time 52 56 48 40 60 28 80 84 92 92 72 80 Smpl V 1.05 1.40 1.40 1.25 1.05 0.75 0.35 0.55 0.55 0.52 0.42 0.41 Peak Volts --> The maximum value reached by the ADC input pulse. Time --> How long after the ADC Clk falling edge did the ADC input reach its maximum. Yes, in all cases the ADC input reached its maximum value after the ADC Clock falling edge. Sample Volts --> The amplitude of the ADC input signals at the time of the falling edge of the ADC Clk. Recall that for EM it is Trigger Tower Phi's 6 and 7 that are the crack between CC and EC. Phi 6 is missing just a little bit and phi 7 is almost completely gone. Phi's 5 and 8 are fully complete. Most of the EM wave forms look pretty much like a pulse except for eta 7. EM eta 7 is a very confused wave form. HD at Phi 10 ------------- +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 0.65 0.65 0.65 0.60 0.26 0.25 0.58 0.45 0.38 0.32 0.32 0.30 Smpl V 0.25 0.20 0.20 0.20 0.22 0.20 0.38 0.30 0.24 0.20 0.22 0.22 Shape M M M M wm wm M M M M M M Sp_Loc nbm nbm nbm nbm rsm nbm nbm nbm abm abm abm nbm HD at Phi 25 ------------- +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 0.75 0.75 0.75 0.70 0.31 0.26 0.62 0.48 0.42 0.36 0.32 0.30 Smpl V 0.25 0.30 0.30 0.30 0.25 0.20 0.45 0.35 0.32 0.28 0.24 0.21 Shape M M M M wm wm M M M M M M Sp_Loc nbm nbm nbm nbm rsm nbm nbm nbm abm abm abm nbm HD at Phi 10 ------------- -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 0.75 0.75 0.65 0.65 0.28 0.28 0.70 0.51 0.44 0.38 0.36 0.32 Smpl V 0.20 0.20 0.20 0.20 0.22 0.20 0.45 0.38 0.32 0.24 0.25 0.23 Shape M M M M wm wm M M M M M M Sp_Loc nbm nbm nbm nbm nbm abm nbm nbm nbm abm nbm nbm HD at Phi 25 ------------- -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Peak V 0.65 0.65 0.65 0.50 0.25 0.26 0.52 0.42 0.38 0.35 0.28 0.25 Smpl V 0.20 0.20 0.20 0.30 0.20 0.20 0.28 0.28 0.30 0.24 0.22 0.20 Shape M M M M wm wm M M M M wm wm Sp_Loc nbm nbm nbm nbm rsm lsm abm nbm abm abm abm abm Peak Volts --> The maximum value reached by the ADC input pulse. Sample Volts --> The amplitude of the ADC input signals at the time of the falling edge of the ADC Clk. Shape --> Indicates the general shape of the input pulse: where M --> an "M" shape to the pulse and wm --> a weak amount of "M" shape to the pulse. Sample Location --> Indicates about where the location of the falling edge of the ADC Clk is located: where nbm --> near bottom of the "M" abm --> at the bottom of the "M" rsm --> right side of the "M" lsm --> left side of the "M" That's right, in almost all cases the ADC Clk samples near the minimum (i.e. center of the "M") of the input pulse. Recall that for HD it is Trigger Tower Phi's 5 and 6 that are the crack between CC and EC. Phi's 4 and 7 are fully complete. While making the above scope measurements I noticed that TT +6,10 has its HD oscillating about 300 mV. So I pulled +6,10. The previous full list of pulled TT's is in last week's log book entry. While Daniel and Joe were looking at Trigger Tower BLS signals they found that -2,9 looked like it had noise. So -2,9 has also been pulled. Take 15 CTFE cards to SiDet for the rework. This is: 7 cards from the MSU Test Stand, 2 Spare cards from the D-Zero Spare Card Cabinet, 2 cards from the racks that had been kept here in case we wanted to see again how the original signals looked, 4 cards from MSU that had been awaiting repair. SCL Frame Structure in Hex x --> Live Crossing in the Accelerator S.G. --> Sync Gap C.G. --> Cosmic Gap B.O.T. --> Beginning of Turn S. --> Spare Marker Cur Cur Cur BX BX BX Num Activity Num Activity Num Activity --- --------------- --- --------------- --- --------------- 1 S.G. S. B.O.T. 36 C.G. S. 6b C.G. S. 2 S.G. 37 C.G. 6c C.G. 3 S.G. 38 C.G. 6d C.G. 4 S.G. S. 39 C.G. S. 6e C.G. S. 5 S.G. 3a C.G. 6f C.G. 6 S.G. 3b C.G. 70 C.G. 7 x S. 3c x S. 71 x S. 8 3d 72 9 3e 73 a x S. 3f x S. 74 x S. b 40 75 c 41 76 d x S. 42 x S. 77 x S. e 43 78 f 44 79 10 x S. 45 x S. 7a x S. 11 46 7b 12 47 7c 13 x S. 48 x S. 7d x S. 14 49 7e 15 4a 7f 16 x S. 4b x S. 80 x S. 17 4c 81 18 4d 82 19 x S. 4e x S. 83 x S. 1a 4f 84 1b 50 85 1c x S. 51 x S. 86 x S. 1d 52 87 1e 53 88 1f x S. 54 x S. 89 x S. 20 55 8a 21 56 8b 22 x S. 57 x S. 8c x S. 23 58 8d 24 59 8e 25 x S. 5a x S. 8f x S. 26 5b 90 27 5c 91 28 x S. 5d x S. 92 x S. 29 5e 93 2a 5f 94 2b C.G. S. 60 C.G. S. 95 S.G. S. 2c C.G. 61 C.G. 96 S.G. 2d C.G. 62 C.G. 97 S.G. 2e C.G. S. 63 C.G. S. 98 S.G. S. 2f C.G. 64 C.G. 99 S.G. 30 C.G. 65 C.G. 9a S.G. 31 C.G. S. 66 C.G. S. 9b S.G. S. 32 C.G. 67 C.G. 9c S.G. 33 C.G. S. 68 C.G. S. 9d S.G. S. 34 C.G. 69 C.G. 9e S.G. 35 C.G. 6a C.G. 9f S.G. ------------------------------------------------------------------------------ DATE: 19:21-JUNE-02 At: Fermi Topics: Work on L1 Cal Trig, Verify Master Clock Timing Check the Master Clock. Using SE01 and the standard 64 nsec and 8 nsec cables I get 355.5 nsec as the raw number. Measure from the leading edge of the Master Clock beam crossing marker to the center of the PD signal and get 956 or 957 nsec (probably closer to 957). This is now setup #1 on the scope. The most recent check before this was 22:26-APR-02. Todays numbers are all either the same as the previous numbers or 1 nsec earlier. 1 nsec earlier would be where the clock was on the measurement previous to 22:26-APR-02. Pager Number for Daniel: 9 for an outside line then 218-4462 wait for the beep and then enter the extension to call. Installed the 600 Amp brick SN# 30 into MM-07 and SN#7 into PDM-17. See last weeks log book entry about Power Pan repair. Pull out and check the card with the current label -05,01 SN# 80 which was reported with Vee to Gnd short on 7,8-MAY-2002. This card is installed at -1,-1. Yes, this card had a black serial DAC wire pinched under pin #13 of the flash ADC. Re-dress this cable so that the nick in the black wire can not touch anything and reinstall it. So, yes, pinched wires are the cause of this problem. We now have one card left in the system that had a Vee to Gnd short that went away when the Term-Attn-Brd was removed and re-installed - but where is this card now ? Install 12 nFd capacitors on the BLS Driver card and the Term-Attn-Card for +1,17 EM and HD. Collect the required before and after scope shots. The cable that feeds the fanout to T2 & T3 has the following signals in it. Signal Pair Source Function ------ ---------- ------------------------------------- 1:9 none 10 MTG FA_? static level 11 CMC_15 static level for now 12 MTG FA_? static level 13 CMC_14 Tier 3 Counter Tree Input Clock 14 MTG FA_? static level 15 CMC_11 Tier 2 Counter Tree Input Clock 16 MTG FA_? static level 17 MTG FA_? static level Edit the Calorimeter Trigger Power Control proceedure to bring it up to date to represent the current system. List of what is currently Excluded and Not Plugged In. With 6 racks we are currently running 768 Trigger Towers (1536 channels) Channels Currently Excluded Rev. 21-JUNE-2002 total = 11 -11,19 EM -11,19 HD -6,9 HD +4,17 EM +5,9 HD +5,27 HD +5,30 HD +6,10 HD +6,29 HD +6,31 HD +10,27 EM Trigger Towers Currently UnPlugged because they have noise: These have been checked on a scope. Rev. 21-JUNE-2002 total = 20 -1,15 the EM has very big noise unplugged since 24-MAY-02 +3,26 the EM has very big noise unplugged since 23-MAY-02 -7,9 -8,9 -9,9 -10,9 the EM and the HD of these towers have noise -11,9 -12,9 -7,10 -8,10 the EM and the HD of these towers have noise -9,10 -10,10 -6,12 the EM has noise -6,24 the EM has noise -4,25 the HD has noise it comes and goes -3,32 the EM probably has noise -1,9 the HD has noise that comes and goes +2,16 the EM has very big noise +3,25 the HD has very big noise +6,24 the HD has noise Towers that have looked a little funny but have not been unplugged -8,7 the HD may have noise -1,6 the HD may have noise -2,9 the HD may have noise -2,3 the HD may have noise In addition to the the eta,phi range eta +9:+12 phi 9:16 is not contributing to the generation of Total Et triggers. This is 32 Trigger Towers, about 4% of the Trigger Towers that are currently running. This area is contributing to the EM triggers. This should not be too hard to fix. Count how many eta 5:20 Term-Attn-Brds there are here. I find: 2 that are clipped and ready to use 28 that need repair 10 that have been repaired 109 in the box from Hughes. This is a total of 149. Note that we have 4 racks to go which will require 256. We have assembled 4 racks using 2:20 Term-Attn-Brd's which is 256. So I think we must have had 256 + 149 = 405 Term-Attn-Brd's here of the 5:20 type here at Fermi. I'm 97% certain that I ordered 550 of the 5:20 type Term-Attn-Brds and 150 of the 1:4 type Term-Attn-Brds for 700 total. I need to check the Parts Order Log Book at MSU and call Hughes Electronics. A new Find DAC pedestal run was made Thursday night on all eta coverage -12:+12 Only one TT failed to find a good DAC value. This is +4,17 EM. It did find good DAC values for all the channels that did not have their BLS cables plugged in. I thought that Find DAC would fail on channels that have no input noise. OK so look at the histograms from some of these unplugged channels. What you see is that as the PED DAC comes up on a value that gives you all 8's, you find a range with all 7's and 8's and a few 11's or 12's or 13's or 15's. And then you reach a range of pure 8's and the you have a smooth exit of just 8's and 9's. I do not know where the 11, 12, 13, 15's come from - but it must count as noise and Find_DAC is happy - and it picks one of the values that gave all 8's. Is this an effect of reading the 29525 will it is shifting ? The current files to use are: (this is the new pedestal file) Gain File to load via VME_Access: \D0_Config\RunII_L1CT_Nominal_Gain.tti ! this is for |eta| 1:12 Pedestal files to load via VME_Access: \D0_Config\Find_DAC_V3_H_20020621.tti:1 ! this is for |eta| 1:12 Want to install a panel to control air flow in M104 where the patch panel was removed this week. Need to bring to Fermi a small CTFE RF choke to fix the cooked one. Need to bring a 3 phase 30 Amp variac here to Fermi. Bring LED S6 lamp for a power pan. ------------------------------------------------------------------------------ DATE: 11:15-JUNE-02 At: Fermi Topics: Work on L1 Cal Trig, The pulleys to run the blower at full normal speed were installed on Monday. I do not know if they did anything about the fact that it looked like they were pretty far out on their shafts and that they had walked there. The belt does not skweek when started - I do not know how tight it is. I do not know if they lubricated the bearings. The numbers to call are: x2849 for the D-Zero On Duty Operator and x3414 for Dispatch. The VESDA did go into "Over air flow" "trouble" when the Cal Trig started but after 15 to 30 minutes all was OK. The fan sounds OK and the motor is not hot. Edited the L1 Cal Trig CMC Sequencer #2 file to compensate for the new cable lenghts in the Run II Timing & Control Distribution. An issue here is that I did not want to change the location of the 2 signals that run the ERPB's, i.e. Time Lines 20 and 21. I'm not certain but what they are in a magical location that lets the system readout correctly no matter what BX you fire on. An issue is that the location of the ADC_Clock can not change in absolute time. So all the rest of Tier_1 and Tier_2 signals moved earlier by 3 RF buckets so that they match the ERPB. The net result is that the ADC data has 3 x 18.8 nsec less setup time. Some number of problems getting the first two racks running again with all the work that has gone on. But they are now back running OK and the next 2 racks turned ON OK. Run Find-DAC in 5:8 with just the results file. This takes about 1:15 to run and reports 68 bad channels (out of 512) spread across 18 CTFE cards (out of 64). Edit the \D0_Config\RunII_L1CT_Nominal_Gain.tti so that it now has the nominal gains for all eta's 1:8. Remember that HD 5:8 needs to be boosted by 1.6x The Tier 3 Power Pan (located in M108 to supply power to Tier 3 in M107) did not start up after its 6 year rest. It's -4.5 Volt brick was dead. So pull MM7 and install MM4. We tested MM4 before installing it. The dead 600 Amp brick from MM7 was pulled out and taken back to MSU to be returned for repair. This brick is SN# 25. The Upper Tier 1 in M107 (eta +9:+12 phi 1:16) Power Pan did not start after its 6 year rest. It's +5 brick was dead. So pull PDM-17 and install the recently repaired PDM-04. The dead 600 Amp brick from PDM-17 was pulled out and taken back to MSU to be sent for repair. This is brick SN# 19. Both of these Power Pan problems are with their 600 Amp bricks The following files must currently be loaded from VME_Access to start the L1 Cal Trig from power up: Gain file to load via VME_Access: \D0_Config\RunII_L1CT_Nominal_Gain.tti ! this is for |eta| 1:12 Pedestal files to load via VME_Access: \D0_Config\Find_DAC_V3_G_20020524.tti:13 ! this is for |eta| 1:4 \D0_Config\Find_DAC_V3_H_20020613.tti;6 ! this is for |eta| 5:8 \D0_Config\Find_DAC_V3_H_20020615.tti;11 ! this is for |eta| 9:12 Have edited lots of the files that control the configuration and initialization of the L1 Cal Trig. These include: The M101 DFC # now configure 6 Bougie/Spark cards using Spark_8_2 # and the aonmct_for_spark in the Main_Array of these cards L1CT_post_init_auxi.vio # Now setup 2 VRB's and change what channels are # to be readout. Change the VBD (SBC) what cards # to readout list. L1CT_post_init_auxi.cio # Change the output state on some of the MTG # channels to select the desired Energy lookup # pages (page 7 for 1st LU, page 5 2nd LU). L1CT_post_init_auxi.rio # Now setup 6 Sparks instead of just 2. the "default gains" file # Now includes all 6 running racks. Install the fibers to feed the L1 Cal Trig data from M105:M108 to L2 Cal Trig. ------------------------------------------------------------------------------ DATE: 4:8-JUNE-02 At: Fermi Topics: Work on L1 Cal Trig, The pedestal runs that show about 5% of the Total Et readout around 8 counts instead of about 16 counts were taken with trigger configurations that allow you to fire on any one of the 159 ticks in a turn. Restrikting the trigger to fire on only the ticks that are the 36 real beam crossings makes the pedestal runs look OK. A real physics beam run from last week looks OK. Verified that the Spark_8_2 and the AONMCT that is made for use with Spark do run OK together and the LSBit looks OK. Now need to make a Rev 9 Spark that internally inverts the strobe from DC Brought the Toaster back to Fermi. Worked on installing 5:8 and 9:12. Worked on the Run II Timing and Control Distribution for L1 Cal Trig. There are 10 BBB's that are used to distribute the Timing & Control to the 10 Tier 1 racks. The TSS section of the BBB is used for this. This distribution is both the Tier 1 signals and the ERPB signals. It is setup in the following way: BBB TSS section signals 1:15 are the ERPB "MTG signals" 1:15. Note that it is OK that signal pairs 16 and 17 on this cable are not driven because the DC's do not use these two pairs. The 17th pair is not cennected to anything. The 16th pair is received by a 100325 (which is OK with floating inputs) but the output from this section of the 100325 is not connected to anything. These 15 signals are just a direct connection to the Cal_Trig_Readout_Helper. BBB TSS section signals 16:32 are used to carry 17 Tier 1 Timing and Control signals. This is the setup: BBB TSS MBD Pair Maps (Cable MBD this to Bus TSS Driven Backplane Tier 1 Backplane Buse Pair) Input by Bus Function ------- ----- -------- --------- ------------------------ 16 1 CMC_0 H ADC Clock 17 2 CMC_2 G 2X CTFE Clock 18 3 CMC_3 F X CTFE Clock 19 4 MTG FA_0 C Read A/B 20 5 CMC_1 B Latch/Shift 21 6 MTG FA_1 A Write A/B 22 7 CMC_6 R CHTCR Clock 23 8 MTG FA_6 Not used - static drive 24 9 CMC_4 E (INV) Energy MD Bit Adrs 25 10 MTG FA_2 J Energy MS Bit Adrs 26 11 MTG FA_3 D Energy LS Bit Adrs 27 12 CMC_5 M Momentum MS Bit Adrs 28 13 MTG FA_4 L Momentum MD Bit Adrs 29 14 MTG_FA_5 K Momentum LS Bit Adrs 30 15 MTG FA_7 S Not used - static drive 31 16 CMC_8 N Tier 1 Momentum CAT2 Clk 32 17 CMC_7 P Tier 1 Energy CAT2 Clk This is the 11-JUNE-2002 Tier 1 MBD mapping of TSS Cable Bus to Backplane Bus. Note that both the BBB's and the MBD's use 10116 chips to buffer these Timing & Control signals. If any section of this chip is used, then all sections of this chip must be driven or biased. This is taken care of on the BBB by driving all 32 TSS channels. Where no useful signal is needed a static drive MTG signal is used. On the MBD there is one 10116 that we use 2 sections of but the 3rd section buffers the 18th cable pair that we are not connected to. To bias this section of this chip on the Tier 1 MBD we need to solder bridge U22 pins 11 and 12. Thus we have all sections of all 10116's on the Tier 1 MBD's either driven or biased. Connection of the Timing & Control Signals to the 10 BBB's that Distribute these signals to Tier 1. ________________________[] Feed 2 sections to first BBB | | | ___________[] Termination 15 sectopms from feed | | | |__ | _____[] slot 18 feeds M103 13 sections | | | |_____ | _____[] slot 17 feeds M104 11 sections | | | |_____ | _____[] slot 16 feeds M105 10 sections | | | |_____ | _____[] slot 15 feeds M106 9 sections | | | |_____ | _____[] slot 14 feeds M107 8 sections | | | |_____ | _____[] slot 13 feeds M108 7 sections | | | |_____ | _____[] slot 10 feeds M109 5 sections | | | |_____ | _____[] slot 9 feeds M110 4 sections | | | |_____ | _____[] slot 8 feeds M111 3 sections | | | |_____ |______________[] slot 7 feeds M112 2 sections [] = connector to BBB or Feed or Termination The feed to this is the Top Left Hand connector at the top of M103. The termination on this is the Lower Left Hand connector at the top of M103. Runs from the BBB's to the MBD's in the Tier 1 Crates from BBB's to M103 Upper Tier 1 is 6 section 9 section full length from BBB's to M104 Upper Tier 1 is 8 section 11 section full length from BBB's to M105 Upper Tier 1 is 9 section 12 section full length from BBB's to M106 Upper Tier 1 is 10 section 13 section full length from BBB's to M107 Upper Tier 1 is 11 section 14 section full length from BBB's to M108 Upper Tier 1 is 12 section 15 section full length from BBB's to M109 Upper Tier 1 is 14 section 17 section full length from BBB's to M110 Upper Tier 1 is 15 section 18 section full length from BBB's to M111 Upper Tier 1 is 16 section 19 section full length from BBB's to M112 Upper Tier 1 is 17 section 20 section full length | | BBB to first (upper) MBD ------+ | full length of raw cable to make this BBB to MBD cable ---+ In the setup used before June 2002 these cables had been 4 sections long. The Cal_Trig_Readout_Helper to DC and Thus ERPB's cable was 35 sections long. To make the Tier 1 end of these new BBB to Tier 1 MBD cables: Split the cable into pair 1:15 and 16:32 Split this back through 3 and 1/2 twisted sections From the 1:15 bunch, cut off two sections. Install 34 pin connectors on the 1:15 bunch (cable pair 1 to connector pair 1, connector pair 16 and 17 are open). Install a connector at the end of the 1:15 bunch and install another connector one section up from the end. Install 34 pin connectors on the 16:32 bunch (cable pair 16 to connector pair 1). Install a connector at the end of the 16:32 bunch and install another connector 3 sections up from the end. The Timing & Control fanout to the Tier 2 and Tier 3 crates is taken care of by the CBus Section of the 4 BBB cards in slots 7 through 10 of the Cal Trig Control Crate. The 8 MBA buffers and the 6 CA buffers and the 8 FA buffers and even perhaps the Stb and Dir buffers are used to fanout Timing & Control to the 3 Tier 2 crates and the 1 Tier 3 crate. The inputs to these BBB CBus sections are just feed in parallel so the runs from the BBB to the T2 and T3 crates must all be the same length. There are the same constraints as noted above about not letting both inputs to any section of a 10116 on the BBB or MBD "float" if any section of that 10116 is being used. ------------------------------------------------------------------------------ DATE: 28-MAY-02 At: MSU Topics: Work at Fermi with Bob to test the L1 Cal Trig readout LSB. The problem with the LSB of the L1 Cal Trig Spark readout is now clear. It is caused by pin DOUT on the unconfigured MSA FPGA's being used as the LSB of the bus that carries data to the HSROCB. So this afternoon try Configuring the Main Signal Processing Array FPGA's on the 2 Spark cards (slots 10 and 11 of M101 Middle) with the configuration file aonmct_for_spark_4_1.exo. This is the new cleaned up version of the aonmct from 17-MAY-02 that is setup for this application. This appears to have fixed the problem of the stuck LSB in the 16 bit wide path that feeds the HSRO. One thing to be careful of is that this was done when running the old standard Spark_7_2 from 5-OCT-2001. We now need to test this with the cleaned up Spark_8_2 from 14-MAY-2002. Bob reports that the Pedestal plots from L1 Cal Trig Examine now show the 1/4 GeV structure for Total Et pedestals. ------------------------------------------------------------------------------ DATE: 27-MAY-02 At: MSU Topics: Readout from L1 Cal Trig They called about 6:30 Monday afternoon. Readout from the L1 Cal Trig looked bad. I thought that they might just have pushed the VME Reset button in the L1 Cal Trig readout crate and then not re-initialized the L1 Cal Trig (to setup the VRB's and such) but there was a bigger problem. The FPGA's in the L1 Cal Trig readout (M101 Middle, i.e. the Spark's and the Cal Trig Readout Helper) had never been Configured. I.E. the power to L1 Cal Trig must have been off when they ran the Configure All Master Command File after the site wide power outage on Sunday. I.E. the readout from L1 Cal Trig probably has not been working since the power outage. So I ran the Configure_M101_All and the the L1_Cal_Trig_Post_Init.vio and the L1_Cal_Trig_Post_Init.rio and the data looked OK in the Formatted Event Dump display. So I guess that we need to add to the start up instructions looking at both the TT_Mon and the Formatted Event Dump just to check and verify that all is OK. ------------------------------------------------------------------------------ DATE: 26-MAY-02 At: MSU Topics: Site wide Power Outage Site wide power outage at Fermilab on Sunday 26. I think that this was at about 6 AM. I do not know when they called Daniel. I hope that they called him right away. They did call Philippe late Sunday afternoon with a Master Clock problem (actually with something that could not have been a Master Clock problem) but at least they got a hold of him so he could load the Gain and Ped files into the L1 Cal Trig. I do not know why he was not called earlier. Philippe was home all morning and there was no phone call. A message was sent to d0daqshifters@fnal.gov at 3pm telling that Philippe would be reachable at a different number [=Maris']. The first message on Philippe's home answering machine was stamped (I think) around 6:30pm. Michael Rijssenbeek (I think), the captain, was referring to Master Clock problems because a "Synch Error LED" on the PCC would not stay cleared after a reset. Philippe asked them to page Daniel. Only some of the muon crates were affected amd the Metro Card showed no sign of invasion. So it appeared unlikely to be a master clock problem. The earlier power outage was not mentioned at the time, and Philippe wasn't aware of it. Luckily Daniel came to the rescue and diagnosed that the master clock was not in its normal mode for synching to the accelerator. Daniel and Philippe later went through the steps of loading TT pedestals: (0) Daniel felt more comfortable first pausing all runs (1) Telling Trics to ignore L1CT, (3) Starting VME_Access (4) Loading Trics\D0_Config\RunII_L1CT_Nominal_Gain.tti (5) Loading trics\D0_Log\Find_DAC_V3_1_G_20020524.tti;13 (6) Telling Trics to stop ingnoring L1CT, (7) Starting "TT ADC Monit" to verify that pedestals were loaded Note: What started automatically after power up is Trics V10.0 Rev H instead of Rev J. Rev H has a bug that prevents "Excluding" Trigger Towers, but since there is currently no Trigger Tower to exclude, it makes no difference, and Rev H was thus left running. ------------------------------------------------------------------------------ DATE: 21:24-MAY-02 At: Fermi Topics: Work on L1 Cal Trig, Clock files to move the hickup in the 396 nsec spare marker for SMT. Switch to Trics V10.0 Rev J. Several versions of VME_Access, now V3.1 Rev G. There are currently 10 spare Term-Attn-Brd's for the Eta Index 1:4 that are all set and ready to use (pins clipped and black dot marked). In addition there are 4 more spare Term-Attn-Brd's for Eta 1:4 that have a few broken pins on each card. I will leave these at Fermi for repair at Fermi. The number of spare Eta Index 1:4 Term-Attn-Brd's went down to zero as the week went on. Daniel has been fixing them and we now have a few. Need to bring headers to Fermi to fix those with broken pins. Need to check at SiDet about the size of the anti-static pads that they use in the PROM eraser and about how much they grind off the LEMO's. Cheched this and what they are using is OK. Active area size is about 8 1/2" x 4 1/2". The input attenuator resistors on the Term-Attn-Brd's that are installed in Eta Index 1:4 (plus and minus) have been adjusted to compensate for the mistake in the Hadronic BLS pickoff resistor on the BLS cards that service Eta Index 1:8. So we will just load the nominal gains for both EM and Had for the Trigger Towers 1:4. The nominal gains are shown in the following table. Est Req DAC Code to TT Eta Gain Get this Gain ------ ------- ------------- 1 1.54 183 decimal 2 1.48 176 3 1.37 165 4 1.24 152 The legacy PROM's that we have been using have worked using Page Adrs 3 for the first lookup and Page Adrs 7 for te second lookup. This was for both Energy and Momentum PROM's. That is the address went from 011 to 111. With the new Run II PROM's we need to use the following setup for initial running: Energy Page Adrs Momentum Page Adrs ---------------- ------------------ First LU 0 = 000 0 = 000 Second LU 5 = 101 4 = 100 For both the Energy and Momentum Page Select Adrs lines the two low order bits have come from an MTG and the high order bit comes from the CMC. For Energy we need to get the LSBit to move. So on the MBD disconnect the Backplane Bus line "D" from Cable Bus signal 11, and connect Cable Bus signal 9 to both Backplane Bus signals "J" and "D". Also set both of the low order MTG generated signals low instead of hi. For Momentum all we have to do is set the two low order Page Select Adrs lines low instead of high on the MTG channels that supply these signals. Neither of the MBD cards in either M103 or M104 (the currently running racks) had terminator resistors on their Timing Bus inputs ! Why not, these are all separate feeds. Was this just forgotten a year ago ? So I put terminators on all 4 of these cards. Daniel has worked on checking in the 32 CTFE cards that are labeled for -5:-8 These will be plugged into -1:-4 -5,1 SN# 80 -5,17 SN# 124 -5,2 SN# 49 -5,18 SN# 133 -5,3 SN# 168 -5,19 SN# 68 -5,4 SN# 92 -5,20 SN# 146 -5,5 SN# 28 -5,21 SN# 150 -5,6 SN# 40 -5,22 SN# 79 -5,7 SN# 45 -5,23 SN# 167 -5,8 SN# 50 -5,24 SN# 85 -5,9 SN# 148 -5,25 SN# 142 -5,10 SN# 77 -5,26 SN# 159 -5,11 SN# 63 -5,27 SN# 121 -5,12 SN# 128 -5,28 SN# 62 -5,13 SN# 65 -5,29 SN# 134 -5,14 SN# 51 -5,30 SN# 102 -5,15 SN# 84 -5,31 SN# 52 -5,16 SN# 107 -5,32 SN# 83 There has also been work on the +9:+12 cards that will be installed at +5:+8. +9,02 SN# 203 +9,03 SN# 177 +9,04 SN# 178 +9,05 SN# 173 +9,06 SN# 171 +9,07 SN# 205 +9,08 SN# 234 +9,09 SN# 136 +9,10 SN# 110 +9,11 SN# 100 +9,12 SN# 157 +9,13 SN# 162 +9,14 SN# 41 +9,15 SN# 69 +9,16 SN# 46 There has also been work on the -9:-12 cards that will be installed at -5:-8. -9,01 SN# 272 -9,02 SN# 279 -9,03 SN# 367 -9,04 SN# 377 -9,05 SN# 274 -9,06 SN# 191 -9,07 SN# 259 -9,08 SN# 376 -9,09 SN# 267 -9,10 SN# 282 -9,11 SN# 246 -9,12 SN# 228 -9,13 SN# 252 -9,14 SN# 242 -9,15 SN# 224 -9,16 SN# 326 -9,27 SN# 232 -9,28 SN# 209 -9,29 SN# 206 -9,30 SN# 363 -9,31 SN# 219 -9,32 SN# 251 Initial pass at getting the new cards installed in | 1:4 | to run. The card that was installed at +1,7 i.e. the card that is still labeled +5,7 had 3 blown up 10H125's along the CBus connector. You could see low resistance from these pins to Gnd when probing them. The IC that had to be replaced are: U24, U25, U26. The card labeled +5,7 is SN# 105. I did not have good de-soldering equipment here. I could not clean out the hole for pin #16 so its socket pin is clipped off and just a stub in going into the via and the rest of the pin is just soldered to the top pad. This card was installed and runs OK. The card at -1,6 (current label -5,6) SN# 40 was having trouble with all its channels. The problem was the contacts were put into the connector housing in the wrong order on the cable harnes. The card at +1,7 (current label +5,7) SN# 105 was having trouble with all of its channels. Both Term-Attn-Brd's needed to be replaced. Now OK. The card at -1,18 (current label -5,18) SN# 133 was having trouble with all 4 eta's. Replaced just the first Term-Attn-Brd and that fixed it. The card at -1,32 (current label -5,32) SN# 83 was having trouble with its 2nd two eta's. Replaced the first Term-Attn-Brd and now its OK. The card at -1,28 (current label -5,28) SN# 62 was having trouble with its 2nd two eta's. Replaced the first Term-Attn-Brd with one for eta's 5:20 and now it is OK. The card at -1,24 (current label -5,24) SN# 85 was having trouble with its 2nd two eta's. Tried lots of things to fix this - different Term-Attn-Brd's. It ends up the CTFE SN# 85 has a blown up Function Address #3 receiver chip, i.e. U??. For now just swapped with the card labeled -9,24 SN# 353. I will fix SN# 85 and it will be the card that will be used at -5,24 <----- This leaves problems with: Failed Finding Pedestal Control Value for EM_TT(+ 1,17) Failed Finding Pedestal Control Value for EM_TT(+ 4,30) Failed Finding Pedestal Control Value for HD_TT(+ 2,30) Failed Finding Pedestal Control Value for HD_TT(- 1, 4) Failed Finding Pedestal Control Value for HD_TT(- 1,12) Failed Finding Pedestal Control Value for HD_TT(- 1,21) Failed Finding Pedestal Control Value for HD_TT(+ 1,25) For Thursday store these TT's are just excluded via TRICS. Trics V10.0 Rev H does not initialize the CTFE CSR register to allow direct loading of Simulated data, and this prevents the Exclude Trigger Tower Algorithm from working (Write 8,but Read back 0 in Test Data Register FA 82). Trics V10.0 Rev J was installed to intialize the CTFE CSR Register (FA 80) to value 0x81 instead of 0x01. Note the skip in revision number: There already was a V10.0.I that we never ran at DZero. Rev I happens to be a very important version, as it is the one that generated the 5k L1CT PROMs. We went through several versions of VME_Access to correct bugs on loading DAC values from Command files and to improve Find_DAC. The agregate CBUS cycle to do a Serial load of the DACs was improved which brought down the time to run Find_DAC on eta (-4:+4) from 2.5 hours to 57 mn. Find_DAC now also writes two files, one .TTI file for the commands to later load the pedestals, and one .HST with only the histogram values. The .TTI file also includes as comment the Average and Standard Deviation of the selected histogram. The current VME_Access is V3.1 Rev G. There was a problem with the HD prom at +3,6. It was put in the socket wrong. Bob cooked a new one. In addition there are 4 TT's that appear to always readout exactly zero for their EM value and their EM contribution to Total Et. These are: -4,13 -4,20 -1,20 -2,21. The TT_Mon looks fine for these Towers but their HSRO readout is zero in the EM. Bob made new PROM's to try replacing these. This fixed the problem. Bob checked the original EM Energy PROM's and they were blank. Running with beam Thursday night, +3,26 EM was hot. There were pulses coming up on the Blue cable from the platform that were about 30 GeV high and lasted for about 20 to 30 usec. So +3,26 was unplugged from the L1 Cal Trig and a note was taped to it and a note put in the Cal log book. Work on Friday to investigate the rest of the not working channels: +1,17 EM CTFE SN#64 missing comp side resistor on Term-Attn-Brd. Now OK. +1,25 HD CTFE SN#89 a grounder wire on the solder side of the CTFE shorted the output of the Term-Attn-Brd. Now OK. +4,30 EM CTFE SN#23 missing solder side resistor on Term-Attn-Brd. Now OK. +2,30 HD CTFE SN#23 a grounder wire on the solder side of the CTFE shorted the output of the Term-Attn-Brd. Now OK. -1,4 HD CTFE SN#92 was reading all zeros - could not see the problem. Swap Term-Attn-Brd's and now OK. -1,12 HD CTFE SN# 128 missing comp side resistor on Term-Attn-Brd. Now OK. -1,21 HD CTFE SN#150 was reading all 255 - there is a clear registration problem of the 12 bit DAC on Term-Attn-Brd. Swap Term-Attn-Brd's and now OK. Bob and Cal shifter said that they had seen times when all 4 TT's on the CTFE at phi 28 (neg eta) EM only readout high or at a high rate or something like that. I could not find anything wrong but just to make sure that we would not have a problem I swapped this CTFE (SN# 62) with one that is ready to go into higher eta, i.e. SN#230. Friday late afternoon. All channels in the first two racks now appear to be working OK so make another Find-DAC Run. This run of Find DAC finds good pedestals for all TT's in the first two racks. The Pedestal File from this is: \D0_Logs\Find-DAC_V3_1_G_20020524.tti;13 I did not move it from the logs directory to the configure directory. I did edit the file that TRICS calls from Init_Post_Auxi.mcf to Exclude TT's so that no TT's are currently Excluded. Friday afternoon late. The power supply chassis for the bottom crate in M103 has two bricks that look funny. The -2V and the -4.5V both have low valtage and high ripple (a couple of hundred mV). I did not have time to sawp so I hope that these live through the next week. If the -4.5V dies then TRICS will not be happy because it will not be able to load the registers in the CAT2 cards in this Tier 1 crate. Friday night there is another hot tower. This is -1,15 EM and has the same characteristics as the one Thurdsay night. It wanders between 50 Hz and 2kHz on the CEM (1,10) trigger. We labeled it and unplugged it from the L1 Cal Trig For testing SMT they wanted to move the the location in the Gap of the hickup in the 396 nsec clock. So I made two test clock files, Seq #1, for them. These are in the Test director under master_clock. The only thing that was moved in these files was the 396 nsec spare marker clock. Booted the slot #1 processor to do this and pulled its ethernet cable and pushed it reset button when we were done. It did not do any VME writes on its own accord when it booted. Tom Diehl said that he has also seen EPCIS change things on its own accord in the muon system. He has investigated and learned what EPICS components must be present for these uninvited write to happen. ------------------------------------------------------------------------------ DATE: 17-MAY-02 At: MSU Topics: Work at Fermi via Bob to test the L1 Cal Trig readout LSB. The problem with the LSB of the L1 Cal Trig Spark readout is now clear. It is caused by pin DOUT on the unconfigured MSA FPGA's being used as the LSB of the bus that carries data to the HSROCB. So try loading AONMCT_3_1 into the 16 MSA sites on the 2 running Spark cards i.e. Build A AONM's. Do this and now both VRB channels 0&1 and 2&3 are mostly even. There is some small fraction of odd in both of these channel blocks. So this is clearly poking at the problem but did not fix it. This was still running the new Spark_8_2. VRB Ch 0&1 was all odd now mostly even with a little odd VRB Ch 2&3 was all even now mostly even with a little odd ------------------------------------------------------------------------------ DATE: 15-MAY-02 At: MSU Topics: Work at Fermi via Bob to test the L1 Cal Trig readout LSB. Verify using the VME Access formatted event dump of the L1 Cal Trig that it is VRB channels 0 & 1 that are always reading odd and VRB channels 2&3 that are always reading even. Swap from the standard (since 29-NOV-2001) spark_7_2.exo to spark_8_2.exo In the 8_2 the FAST was removed from the HSROCB_Data signals to make them just like the BSF version. In 8_2 that is also some additional circuit clean up (better use of Global Clock lines) and tighter timing in the ucf. It made no difference at all, i.e. still even and odd. I looked at >25 events just to make sure that we were not stuck with old SBC data. We left 8_2 running as it is clearly on the path that development is going to follow. The trigger configuration to run for this is: commissioning --> L1Cal --> tfw_only_sr_l1cal_1.0 This reads out TFF and L1 Cal Trig and is using just a prescale to make the L1_Acpts. Next step double check what is going on by swapping DC to Spark cables and then swapping Spark to VRB fibers. ------------------------------------------------------------------------------ DATE: 7,8-MAY-02 At: Fermi Topics: Work on Level 2 TCC, Work on L1 Cal Trig Change Tick-Select #1 and how the Tick-Selects are setup, Check In more CTFE's, Get M105 M106 ready for readout, Practice running Term-Attn-Brd's from TRICS and by hand, Swap the L1CT's VBD for a SBC, Get formatted event dump going from SBC, Work on L2 TCC PCI expansion box and L2 TCC L2RS software. Exercize the new Find_DAC software from VME_Access. Change Tick-Select #1 from issuing L1 Accepts for tick 7 to tick 37. So the setup of the Tick_Selects now looks like: Tick Select: Selects Who "owns" Tick-Sel AOIT Tick or uses this -------- ---- ------- ------------------ 0 251 24 Muon & ? 1 252 37 CFT & L1 Muon & ? 2 253 10 SMT & ? 3 254 25 CFT & Muon & ? At the same time I quit using the ...rio\tts_select_tick_for_251.rii and 252,253,254. So now right in the D0_Config\Init_Post_Auxi_L1FW.rio it does the Register I/O to setup the Tick_Selects. The ...rio\tts_select_tick_for_251.rii files can be moved to ...rio\obsolete\ Cook the PROM's to start using HSRO from rack M105. Cook a ERPB_7.FUL for SCP1 This is format 82 sum check 000E 1E83 Cook a U26.NOW for U26 This is format 82 sum check 0003 F8D6 Cooked all the DC parts and just 2 more serial PROM's for erpb configuration. Racks M105 and M106 now have all the parts in them to be ready for Run II readout. Worked with 28 of the ERPB Transmit Headers made by Bob Jones groupe. 3 of them were miss-wired and 2 of them had clearly cold solder joints. Daniel has worked on checking in the 32 CTFE cards that are labeled for -5:-8. These will be plugged into -1:-4 -5,1 SN# 80 -5,17 SN# 124 -5,2 SN# 49 -5,18 SN# 133 -5,3 SN# 168 -5,19 SN# 68 -5,4 SN# 92 -5,20 SN# 146 -5,5 SN# 28 -5,21 SN# 150 -5,6 SN# 40 -5,22 SN# 79 -5,7 SN# 45 -5,23 SN# 167 -5,8 SN# 50 -5,24 SN# 85 -5,9 SN# 148 -5,25 SN# 142 -5,10 SN# 77 -5,26 SN# 159 -5,11 SN# 63 -5,27 SN# \ -5,12 SN# 128 -5,28 SN# \ -5,13 SN# 65 -5,29 SN# | Still to be -5,14 SN# 51 -5,30 SN# | preped. -5,15 SN# 84 -5,31 SN# / -5,16 SN# 107 -5,32 SN# / Was there any rework of the SiDet rework required ? Card -05,01 SN# 80 had a Vee to Gnd short. It was clearly in the vicinity of the Term-Attn-Brd for Ch #2. I removed that Term-Attn-Brd and air hosed off the card and the short went away. I do not know what was causing the short. I have now run this card under power and it appers to be OK. By hand checked the Pedestal DAC values required to get 8 counts out of the flash ADC's. Checked this with the Gain DAC set to 0 and with it set to 128. The intent was to see how big of a Pedestal DAC value was required to get 8 counts out of the flash ADC and how much the Pedestal DAC value needed to change when the Gain was moved from 0 to 128. +05,01 Card -05,01 Card 0 Gain 128 delta 0 Gain 128 delta ---- ---- ----- ---- ---- ----- 3670 3690 +20 3670 3705 +35 3720 3735 +15 3620 3590 -30 3650 3650 0 3800 3800 0 3650 3620 -30 3650 3640 -10 3670 3670 0 3740 3790 +50 3675 3670 -5 3600 3635 +35 3650 3640 -10 3650 3640 -10 3700 3775 +75 3700 3705 +5 Wednesday afternoon. Removed the VBD from the Cal Trig Readout. And then Andy removed all the 1st floor VRB equipment and cables. The SBC in the L1 Cal Trig readout is called: 0x10 (L1CAL) now has d0sbc011b The Init_Post_Auxi_L1CT.vio file was modified to remove the following !Read_VME: 0x1CFF600C ! Verification (?) removed 8-may-02 ! I need to understand this instruction While the SBC computer was initially misconfigured and not presenting VME registers to emulate the VBD control registers, every VME cycle was failing, but Write failures were not stopping the VIO command file while Read failures cause the file to abort without executing the following VRB and VRBC configuration commands. This issue needs to be understood and Trics should treat Read and Write the same way, and we need to decide _which_ way. Philippe worked with Ron to get the last event that was read in by the SBC to be made visible by the SBC. He has changed the formatted display that is available from VME Access so that you can dump the last event from the SBC. This is VME_Access V3.1.A, and the shorcut on TCC's screen has been updated to start this new version. Trics V10.0.H cannot analyze events from the SBC. The next version will be able to. Philippe was able to get the L2 TCC PCI expansion box running with separate Bit-3 optical links to each of the L2 components. However if one of the bit3 cards do not see its remote crate, L2 TCC will hang when it tries to make the bit3 driver access the card. The constraint is that all 4x bit 3 Model 618 must have it optical link plugged in and the remote VME crate must be powered up, or else the Bit-3 driver software hangs the whole system, as even the mouse pointer freezes. This freezing may be reversible if the remote crate is powered again, but this was not tested again. As part of the process, our L1 spare Bit3 Model 617 PCI module was removed from the PCI Expansion box and return this card to the box with its VME partner, and placed back in the bottom of the yellow rack of spare trigger cards. This 617 had been left in the slot labelled P6 on the silkscreen of the motherboard of the PCI expansion box when we brought the system up. Looking from the back, outside of the PCI expansion box, P1 is on the right, P7 on the left. Philippe installed two new bit3 Model 618 PCI cards in P4 and P6. We now have SN 183989 in P4 (new) SN 197674 in P5 (no change) SN 197717 in P6 (new, replaced the 617) SN 197687 in P7 (no change) Reinhard disconnected the two muon crates from d0ntmsu7 and connected them to d0tcc2. Starting today, the Bit-3 unit number assignment is as follows: Unit L2 crate 0 L2GBL 1 L2MUC 2 L2MUF 3 L2CAL Philippe also updated the L2RS software to version 2.1 revision C. This version knows how to request updated monitoring information independently from each L2 crates when the information in the Dual Port Memory hasn't been updated in a specified amount of time. This feature can also be disabled and the timeout can be changed from the L2RS' dialog menus, while it is set to 15 seconds by default. L2 TCC will only request this information if the Alpha is not in the event loop as Reinhard says it otherwise causes serious L2 application and linux system crashes if L2 TCC makes such requests to the L2 administrator mailbox while the L2 Admin software is starting up. Ran the new Find_DAC from VME_Access on 8x pairs of TT channels with the new CTFE analog front-end mezzanine boards to collect statistics and watch the behavior of the old simple algorithm while it seeking the correct DAC value with the new hardware. The Noise histogram are no longer symmetrical around the average value, and it is not totally clear which is the best DAC value to pick at this 13x DAC to 1x ADC Least Count ratio. The upper boundary of the search range had to be increased from its naive initial setting to be able to catch some of the 8 channels tested. Logfiles were generated that we can study in details at MSU. ------------------------------------------------------------------------------ DATE: 28-APR, 3-MAY-02 At: Fermi Topics: CMS Review, Work on understanding Cal Trig Timing distribution, Checkin cards from SiDet, Master Clock murdered. Restart TRICS 4 SCL Receivers to Si Trigger Count of BBB's at MSU is either 7 or 8. So this plus the 4 not in use ones at Fermi makes enough that BBB should work for Cal Trig Timing Distribution. There are 3+ boxes of the 24" pitch 34 conductor cable. Put on the web the checkin list for the CTFE cards that are coming back from SiDet. This is in the CTFE directory. Checking +5:+8 all 32 Phi. We had to install the 2nd Term-Attn-Brd on these cards. We are clipping all pins. The vertical fit even with the 1/32" G10 insulator looks OK. I want to make the insulator 1/4" wider, further back on the card. All of the SiDet work looked OK - no mistakes seen. The +5:+8 cards are: +5,1 SN# 38 +5,17 SN# 64 +5,2 SN# 72 +5,18 SN# 30 +5,3 SN# 158 +5,19 SN# 53 +5,4 SN# 24 +5,20 SN# 103 +5,5 SN# 131 +5,21 SN# 86 +5,6 SN# 147 +5,22 SN# 122 +5,7 SN# 105 +5,23 SN# 116 +5,8 SN# 61 +5,24 SN# 73 +5,9 SN# 154 +5,25 SN# 89 +5,10 SN# 118 +5,26 SN# 74 +5,11 SN# 75 +5,27 SN# 129 +5,12 SN# 97 +5,28 SN# 112 +5,13 SN# 95 +5,29 SN# 37 +5,14 SN# 44 +5,30 SN# 23 +5,15 SN# 161 +5,31 SN# 60 +5,16 SN# 114 +5,32 SN# 59 These CTFE's have the Term-Attn-Brd's with the extra 1.6 HD gain. These will go into +1:+4. On Friday, picked up from SiDet the 32 -5:-8 cards. Wednesday afternoon. The Master Clock hardware was running just fine. At 3:20 in the afternoon the slot 1 EPICS processor decided that it should start doing VME Write cycles in the Master Clock crate and thus murdered the Clock. No human asked for these VME write cycles. The VME-Metro was armed and captured it all. See the note from Daniel. Fritz was monitoring that IOC processor and knows that no one was connected to it (i.e. no one could have asked for these writes). At about 5 PM, after Fritz had finished checking things, I pulled the Ethernet connector and pushed the boot button on the slot 1 processor. We will try running with the slot 1 processor trapped in this way. The VME-Metro is armed and ready to capture any write cycles. ------------------------------------------------------------------------------ DATE: 1:2-MAY-02 At: MSU Topic: backup and archive Trics files Copy official PROM file to \\d0tcc1\trics\d0_config RunII_L1CT_Lookup_PROMs.tti Update \\d0tcc1\trics\doc release notes and syntax definition files Take snapshot of \\d0tcc1\trics directory for archival D0_Trics_II_Run_2002_05_01.zip These snapshots include a set of all latest executables, contemporary with the snapshot. They do not include logfiles. (Note: cheat a little and archive the more annotated versions of \Trics\d0_config helper command files that were never tested, but had been hadn-verified to contain the same commands as on d0tcc1). Copy this zip file to the disaster recovery directory \\d0server4\users\laurens\d0tcc1\D0_Trics_II_Run_Files Also copy archive of latest V10.0.H executable to disaster recovery \\d0server4\users\laurens\d0tcc1\D0_Trics_II_Exe_Files Trics_II_V10.0.H_exe@Dzero.zip (Note: Trigmon V2.0.C is there too) Check/update backup directory tree \\msul1a\trics to match \\d0tcc1\trics. Except for \d0_log and \exe directories which are not expected to match. Check that \\msul1a\trics\exe contains the latest executables. Capture April Logfiles for archival after Trics was restarted 2-may-2002 D0_Trics_II_Log_2002_04.zip ------------------------------------------------------------------------------ DATE: 22:26-APR-02 At: Fermi Topics: Trigger Workshop, BBB and Connector Survey, SiDet, Check Master Clock, Connect the L3<->TFW Inputs to the Dave's, Install and SBC in M101B for the L3<->TFW, Get cards from SiDet Gave talk at Trigger Workshop, on web as: http://www.pa.msu.edu/hep/d0/ftp/l1/ cal_trig/hardware/general/talk_22apr2002.pdf Need to find-make a better place for this stuff. There are only 4 not in use BBB's at Fermi. 2 are in the card storage cabinet and 2 are in M103T. There are 6 BBB's in M103T doing the CBus fanout. These 6 are all plugged in and running. The Run I M114 layout files shows 14 BBB's were in use. Installed the 9 cables (17 pair twist & flat) to carry the Fired Mask and the L3 Transfer Number to the DAVE fpga's L3<->TFW Control Path Interface. These cables are 10 sections long of the 24" pitch cable (i.e. 20 ft long). The 8 cables (that still need to be made) for the Individual Disables should be the same length. Have about 65 cable mount female Ansley 34 pin and about 100 of the 16 pin at Fermi. There are about 8 of the Ansley 64 pin connectors at Fermi. Working with Doug, Installed and SBC in M101B Slot 3 for the connection to the DAVE's in the L3<->TFW Control Path. This SBC is tied into the TOM 6U to 9U card. It booted and in tests is putting Address Strobe onto the VME Bus but so far the THE-Cards did not wake up to their cycles. Looking into how to run their peek/poke program - AM and bus width and such. Visit SiDet to verify that the process of cleaning the PROM's is not driving the schedule. It is OK. Cleaning in batch mode fits in the 12 minute erase cycle. They are processing 16 cards per day --> 2 racks per week. Got the +05 1:32 cards from SiDet. Only one of the Trm-Attn-Brd's is put on and only one set of Lemo's is clipped so I need to take care of that. Check the timing of the Master Clock wrt SE-01 using standard setup of 8 nsec and 64 nsec cables. Readings are 356, 357, 356, 357, 356, 357. From the leading edge of the 1st D-Zero BX marker to the center of the first PD Beam pickup signal is 957 nsec (i.e. 166 nsec plus 2 periods of 396 which is 790.90 nsec). These numbers match and show that the Master Clock may be 1 nsec late compared to where it was on 28-MAR-02 which would put it just where it was with the old PCC. The previous checks were 26:29-MAR-2002 and 13-Mar-2002. There was at least one more occurrence of the loss of time line programming during the past two weeks. See the Control Room operations log book for Date: Fri Apr 19 00:46:33 2002. Bring all the timing fanout cable stuff that we have. Bring card file for CTFE storage if we still have one. ------------------------------------------------------------------------------ DATE: 15:24-APR-02 At: MSU Topic: generate & check Run II L1CT PROM files Generated all 5,120 EM, HD, Px and Py PROM raw binary files Bob's coefficient choices are in http://www-clued0.fnal.gov/~kehoe/l1cal/lookup_proms.txt The WWW directory where the PROM generation documentation resides is http://www.pa.msu.edu/hep/d0/ftp/l1/cal_trig/hardware/prog_dev/ctfe_lookup/ - the PROM definition source file is ctfe_lookup/runii_l1ct_ctfe_proms_reva_18apr02.txt - all PROM files and the checksum files are in ctfe_lookup/runii_l1ct_ctfe_proms_reva_18apr02.zip - checking the file content is detailed in ctfe_lookup/runii_l1ct_ctfe_proms_reva_18apr02_checklog.txt - checking-helper DOS batch files are in ctfe_lookup/runii_l1ct_ctfe_proms_reva_18apr02_checklog.zip ------------------------------------------------------------------------------ DATE: 10:12-APR-02 At: Fermi Topics: Install new version of TRICS and Trigmon on TCC1 and make tests of the L2 Control functions, Install +-12V Power Supplies, Tests of the Dave FPGA, Talk with Fritz, Daniel, Leslie about CMC. L2 Programming Tests. Philippe installed TRICS 10.0 on TCC1. The correct version to run is 10.0 H. Details of what has been tested and what needs to be tested: New ITC - this must be working OK (used by COOR, DaqMon, Lum Server, Trigmon) Force L2 Reject - tested now via L2 Accept AONM instead of L2 Answer TRM Reset L2 Answer TRM - not tested, still also done in during SCL Initialize RIO file called as part of the SCL Init sequence. L2 UnBiased Sample - not tested, need to get the output from the TDM's working before this can be tested. New TTS Fpga Initialize - tested, this is now the default that will be Configured. Ignore/Obey L2 Global - tested L2 Data Path - tested New Trics\D0_Config - tested, except for Configure_FPGAs FileNames called by TRICS to help COOR commands New Trics\D0_Config - tested FileNames called by TRICS to implement MCF buttons New Monitor Data - tested includes minor bug fixes and new functionality Register Dump - tested good L1&L2 FW register dump file was moved to \D0_Log\RegDump\REG_DUMP_V10_0_F_20020410.dmp;2 SCT - not tested followed the change in L2 AONM card programming We still need to move to Fermi the more annotated versions of the new Control Files (which had been prepared in advance but were not accessible from fnal). We still need to delete (or pack up into \d0_config\obsolete\for_v9) all the old files that have been replaced. V10.0.H has been made the "autostart" version on 19-Apr-02 Edit the \TRICS\DCF\tts.dci to change from tts_15_1.exo to tts_16_1.exo We still need to try a full power up Configure. Need to schedule time to install pull down resistors on the TDM outputs for the Mark and Force Pass Scaler Outputs and to install wire wrap wire on the FOM++ Also Installed Trigmon V2.0.C which now displays the AndOr term programming, Geographis Section Programming, and L1 Qualifier Programming in the detailed view of the Spec Trig Display. Install the +- 12 Volt 100 ma DC-DC converters to supply M101 Top (the VIPA crate for L1 Cal Trig Readout) and M101 Bottom (the crate that for now will be the Routing Manager). The +5V input for the DC-DC converter for the Top VIPA crate comes from the Middle crate which runs from the same Power Pan as the Top crate, i.e. the top and middle crate share a common Power Pan. The +5V input for the DC-DC converter that supplies the Bottom crate comes from the Bottom crate. Talk with Fritz, Daniel, Leslie about the Master Clock: From 29-MAR-02 through 3-APR-02 there were 3 looses of Time Line Programming. The VMEMETRO was only setup and working in two of these occurrences. In both of these occurences it captured write cycles on the Clock's VME bus. Daniel verified that the Clock Gui was NOT up and running in the Control Room when these VME Writes took place. So what caused these VME Write cycles in the Clock Crate ? Daniel says that it kind of looked like it starts as the IOC doing a read and seeing that the status in some register has changed, i.e. a benign situations, and then it immediately starts VME Bus writing. Verify with Leslie and Daniel that if this starts again that we will not try to diagnose it but rather just trap the IOC processor and get it to stop all activity. Talked with Fritz, yes he has continued to change stuff. When ?? Is this why we had no more crashes after the 3-APR-2002 ? He added "logging" but when he tried to show it to me it did not work. He wants to play with it more (and I think will play with it more even though all we want is a stable system). He pushed that it must be some human doing something that has been causing the loss of Time Line programming. The protection that I thought we had is not that great. Any DZero user on either of two machines can make a "parameter page" and thus play with the Master Clock. By accident they could be playing with it. From 4-APR through 12-APR there were no additional losses of Time Line Programming. No VME Writes were captured. What changed besides the changes that Fritz made ? Setup on the TOM Card in slot 3 for the RM Processor. We need to pass BG3OUT from slot 1 to BG3IN of slot 3. This is hard to do with just a normal jumper wire because the J1 pins of slot 3 are short and just come through the backplane by a mm or so. We will use a free non-bused J2 pin a slot 3 to pass this signal. On the TOM Card this J2 pin just comes to a via. At slot 1 BG3OUT comes out on J1 pin A17. At slot 3 BG3IN comes in on J1 pin D16 but it is hard to use J1 pin D16. So on TOM Card add a jumper wire from the via for J2 pin E1 to J1 pin D16. On the backplane put a jumper slot 1 J1 pin A17 to slot 3 J2 pin E1. This routes: BG3OUT from slot 1 to BG3IN of slot 3. Verified that I could pass Bus Master-ship back and forth between the slot 1 Vertical Interconnect and a 68k processor in slot 3. This is working OK. This is basically ready for them to start using. L2 Programming Tests with Roger. Right before we left on Friday Roger managed to beat the L2 code into shape so that the L2 Admin could follow configuration and programming directions from L2 TCC. Current version is L2RS V2.0.H No test with COOR were done, no test with real data. DATE: 26:29-MAR-02 At: Fermi Topics: Work on the Master Clock, Verify the SCL Hub-End setup, Check timing wrt Tevetron beam pickup, Install VME Metro, Header parts to Bob Jones. In the PCC that we had been running until 13-March, Steve found an input protection Transorber with one side never soldered. This was on the Vee supply and could have made some noise on the Vee. He has replaced all the IC's in the principal signal chain and it has a new PLL circuit board from Sten. The "Sync Delay" in the NIM Delay Box for the PCC that we had been using for the past 2 weeks is 8+4+2. For the "old repaired modified" PCC that we will start using this afternoon the setting is 4+2. Part of this reason is that the "old repaired modified" PCC will try to run from the leading edge of the NIM RF input signal. The original PCC design ran from the rising edge of the NIM signal which means that it sees all the discriminator width noise and drift. Looking at the "old repaired modified" PCC running on the scope it appears that it is still using the rising edge of its RF Input signal. I.E. changing the width of the RF discriminator moves this PCC's RF output wrt its RF Input. We switched PCC's (to using the PCC that had been in use until 13-MAR) before we made a careful measurement of the 53 to 7.5 MHz relative phase operating range of the SCL Hub-End. So all data below is with the this old original PCC back in the Master Clock. Test of the Hub Controller that we have been running with since at least October 2001. This is HC SN# 010. This test of its operating range is done in 1/2 nsec steps. We have a 14" cable in the 7.5 MHz signal. "+" delays mean delaying the 7.5 MHz even more. "-" delays mean delaying the 7.5 MHz less. The test shows that this HC operates over the range: +1 nsec to -2 nsec at +1 1/2 get Red in some high numbered slot at -2 1/2 data is junk but no Red shows Same 14" cable setup but using the spare Hub Controller which is SN# 011 the operating range is: +2 nsec to -3 nsec at +2 1/2 all slots show Red at -3 1/2 data is junk but no Red shows This implied that the center of the operating range is the same for both Hub Controllers but that the operating range of SN# 011 is wider than that of SN# 010. If we reduce the 14" cable by 1/2 nsec then things should be setup in the center of the operating range for both Hub Controllers. So switch to using a 10" delay cable (i.e. 1/2 nsec less than 14") and retest HC SN# 010. It now runs in the range: +2 nsec to -2 1/2 nsec at +2 1/2 get Red in some high numbered slots at -3 data is junk but no Red shows We did not retest HC SN# 011 with the 10" delay cable but what we should see when we do so is an operating range of: +1 1/2 nsec to -1 1/2 nsec at +2 get Red in some high numbered slots at -2 data is junk but no Red shows Leave it running with what had been the "spare" SCL Hub-End Hub Controller, i.e. SN# 011 is installed. Things that did not get done: Full sweep of Hub Controller SN# 011 with 10" delay cable in the 7.5 MHz. Full sweep of either Hub Controller with the PCC that we have used for the past 2 weeks. The PCC that we have used for the past 2 weeks is marked "2nd" on its P3 connector an is stored in a box in the Power Supply storage cabinet. Big not understood Master Clock issues: 2 weeks ago, how was the bad PCC forcing the Sequencers into Halted state ? How did changing the PCC's move the relative phase of 53 MHz and 7.5 MHz ? Are we loosing Time Line programming ? Thursday morning is the first store with the repaired - modified PCC. As expected it has moved half an RF period. Specifically compared to the last measurement on 13-MARCH it has moved: 10 nsec early wrt the SE01 Luminosity PMT 9 nsec early wrt the down stream proton beam pickup Install 8 nsec delay cables in both the SYNC and RF input connections to the PCC. Now the it measures (wrt 13-March): 2 nsec early wrt Luminosity PMT 1 nsec early wrt beam pickup The exact numbers for Luminosity were 5 measurements of 358 nsec (using the standard 8 and 64 nsec cables). Using 8 and 8 nsec cables the numbers for the Beam Pick Up measurement were 167 + 791 (i.e. 2x 396) = 958 nsec. To install the 2 delay cables mentioned above I put the PCC into FreeRun, installed the cables, and then put it back into Normal. After putting it back into normal I walked into the MCH and all the error LED's on both Sequencers were set and the Dynamic Time Lines were gone. I read back the Dynamic TL's and they were flat at zero. Reload both Sequencers and off it ran for the rest of the store with no errors. So did moving from FreeRun to Normal trigger the loss of Time Line programming ? Thursday night after the store. Cycle Normal-FreeRun-Normal 6 times and no bad errors. 4 of the times while in FreeRun pull the inputs out of the PCC and then plug them back in so things were just like this morning. The only Sequencer errors were the expected Hold. Thursday night, restart TRICS. Friday afternoon, 29-MAR, install VME Metro in the Master Clock Crate and wait for the phone to ring. Parts and Instructions and Examples and Jig to Bob Jones x4034 on 13 South to make the DC Selector and ERPB Transmit Headers. Via Rick Hance. DATE: 12:16-MAR-02 At: Fermi Topics: Work on the Master Clock, Getting SCL Hub-End to run with the new PCC, Verify the Master Clock timing, Look at Beam Pick Off signal, Run SCT (yes), Rest of Drew's De-Mux to L2 Answ TRM Cables installed, Visit SiDet to deliver Term-Attn-Brd's, work on Dave fpga, FOM++ outputs 36:39, Meeting with Steve about new PCC, VRBC with Harry Daniel Marvin, Data I/O 2700 to Bob. Master Clock was dying about once every 3 to 20 minutes. The Sequencers would show lots of errors and then one or both of them would go into the HALT state. The errors would typically come in bursts - a few and then a few more. Typically, ST Parity was the first error to show. We could get it out of the HALT state by telling the Sequencer to Stop and then to Run. Verified that the signals from the Accelerator Rack were OK and that the Clock Rack power supplies were OK and that the slot 1 processor was not the cause of the problem. The problem ended up being the kludge PCC. We are running using the 2nd PCC module with the Sten's phase lock loop circuit board from the 1st PCC module installed in it. If this fails we do not have a spare. There are a number of issues that we do not understand, e.g. why a bad PCC could make the Sequencers go into the "HALT" state, how changing the PCC could move the phase of the Selector Fanout Time Line outputs wrt the Selector Fanout 53 MHZ output by a fraction of a nsec, what went wrong with the PCC that we have been using for the past year, how changing the PCC Sync Delay could more Selector Fanout Time Line and 53 MHz signals very slightly wrt each other. Running with the new kludge PCC made a slight shift in the relative timing of the 53 MHz and the 7 MHz coming out of the SCL's Selector Fanout. This shift which is only a nsec or less bothered the SCL Hub-End enough that it would not run, i.e. RED LED's on on SFO modules and the logic analyzer on the Test Receiver said most signals were flat line. Adding the short extension cable (9 inches) to the 7 MHz signal made the SCL work OK. Adding the long cable and it worked OK. Adding the short plus long and the logic analyzer looked OK but sometimes a few of the SFO modules on the right hand side (high GS numbers) showed flickering RED LED's. So we are running with the long extension cable added to the 7 MHz line. This is installed in the back of the Master Clock rack to keep it out of the way. Before giving the system back to the control room, we ran some SCT. This included 5k loops of all cards with all tests and another run of 1k loops of just L1 cards and allow firing on pattern "A". There were no errors shown. Need to start running this more and doing something to make errors. Talked with Steve on Thursday and on Friday. Pushed the idea that we just need stability, not adjustability, in the new PCC. Need to send a written note. During the store Wednesday afternoon, after the Master Clock was repaired check the Master Clock timing vs SE01. Made 4 integrations and measured each twice. The numbers are: 356,355 356,355 357,356 355,355 This looks within 1 nsec of the previous measurement that was on 23-FEB-2002. This was with 100% HV on the SE01 PMT. Start looking at the PD (proton down stream) beam pickoff. Having the scope on 1 V/Div is about right for this signal. Put back the 50 Ohm Terminator when not using this signal. From the falling leading edge of the Master Clock D-Zero real BX Marker to the center of the beam pickoff measures 957 nsec. D-Zero Note # 1388, "D0 Clock to Tevatron Synchronization and Calibration Procedures and Installation", page 11: "... the delay from bunch crossing at the center of the detector to the time the corresponding PD signal appears at the Clock Rack patch panel. It is comprised of strictly cable delay and delay from passive components and was measured / calculated to be 935.25 nsec at the output of the isolating transformer." This is from November 1992. So to summarize the current measurement of the Master Clock real BX Marker wrt the SE01 and the PD. The Master Clock real BX Marker signal is: 3 nsec early compared to the calculated position of SE01. 22 nsec early compared to the calculated position of DP. Get labels on cables in the Accelerator Rack and the Trompeter cables on the back of the Selector FanOut cards. Install the rest of the cables between Drew's De-Mux card and the L2 Answer TRM FIFO Cards. Dig out the final part of the L2_Helper cabling information and get the L2_Helper document corrected. Work on the Control Path to/from L3. Install cards in M101 bottom: slot 5 FOM-19 (build A) Control - Error Detection slot 7 AOM-8 (build A) Trigger Mask and L3 Disables 63:0 slot 9 AOM-12 (build A) L3 Trans Num and L3 Disables 127:64 These are all build A AONM cards with 4013L in the Main Array and 4036XLA in the BSF. The card in slot 5 needs to send signals out its MSA_Out front panel connector to the TOM_PB at slot 1 on the backplane. The cable that I made to do this are 7 1/2 ft long. On D0TCC1 made a \Scratch\Dave_Configure_All.dcf (which calls the BSF dci file itself) made \dcf\Dave.dci to configure \exo\Dave\Dave_1_1.exo into all 16 MSA locations, made the directory \exo\Dave\, made a file \Scratch\Dave_Init_Test_1.rio which calls \Scratch\Dave_Default_Init_Test_1.rii made a \Scratch\Dave_Inc_Wrt_Pntr_Test_1.rio Got as far as the 3 cards configuring OK and talking to registers but I did not make the Increment Write Pointer Test work yet. Meeting with Doug and Ron: Any detected error sets a bits in a register (error currently exists, error has existed at some point). Data in FIFO and Interrupt Enabled generates an interrupt. Details of what you see during the IAC cycle. Register to control how close Write Pointer can come to lapping the Read Pointer before Global Disable is generated. Ability to block any writes that would allow the write pointer to lap the read pointer. Fix 1,4 0,2. Meeting with Jill and Pamala Dropped off the bulk of the Term-Attn_Brds, i.e. they now have all of them for +-1 and +-5. With Bob talked with them about PROM cooking and where to put it and how long it will take. Issue of what is really going on with output 36:39 from the FOM++, i.e. the nominal L1 Fired Strobe outputs. Philippe reports that 39 is actually setup to just fire on the triggers that G.S. 31 fires on. I looked as much as I could with power on and I think we are only using 36 and 37 both of which run to the L1 Fired Strobe FanOut Box in the back of M123. Output 38 is also cabled over to the box but is not used. I need to confirm all of this some time when power is off. I need to get the proper labels on the Single Signals documentation. There is some stuff in the log book about all this, look at the entry for 17,18,19-MAY-2000 Talked with Harry, Daniel, and Marvin about the rebuild of the VRBC. Ron will now start working on the current VRBC with Daniel. Pushed the idea that we need written functional specification and that Daniel is the only one who can do it (encouraged him to get this done). Marvin has now talked with CD and they can help. Rough estimate is next fall to have the new version. Marvin has the money for 30. But not until next fall means that the current one needs to run multi-buffer. Passed the Data I/O 2700 to Bob. Philippe send him our most recent software which is Ver 6.10 from Oct 1999. Bob has practiced cooking and erasing. Looked inside the 2700 with Bob and pronounced it "not repairable by us" - too many Data I/O asic's. DATE: 27-FEB:2-MAR-02 At: Fermi Topics: Test with L2 Global, Test of L2_Helper 16_1, Request for new AOT and its setup, Meetings, VRB problem, SCL_Init now drains L2, Visit SiDet and drop stuff off, Kerberos, Master Clock Seq #1 Setup. Test with Roger and Reinhard. Ran 4 L1 Triggers and L2 was sending an L2 Accept Decision to the TFW for just the L1 that fired. This looked OK. There was a problem with an SFO but when Reinhard removed it (or used a different channel on it) then everything was OK. No problem with the L2 Answer FIFO's staying in sync. To drain the L2 TRM FIFO's add, at the end of, D0_Config\scl_initialize.rio the following line Call_File: "%CONFIG%\Reset_All_L2TRM_FIFO.rio" Before Reinhard worked on the SFO the system was hanging after a minute or two of running. It would hang waiting for an answer from L2 Global. The L2 Helper State Engine (May 2000) Register 17 read $4005. In the \Scratch directory I made a User_L2_Global.rio to switch the TFW over to using answers from Roger. To switch back you need to do a Framework Initialize (which is probably a good idea anyway. At the end of this test I made a quick test of the new Jan 2002 design of the L2 Helper. This is l2_helper_16_1.exo. It has problems: Continuously issue L2 Decisions, I did not get a change to record what state it was in, or know for certain that it was ever setup or reset correctly. In order to start running Cosmic Triggers during the Global Runs they would like a new And-Or Term that is only asserted for Tick Numbers: 43, 57, 96, and 110. These are the ticks during the two Cosmic Gaps that both SMT and CFT are alive and able to process L1_Accepts. I will make this AOT from Master Clock TL20. Note that using Master Clock TL20 this purpose requires moving its current occupant, CFT_LED_Pulser_4, from TL20 to TL16. So the 1-MAR-2002 version of the Sequencer #1 file had CFT_LED_Pulser_4 moved to TL16 and TL20 made into a signal that is asserted for ticks 43, 57, 96, 110. Note that the timing setup of this is similar to that of TL21 and TL22, i.e. the first and last of every Super Bunch. Setup of the First BX of every Super Bunch and the Last BX of every Super Bunch is covered in the 8:10-AUG-01 Log Book entry. Recall in the Sequencer #1 file, to go from Tick Number to RF Bucket Number, add 13 to the Tick Number and multiply by 7. This new And-Or Term will go into the TFW as AOT 241. Note that AOT 241 had been Outstanding L1_Accept_Limit_#1. We still have Outstanding L1_Accept_ Limit_#0 on AOT 240. A note to Scott asking him to make the change in his resources file /online/data/coor/resources/ coor_resources.xml The person who would like this new "Live_Cosmic_BX" And-Or Term is Gaston GUTIERREZ and this is an official project. The Master Clock to And-Or Term Input Trompeter Cables are 25 feet long. Verified that this new AOT was working OK, i.e. had FW_Only use it and looked to see where it issued L1_Acpt. SMT was having a problem with reading out a crate. After playing around hot swapping VRBC, Petros wanted an SCL Receiver. I gave one to him and he swapped it. Then Daniel arrived to rescue the situation. He was going to test the VRBC's and SCL Receivers and give it back to me. Meetings: Trigger Commissioning (gave presentation to Ron), Trig Workshop is 22,23 April, Run IIB Trigger upgrade 16:18 April is the Temple Review, the IIA to IIB shutdown starts Jan-2005. Visit SiDet and drop of the dremal tool and bit for cutting off the LEMO's. They say that everyotherone will need an edge trimmed a little. Drop off the PROM eraser with instructions and talk about using it. They are missing CTFE's for +5,25 through +5,32. They will look for them some more. OK, found them at D-Zero. Send note to Jill and Daniel will take them to her on Monday. Kerberos pw expired. If all that you use is crypto-card to d0mino then you get no warning that this is going to happen. To fix this, call the Helpless Desk for phone tree. Give up and send email request. This goes to Yolonda at x8118 DATE: 20:23-FEB-02 At: Fermi Topics: CTFE work at SiDet, Lincoln vs Clock, PDM-04, L2 Tests, VRBC Tests, Pickoff signal work, L2 Scalers, verify Master Clock timing. Visit SiDet on Thursday morning. Need to bring: dremel tool with bit, boxes for Term-Attn_Networks and VTC OpAmps, and eraser to SiDet Don Lincoln takes it upon him self to open up the back of the L1 Cal Trig looking for a place to put his pulser. This is right after poking around in the Master Clock rack and then describing how he was going to move the equipment around in M125. They leave their equipment and pile of cables in front of M100. For therapy I worked a little on getting PDM-04 working again. It was pulled on 29-DEC-01 because of a dead brick. It's -5.2V brick, SN# 8 from 9-NOV-1988 had died. It is the old kind of 200 Amp brick so I'm going to junk it. Replace it with SN# 28 which was returned to us after repair on 12-FEB-96. SN# 28 is a new type 200 Amp brick. All of the other bricks in PDM-04 are from the 1988 time scale. I installed the new type of AC ON pilot lamp and varistors phase to phase and phase to GND. I still need to test this unit and set it up under load. Toaster to Fermi ? Tests with Roger and Reinhard of the L2_Answers coming back from the L2 Global. I need to get the SCL_Init draining of the L2 Answer FIFO's running and get a switch over script working. Signed up for Wednesday afternoon next week. Tests with Daniel Mendoza of the VRBC that could give the L1 Trig Num to the VRB Buffers. First the bytes were in a strange order but did match the actual L1 Trig Num (except for a couple of stuck bits in the VRBC wire wrap wire). Then on the second try, the bytes were in correct order but it looked like they were and event behind. The idea was to back up one version and verify what was going on but I do not think that Daniel had time to do that. More tests on Friday night. The VME Metro board had bent over P2 pins, a very bent up front panel and a warpped card. Worked with Bob on TT problems. 3 more BLS's were found with either no pickoff parts or else backwards installed pickoff parts. The cable +1,13 HD had a short in the +HD line at the BLS end. I assume that Bob has details in his log book. Installed two more paddle boards of scalers for L2 (8 cables) M123B slots 8 and 9 top. Send a note to Adam asking him to put this adaptor boards in some kind of insulated container. During the store Saturday afternoon check the Master Clock timing. Make 5 integrations and measure each one twice (with the readout covered). The values are: 358,357 357,357 357,357 357,358 358,357. So this is within 1 nsec of the reading on 16:18-JAN-2002. I need to get the magnet conditions logged with these timing checks. DATE: 14:16-FEB-02 At: Fermi Topics: Run IIB L1 Trigger Meeting, Meetings with Jill, Paula, Bob and Daniel about CTFE Re-Work, look at some 45 Hz running, Talked with Alan about removing TCC from check list Two meetings with Jill and Paula at SiDet about getting the rest of the CTFE re-work started. Instructions are now written and on the web. Need to bring to Fermi: cables, Term-Attn_Brds, and foam and the PROM eraser. Run IIB L1 Trigger meeting, notes and a package of schematics and a proto-type Term-Attn-Brd send to Denis. I talked with Alan about removing the "check TCC" from the shifter check list. All is understood and there is no problem. I need to verify what is in the startup document about TCC, and then let Alan know that the start up document is OK and he will pull checking TCC from the check list. No work done on TFW or on L1 Cal Trig. Did watch some smooth 45 Hz global running. It is a nice time to watch single buffer mode L1 Busy. L1 = L2 Hz TFW L1_Bz L1 Cal Trig L1_Bz Worst L1_Bz ---------- --------- ----------------- ----------- 43.6 3.0% 0.5% 3.7% 42.9 3.0 0.5 3.6 46.2 3.2 0.5 3.9 43.6 3.1 0.6 3.7 The crate that takes the longest is 80 aka $50. And note that TFW is about at 2x because of reading out to both VRB and SBC. I do not know if 80 = $50 has an SBC. DATE: 10-FEB-2002 At: MSU Topic: ReStart TRICS Darien Wood called at about 11:15. "COOR has lost its connection with L1TCC and L1TCC says out of virtual memory". I got to the office and VNC connected to d0tcc1 just fine. There was no sign of TRICS. Trigger Tower Mon was an icon as expected. TrigMon was also an icon. I do not know who made TrigMon into an icon. When we left Friday at about 5 PM, the screen was in its standard configuration, i.e. TrigMon was displayed and it had the focus. I stopped Trig Tower Mon with the "q" command. TrigMon was trying to connect to TRICS. I tried to "q" TrigMon but nothing happened. I could see that it was TrigMon V1_2_C like it should be. I ended up using the "X" at the top right of the window to get rid of TrigMon. I restarted TRICS Rev D from 14-DEC-01 It started fine. I did a COOR Init and that looked fine. I restarted TrgMon and Trig Tower Mon. They were both happy and able to get their data just fine. Once TRICS was running again, Darien and company end the Run (TRICS says what are you talking about but this is not a problem) download triggers and start back up with no problem. The DAQ Expt said that there was an error window that said "out of virtual memory" that he then clicked its "OK" button and all the TRICS windows went away. He did not record any thing that was written in that error window. Philippe looked at the TRICS Log File. It just ended at 9:55 PM with every thing looking OK. This image of TRICS had been running since 29-DEC-2001 with no problem. Philippe will start to monitor the virtual memory usage of TRICS and Dan will continure to start a new log file every week (to control the size of the log file file). DATE: 6:8-FEB-02 At: Fermi Topics: ReProgram SCL SFO's, Try Splitting a CFT fiber signal to test buffering, Cal Trig RPSS Control Buttons, Hand pluser test of some Trigger Towers, Talk with Harry and Leslie, Tests with L2, Move Cal Trig Power Off Button Pulled out and reprogrammed the 16 SCL SLF's so that they will only assert L2_Reject if L2_Accept is NOT asserted. From Daniel, the file name and setup for this opperation were: The SLF EPLDs were configured using the JTAG configuration file named Slf_rev1.jcf dated 1/16/02. According to this JTAG configuration file, the name of the programming object files (POF) and their corresponding devices are: (the order matters) POF FILE NAME DEVICE (DATE) ============= ======== addr_decode.pof EMP7032S 3/11/99 slf_rev1.pof EMP9560A 1/10/02 The spare SLF card in the spare card cabinet has also be reprogrammed. We have been running the previous version "old version" since the SCL Hub-End came to D-Zero. This is the fist firmware change to any of its modules. We were careful so the same SLF card is back in the same crate slot after its new firmware was installed. The SCL SFO cards that have been reprogrammed have a green sticker on them. This shows the SCL Serial Coax Cables that are now plugged in 0 1 2 3 4 5 6 7 8 9 a b c d e f -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 00 08 10 18 20 30 38 40 48 50 60 68 70 78 1 01 09 11 19 21 31 39 41 49 51 61 69 71 79 2 02 0a 12 22 32 3a 42 4a 52 62 6a 72 3 03 0b 13 23 33 3b 43 4b 53 63 6b 73 4 04 0c 14 34 44 4c 64 74 5 05 15 35 45 65 75 6 06 16 36 46 66 7 07 17 1f 37 47 4f 67 LA There is also one spare LMR-100 cable that runs up the left side of the SCL Hub-End crate. There are many people trying to understand the reason for only the small fraction of CFT - SMT track matches. There is concern about the VRB's reading out the wrong buffer. So we split a CFT fiber optic cable and feed that signal to both its place in the CFT crate and to a SMT crate input. Then people will look to see that the events have the exact same data in both spots. Details of this analysis are in a note from Mike (fwd via Leslie) on 7-FEB-02. So far all looks OK with the data in the events. Moved the big red emergency power off button from under TCC's monitor so that it is now setup with just a small red button. The hope is that this will stop the accedental power turn offs of the L1 Cal Trig. The switch that was the big red button (now with the big red part removed) is now the ON switch at the far end. I need to get a full Square-D replacement switch for this. Wednesday night I went through the channels that Bob has marked as in trouble in his 1-FEB-2002 plots. I triggered on 20 GeV EM and readout with just the EM switches on and also with both EM & HD on. Just EM EM and HD View from Trigger Tower Switches ON Switches ON Bob's 1-FEB-02 Plot ------------- ----------- ----------- ---------------------- +1,32 d7d6 d8fe ? marked "misc CTFE+" ? -1,6 d3d3 d3ff flat EM Ped -1,14 d3d3 d3ff smaller than normal EM Ped +2,20 d0d0 cffe very small EM & HD Ped -2,24 cccd ccff ? marked "misc CTFE+EM ? +3,11 c0c0 c0fe very snall EM & HD Ped +3,18 c2c2 c2fe flat EM & HD Ped +4,17 b0b2 b0fe ? marked "HD CTFE+HD" ? +4,19 b1b2 b1fe ? marked "HD BLS+HD" ? So this looks OK from the L1 Cal Trig readout point of view. Worked with Roger and Reinhard to look at the L1_qualifiers as seen in L2 Global (via SCL and the L1 Trig Mask Fiber) and look at the L1 Mask as seen in L2 (via the L1 Trig Mask Fiber). There are a bunch of cross checks that you can do. So far it looks OK. DATE: 23:26-JAN-02 At: Fermi Topics: L2 work, L3 work All work this trip was on L2 and L3 upgrade - nothing on Cal Trig and the only thing on FW was to test last week's T&T Scaler to verify that it could be reset by SCL_Init, and to work on details of the L2_Helper engine. Yes, loading $0300 into register 12 on the new T&T Scaler does enable it to be reset by SCL_Init. What you put in the LSBit of register 12 depends on that T&T Scalers application. Meeting with Marvin and Ron and Daniel about VRBC. Test again next week and make a study of how the current pcb version of VRBC could put G.S L1 Accept numbers into the VRB's buffers. Much discussion (Marvin, Ron, Dave) about how to handle the L1 <--> L3 Control Path in the new SBC DAQ System. DATE: 16:18-JAN-02 At: Fermi Topics: SCL_Init Reset of T&T Scalers, Gated Scalers for L2_Acpt and L2_Cycles, L2 De-Mux Card test, Global Disable, test Trigger Tower signals, Master Clock check, TCC Track Ball, L2 De-Mux Answer cables, test runs for L2 Cal PP check the L2_Helper spread, Discover via Philippe's investigation that there is no way to prevent the SCL_Initialize Signal from resetting a given Tick & Turn Scaler, i.e. specifically the T&T Scaler that should never be reset. So this needs to be fixed soon. Work from Fermi and make a new version of the T&T Scaler that allows control of whether or not the SCL_Init will cause a reset. This is TTS_16_1.EXO. All the details are in the FPGA log book #4. Update the description on the web of this part to indicate that register 12 now allows control of this function. For this week for a test just hand load this part into Tick & Turn count NOT Reset by SCL Initialize Scaler. This is FPGA # 14 on the SM card in slot #21 of M123 Bottom. Check how this FPGA's register readback before trying to reconfigure it. Register Readback Register Readback -------- -------- -------- -------- 0 fff8 25 8004 2 0000 32 0001 3 0000 40 0000 8 0000 41 0000 42 0000 12 0000 43 0000 44 0000 16 0000 45 0000 46 0000 47 0000 Running with TTS_16_1.EXO in site 14 looks OK so we will leave it that way. If they FW Init all is OK. If they dead start it will just revert back to 15_1. Did verify that the NOT Reset T&T does live through SCL_Init. Drew has new code for the de-mux card. So run through its 8 channels again. Referring to the diagram from last week: width of strobe is 430 nsec and Output Measured Data Connector Setup Time before Strobe --------- ------------------------ 0:15 774 nsec 16:31 672 32:47 572 48:63 472 64:79 374 80:95 276 96:111 176 112:127 75 Re-Discover how the Global Disables are wired up Glb_Dis_0 is Non-Correlated input #0 not currently used Glb_Dis_1 is Non-Correlated input #1 not currently used Glb_Dis_2 is Non-Correlated input #2 not currently used Glb_Dis_3 is Non-Correlated input #3 TCC Pause/Resume Glb_Dis_4 is Correlated input #0 not currently used Glb_Dis_5 is Correlated input #1 not currently used Glb_Dis_6 is Correlated input #2 not currently used Glb_Dis_7 is Correlated input #3 Skip Next Work with Bob on testing Trigger Tower signals. TT eta ? phi ? looks shorted at the platform end. Lots of poking around but nothing is getting written down so there is no record of what is broken, what has been fixed, what needs testing. Connect the M123B Slot 19 Gated Scalers for L2_FW_Cycles and L2_FW_Accepts. All of the details are in the Gated Scaler List file. Get some more labels on single signals. Track Ball on TCC's Keyboard. This has been getting stuck so that it would not move vertically but would move horizontally. The ball spins on three glass inserts in the socket. Two small rubber rollers on shafts push up against the ball and turn the encoders. These rollers access the surface of the ball through windows in the socket. The "Y" rollers was pushed over on its shaft so that it hit and stuck against the side of its window. It is easy just to slide it on its shaft back into the center of its window. Check Master Clock Timing. Using the standard setup, measure 358, 358, 359, 358 nsec. Previous check was 27:30-NOV-01 and that log book entry has all the links going back. Standard setup is 64 nsec and 8 nsec cables. The current best estimate number for BX to the leading edge of the SE01 Bump in the M114 patch panel is 297 nsec. So: 358 - 64 + 8 = 302 I'm slowly becoming convinced that as the magnet is turned On/Off and Level 0 turns their HV up and down that we can see this. Solenoid ON is 100% L0 HV solenoid OFF is 70% L0 HV. Solenoid was at full current when this measurement was taken. I talked with Rich and he expects a 1 or 2 nsec move when the HV goes from 70 to 100%. Install some L2 De-Mux card to L2 FW L2 Answer Input TRM cables. Install these for L2 Answers 15:0 and 79:64. Recall that the L2_Helper gets the strobe from Roger on the 79:64 cable. For now these cables need to run to the De-Mux card in the M101 rack. Once the SBC VBD stuff is settled down then the L2 De-Mux will be in M124, i.e. in the Trig FW. So for now these cables are long. This is made of the 24" pitch 34 conductor twist-flat cable. They are 14 twisted sections long and none of them should be longer than the one that carries the strobe. After installation it's clear that these could have been only 12 twisted sections long and been long enough. Worked with Reinhard and using a program in L2_Global that just waits for an L1_Acpt and then sends an L2_Answer (pass or fail hard coded in some sequence) back to the L2 Hardware FW we watch a mix of events being accepted and rejected. This was running on Spec Trig 0 and the L2_Global program said reject to all Spec Trigs except 0. To 0 it gave a mix. Made runs to help the L2 Cal PP folks verify what event was what and that the layout and quality of the Cal Trig data was as advertised. We used the hand pulser and they recorded some data where we readout L2 Cal PP, L1 Cal Trg and the FW. For these runs we pulsed in 5 or 6 different TT's. Check for which Tick Numbers the distribution of L2 Decisions is blocked. Do this by running a Trig FW Only, include at Tick Select AOIT, move the Tick Select around, and watch on the logic analyzer when the L2 Decisions are actually sent out. Note that the split between the "L1_Acpt for BX bla could have been in this frame" and the "Current BX in this frame" is always 35 decimal =$23 just like we know that it must be. Current L1_Acpt for BX Num BX bla could This is an L2_Acpt in this have been in for an L1_Acpt Frame this SCL Frm with L1 BX Num ------- ------------ ------------------ $14 $90 $04 15 91 05 16 92 06 17 93 07 18 94 08 19 95 09 1a 96 0a 1b 97 0b 1c 98 0c 1d 99 0d 1e 9a 0e 1f 9b 0f 20 9c 10 22 9e 11 <-- waited one tick 22 9e 12 23 9f 13 25 02 14 <-- waited one tick 25 02 15 26 03 16 28 05 17 <-- waited one tick 28 05 18 So the first one that we skipped is $9d. The first one that we should have skipped is $07. So it needs to move forward by 9, i.e. hold the pattern of ticks that you will not use to advertise L2 Decisions for 9 more steps before it is used to actually block the distribution of an L2 Decision. The delay in the current L2_Helper is: unsigned 25 logical left. Bring more kleenex next week. Things to think about: Are we Draining the L2 FW Input TRM's at SCL_Initialize time ? SCT are we going to get back to running this ? Known Issues: L2_Helper Time Zone Spread Scalers State Engine L2_TRM BX Clock of input data Exactly how does it sync its FIFO vs how do we want it to. Talk with Marvin and Daniel about getting L1_Acpt BX number put in the VRB buffer header with the data. What do we need L3 Trans Num for once we have only SBC running ? DATE: 10:12-JAN-02 At: Fermi Topics: Meeting with Ted, Work on L2 FW, VRBC Test, a little work on Cal Trig Towers, Test receiving L2 Answers from L2 Glb. Visit Ted and drop off a page describing the change we would like in the SLF. He thinks that it should not be a problem (but you never know until you try). Get disk from Ted Friday afternoon with Daniel and verify how to download the SLF. The L2_Helper was built with Xilinx m2.1 (but m1.4 BitGen). The L2_Helper_ _State_Engine was built with Exemplar Logic Leonardo - V4.1.3 on Desmo. Used Modsim. Need to print the 2nd page of Timing Signal Processor. L2_Helper knows the Current to L1 Spread and it knows the wrong number. Note that the current L2_Helper asserts the L2_Maginot signal for one tick during the L2 Decision Cycle after the L2 TRM's have been Read. The VHDL says that this is to "clock data into the Monitor Data Shift Registers", (but on which cards ?). L2_Maginot is routed to M122 Bottom P1_TS_11 and to M123 Mid P1_TS_11. A note in Timing Signal Generation and Distribution says that this signal is not used in M123 Mid. But who uses it in M122 Bottom ? The BSF FPGA Programming file says that the L2_ TRM cards map P1_TS_11 to HQ_1 and that the L2_AONM and L2_FOM cards also mapping P1_TS_11 to HQ_1. So verify how the BSF mapping of P1_TS to HQ is actually setup on the cards in M122 Bottom. M122 Bottom FPGA #17 Register 16 L2_TRM's slots 2,3,4 all read $2220 L2_AONM's slots 6,7,9,10 all read $2420 L2_FOM's slots 12,13,16,17 all read $2420 So what do L2_TRM, L2_AONM, and L2_FOM actually do with HQ_1 ? check the sch. OK in L2_AONM it is used to clock the beam crossing history shift register and to enable the scalers to increment for only one tick (i.e. count only once per L2 cycle). All this sounds rational but the written descrition of L2_AONM is wrong - I will fix it. In the L2_TRM two HQ signals are used to move the signals along. In L2_TRM HQ_1 (which comes from P1_TS_11 which comes from L2_Helper Maginot Line signal) is used to increment the read address pointer, to clock the beam crossing history shift register and to enable the scalers to increment for only one tick (i.e. count only once per L2 cycle). In L2_TRM HQ_2 (which comes from P1_TS_13 which comes from L2_Helper Input_TRM_Read_Enable) is used to clock the term signal output latch. The Maginot Line pulse comes two ticks after the L2 TRM Read pulse. This makes sense to setup the read pointer for the next L2 Cycle. The L2_TRM documentation is just totally screwed up. It does not describe how the L2_TRM works, and it has lots of L1 stuff in it which is totally incorrect. The L2_TRM documentation is incorrect about the HQ lines, about what increments the read pointer, about how the output latch works, about how the mux works. L2_TRM documentation need a serious rewrite. Because this document is screwed up so is the L2 Framework Block diagram. L2 FW Block Diagram needs to so a seperate line to increment the read address pointer in the L2_TRM's and it must loose the Maginot Line controlling the Select Test Register B. It's also clear that the Timing Signal Generation and Distribution file is wrong - i.e. P1_TS_11 is used in M123 Middle. Maginot line is a very very bad name for this signal. Clearly this documentation was not kept up to date. The L2_Helper scaler that is not working is refered to in the current L2_Helper document as "(#6) Number of BX Spent Waiting in L2 BAD State". This appears to count at BX rate. But the signal that gates this scaler is "Waiting_for_ L2_Bad" which should only be asserted in the state of the same name. This signal, Waiting_for_L2_Bad, comes outside of the L2_Helper as MSAOut_10 which is mapped to P1_TS_9 in M122 Bottom. Connect up the rear Paddle Boards for the L2 Global Answer TRM's. This includes the 8 Strobes going to these paddle boards from L2_Helper and the one Stroble from L2 Global going to L2 Helper. The one copy of Strobe from L2 Global is coming from L2 Global Answers 64:79 TRM paddle board connection. How to switch from running without L2 Global to looking at answers from Roger: In the L2_Helper M122B, slot 20, FPGA site 4 State Engine Control Reg #16 load a 1 to bypass L2 Global load a 0 to use L2 Global Answer Auxiliary Controls Reg #18 load a 1 to have TCC generate L2 Answ Strb load a 0 to use the Strb from L2 Global (note that the current L2_Helper Document is wrong about how this works) In the L2 Answer TRM's M122B slots 3,4 all 16 FPGA sites For COOR-TCC supplied L2 Answers we have been running with Register 16 set to $02 i.e. select "Reg A" for output. Program Register 16 with $00 to select "ByPass" or program it with $01 to select the FIFO. Yes, we see data from the d0-mux card. We are looking at the L2_Answer TRM in slot 3, i.e. for Answers 64:127. We are looking at 64:67. L1 (and thus the L2 Hardware FW is running at 2 to 5 Hz and if we read Reg 36 when with By-Pass data selected we typically see something like aa55 or 555a or that kind of thing. The Answer from L2 is switching between 5 and a at 1 Hz. If we use FIFO data then I see a5a5 or 5a5a. I think that all of this makes good sense. Study the de-mux card output This is what we were seeing from the de-mux card. --------- ------------------------------- \/ Data /\ --------- ------------------------------- ----- | | STROBE | | ----------------------------- ------ | | | | ->| |<-- Strobe | | | Width |<---- Setup --->| | Time | Output Measured Data Connector Setup Time before Strobe --------- ------------------------ 0:15 508 nsec 16:31 408 32:47 308 48:63 208 64:79 108 80:95 8 96:111 -92 112:127 -192 Measured Strobe Width is 45 nsec. So where are there problems in the L2 Hardware FW: L2_TRM documentation is a disaster. L2_TRM must do something about its BX clocked input latch must understand it re-sync and drain out logic. L2_Helper must fix its "spread" for picking legal L2 SCL Frames. Recall on the TRM, the MSA Out vs. MSA FPGA # mapping is as follows: MSA_Out MSA FPGA # ------- ---------- 3:0 1 7:4 5 11:8 9 15:12 13 19:16 2 23:20 6 27:24 10 31:28 14 35:32 3 39:36 7 43:40 11 47:44 15 51:48 4 55:52 8 59:56 12 63:60 16 Friday VRBC Test: Problem because someone left SBC boot code that did not work. Problem because both SBC and VBD were reading the FIFOed L3 Trans Number but taking this into account the FIFOing looked OK. At 75 Hz rate it would hang L1 Bz after about 5 seconds of running. Read the VRB and VRBC Status Registers after the hang and see: VRB's $40 once and the rest $00 VRBC $155 once $15d 4 times $1dd 2 times New batteries in the Cal Trig thermometers and the flukes. L1 Cal Trig work. +1,24 EM and -4,21 HD are the two hot towers from Run I that were still hot in the beginning of Run II and that we have been running with their blue cables unplugged. These two Trigger Towers each have a single Cell that is hot. We know the cell from Run I work. So we cut that pin off the Run II Trigger Tower BLS Summing Network and we have these blue cables plugged back in. Changed my mind and pulled +1,24 back out. Will ask Bob to plug it in on Monday when they can watch the rates. DATE: 9-JAN-02 At: MSU Topics: Hardware Work List L1 Calorimeter Trigger: ----------------------- Run II CTFE Receiver Cards Final verification with Bob that the gains are correct. Write new instructions for making the 2 types. Redo the money for a second pick place setup. Give Hughes the documents and to go ahead to assemble. Expanding in Eta Practice installing the Receiver Card cable harness. Write instructions for installing the Receiver Card cable harness. Setup with Jill getting this work done in bulk. Cooking the Run II PROM's Get understanding and a sign off on what we are putting in the PROM's. Verify that this fits in with how the hardware can do page addressing. What cooker to use ? Get it tied up to a computer and write a program to automate it. Get the data file format to Philippe. Get labels printed for the PROM's. Timing and Control Signal Fanout Is this only for 396 nsec running or is it for 132 nsec running ? Need to Fanout both the Cal Trig and the DC-ERPB stuff. Where to put the T0 point in the layout and then match the cables. How do do this without disturbing the running system. Cooling system Bring the fan back up to normal speed. Push on people to actually close the doors. Need to check out the drip and safety system for the rest of the racks. Readout from the L1 Cal Trig Need to add Header/Trailer for L2. Need to add Seed Masks. Need to implement the "monitor capture" of HSRO data. Need to speed up by 2x. Routine Cal Trig Operation Need to get the Voltage Monitoring working. Hardware is mostly tied up but still need software. Need to re-start routine repair of the power supplies. Help figuring out the cabling and bad channel issues. Longer term Quadrant Terms ..... Design and get CTRO cards working to readout other stuff from Cal Trig. Support French and Columbia work on Run IIB Trigger Framework ----------------- L1 Hardware Framework The FOM++ scalers are "counting" the L3 Trans Number bit assertions instead of the number of times that the L1 Qualifiers are asserted. Investigate and Finish the per L1 Spec Trigger Mark & Force_Pass function of the FOM++: cabling, special wiring on the FOM++, FPGA functionality. Investigate and make work the "Capture Monitoring Data" L1 Qualifier: cabling, special wiring on the FOM++, FPGA functionality. L2 Hardware Framework Connect two monitoring scalers to the L2 Hardware Framework. These are the Count the Number of L2 FW Cycles and the Count the Number of L2 Accepts scalers. See 12:15-DEC-2001 log book entry for details. The scaler in the L2_Helper that counts the overall number of ticks that the distribution of the answer is delayed because of L2_Busy is not working. It just counts at BX rate. L2_Helper is setup with the wrong Current to L1 Time zone spread. Need to fix this before serious L2 Multi buffer running. Clean up L2_Helper documentation. L2_TRM has an L2 Answer input latch that is running from BX Clock. Need to sync the L2 Answer Strobe to this to be safe. Major documentation clean up needed since the split with L1_TRM. Level 2 Support Work Get the L2 Global to Trig FW link running. They have/need new FPGA code their de-mux. Need to figure out where to put their de-mux module. Need to look at some of their data again after de-mux fix. Need a day to re-learn the L2 TRM module in detail Need to add COOR control of simulate vs use L2. Add some SCL Geo Section L1 Trig Number to the fiber with L1 Fired Mask. Need to make a FanOut for the SCL Geo Section L1 Trig Number. How to cut up a THE-Card to add more inputs. What Main Array FPGA to stick this data into. Need to make a little receiver mezzanine Spares of the special THE-Card. How to test. Other Systems Hardware Work --------------------------- Multi Buffer VRBC tests, review, design help Master Clock What has become of the Run II PCC module ? Contact Steve Chappa Need to start using the beam pickups. Routine verification that timing has not moved. SCL Hub-End do we want to add one AND gate for protection when ?