D-Zero Hall Log Book for 2006
-------------------------------
The most recent entries are near the beginning of this file. This file
begins in January 2006. This file contains both Trigger Framework and
L1 Calorimeter Trigger entries. Earlier D-Zero Hall Log Books are on the
web in one of the following directories:
http://www.pa.msu.edu/hep/d0/ftp/l1/framework/logs/
http://www.pa.msu.edu/hep/d0/ftp/run1/l1/inventory_logs/
------------------------------------------------------------------------------
DATE: 15-DEC-2006 At: MSU action at Fermi TOPICS: Level Zero Luminosity
And-Or Terms Out of Sync
While watching the system after installation of the L1_Acpt timing change
we noticed that the TFW could not lock onto the block of And-Or Terms from
the Level Zero Luminosity System.
Philippe saved a couple of sweeps of TrgMon display Thursday morning before
work was started to change the L1_Acpt latency. He noticed that the And-Or
Terms from the Luminosity system were already not working at that time.
This was at 9:51 Chicago time Thursday morning 14-DEC-2006.
It ends up that the reason that the TFW could not lock onto the Luminosity
And-Or Terms is because the Luminosity System was not sending a Sync Gap
signal on their And-Or Term Cable. The reason that they were not sending
a Sync-Gap signal is because they had pulled out a Lemo cable from their
NIM electronics stuff. Dean worked with the Luminosity person and figured
out what was wrong with their stuff on Thursday evening.
It ends up that Bill Lee does log TrgMon at Fermi. He dug back through this
log of TrgMon and determined that the TFW has not been locked onto the And-Or
Terms from the Luminosity System for about the past 2 months. I forget the
date - but the exact time and date when they pulled out this Lemo cable from
their system is known from looking back through Bill's TrgMon logs.
So how was the TFW trreating the Luminosity System And-Or Terms during this
period when Luminosity System was not sending Sync Gap to the TFW ? We
took a couple of minutes between Stores and had them pull the cable again an
looked at some registers: M123 Top Crate Slot 2 FPGA Chip 2
Reg Adrs 8, 9, and mostly 10. What we saw is:
Normal Running (they are sending Sync Gap)
Reg 8 Reads $000f
Reg 9 Reads $0000
Reg 10 Reads $1018, $171d, $1808, $1c0a, $171f
Cable Pulled in their system (they are NOT sending Sync Gap)
Reg 8 Reads
Reg 9 Reads $010c 5 reads all the same
Reg 10 Reads $8080 11 reads all the same
So the TRM card in the TFW was continuously trying to re-lock. With no Sync
Gap signal ever coming from the Luminosity System, it never got past the
first step in the re-lock process. Thus the write pointer and read pointer
were both aimed at FIFO location zero. It is real dual-port and thus they
were writing to location zero and the TFW was reading from location zero.
Thus there was zero FIFO delay in the And-Or Terms from the Luminosity System.
Thus the Luminosity System And-Or Terms were being used to make the L1
Decision about 21 ticks before they should have been.
------------------------------------------------------------------------------
DATE: 14-DEC-2006 At: MSU action at Fermi TOPICS: Move TFW to issue
L1_Acpt 3 ticks later
The following work was done to move the L1_Acpts 3 ticks later:
Move into place the new Time Line file for Master Clock Sequencer #1.
working in /online/config/trg/master_clock
ls -la
-rw-rw-r-- 1 d0l1 d0run 99394 Apr 10 2003 clk_sequencer_1_10APR03.txt
-rwxrwxr-x 1 d0l1 d0run 78 Mar 30 2001 clock.startup
-rw-rw-r-- 1 d0run d0run 0 Oct 11 2004 l3xdaq_reset
drwxrwxr-x 2 d0l1 d0run 4096 May 25 2006 obsolete_files
-rw-rw-r-- 1 d0run d0run 723 May 5 2006 sqlnet.log
drwxrwxr-x 2 d0l1 d0run 4096 May 25 2006 test
The files: l3xdaq_reset and sqlnet.log should not be there.
I do not know who put them there. Note that l3xdaq_reset is
zero bytes.
Move the current time line file for Sequencer #1, i.e.
clk_sequencer_1_10APR03.txt to the obsolete_files directory.
From the test directory copy clk_sequencer_1_25MAY06.txt
to the main /online/config/trg/master_clock directory
cp ./test/clk_sequencer_1_25MAY06.txt ./
continuing to work in directory /online/config/trg/master_clock
rename clk_sequencer_1_25MAY06.txt to clk_sequencer_1_14DEC06.txt
diff ./clk_sequencer_1_14DEC06.txt ./test/clk_sequencer_1_25MAY06.txt
They are the same.
diff ./clk_sequencer_1_14DEC06.txt
./obsolete_files/clk_sequencer_1_10APR03.txt
There are the expected differences and only the expected differences.
That is:
14DEC06 file:
-------------
! Current Rev. 25-MAY-2006
! 25-MAY-06 D.E. We are moving the L1_Acpt latency so that the L1_Acpt
! will be issued from the TFW 3 ticks later than it has been for the past
! 4 years. All of this L1_Acpt latency change is taken care of in the
! TFW itself except for 3 And-Or Terms that are generated simply as Time
! Lines in the #1 Sequencer. The offset for these 3 time lines will need
! to be increased by 21 RF Buckets, i.e. 3 ticks x 7 RF Buckets per tick.
! The three time lines, which directly become And-Or Terms, and thus need
! to be adjusted are:
!
! Time Line 20 Ticks 43,57,96,110 Live Cosmic BX And-Or Term 241
! Time Line 21 First Interaction in any Super Bunch And-Or Term 249
! Time Line 22 Last Interaction in any Super Bunch And-Or Term 250
!
! This change is implemented by:
!
! change Live_Cosmic_BX_Dl from 223 to 244
! change Fst_BX_in_SB_Dl from 223 to 244
! change Lst_BX_in_SB_Dl from 223 to 244
Assign Live_Cosmic_BX_Dl = 244 ! The delay was adjusted to center this
Assign Fst_BX_in_SB_Dl = 244 ! The delay was adjusted to center this
Assign Lst_BX_in_SB_Dl = 244 ! The delay was adjusted to center this
10APR03 file:
-------------
! Current Rev. 10-APR-2003
Assign Live_Cosmic_BX_Dl = 223 ! The delay was adjusted to center this
Assign Fst_BX_in_SB_Dl = 223 ! The delay was adjusted to center this
Assign Lst_BX_in_SB_Dl = 223 ! The delay was adjusted to center this
Now that we have coppied the new Sequencer #1 time line file from ./test/
to the main directory, delete from ./test/ clk_sequencer_1_25MAY06.txt
rm ./test/clk_sequencer_1_25MAY06.txt
The Master Clock files are now setup so that its Sequencer #1 can be
re-loaded for running with the L1_Acpt 3 ticks later.
Now edit the files on TFW TCC that move it from operating at a spead
of 37 to a spread of 40:
Edit the .dci files in the dcf subdirectory on TFW TCC.
edit \dcf\tts.dci change from _17_3 to _19_1
edit \dcf\l2_helper.dci change from _18_1 to _19_1
edit \dcf\l1_trm.dci change from _7_1 to _9_2
edit \dcf\scl_helper.dci change from _8_1 to _9_1
Edif the Boot_Auxi.mcf file in the \D0_Config\ directory
edit \D0_Config\Boot_Auxi.mcf change the Time Zone Spread from 37 to 40.
Now the TFW TCC should be ready to do a full configuration of the
TFW FPGAs and then Initialize. We do not need to re-configure the
Routing Master FPGAs.
Background information about this L1_Acpt timing move is in this year's
logbook at:
Log book entry for 23:27-MAY-2006 starting under the Thursday
section of this entry:
- Details of the tests of the spread 40 TFW firmware.
- Note about the new time line file that must be used with
the Master Clock Sequencer #1.
Log book entry for 18-MAY-2006 This is the bulk of the information
about making the change:
- There are 4 FPGA designs running in a total of 178 FPGAs
sites that must change. There is a table listing the FPGA
designs, their versions ID number for spread 37 and spread 40,
and the sites where they run.
- There is a note reminding us that Boot_Auxi.mcf must change
its Time_Zone_Spread message.
- This log book entry also has log book clips from the previous
L1_Acpt timing changes in Sept 2002 and June 2001.
------------------------------------------------------------------------------
DATE: 9-DEC-2006 At: MSU action at Fermi TOPICS: Stuck VME Cycle in M122
We have not had the problem of "a stuck VME cycle" in the M122 top
crate, i.e. the Foreign per Bunch Scalers crate (scalers for the
Luminosity system) since early in August but it came back tonight
right as the Store was going in.
It was discovered when the DAQ Shifter issued the command to
Initialize the TFW. It took me longer than necessary to figure out
what was going on because I have not seen this problem for the past
4 months and I had to get to the office to look at the system to
understand the problem.
If this happens again, the sign is still on the front of M122 telling
people how to get the crate going again. Philippe and I will put this
back on our list of things that need to be fixed.
A current theory is that this is the only crate with cards in all 21 slots
and thus is has a heavy load on the backplane 54 MHz differential distribution
line. The Per Bunch Scaler cards in the crate do not to High Speed Readout
so I think that the only use that they make of the 54 MHz is to run the VME
State Engine. If the 54 MHz signal is not in good shape then maybe the VME
State Engine sometimes sees extra clocks (edges on the 54 MHz) and thus
rushes through doing the steps in the VME cycle (e.g. committing the card to
do a cycle before it is clear that it should). The solution my be just to use
a terminator on the 54 MHz pair that it optimized for a fully loaded
backplane. We need to look in an old paper notebook from 199x to find that
information.
------------------------------------------------------------------------------
DATE: 6,7-NOV-2006 At: Fermi TOPICS: SCL Status Cable to the L1 Cal Trig
Sidewalk Test Stand, Cal 5k SCL signals,
SCL Receiver stock, ECL Box,
Pulled out most of the old $4F status cable that had goes to Dean's 5k Cal
Test Stand but had then been taken over by someone and used in the sidewalk
cal trig test stand. It had been turned into a big ball of dirty crushed cut
and then taped up cable. I pulled out all of this old $4F cable except the
part that is actually in M124 (which is labeled and tucked out of the way.
Work to clean up and verify that the "official" $2D SCL Status cable to the
L1 Cal Trig Test Stand is all working just fine. I rerouted this cable so
that it is no longer where it is going to be easily crushed. Looking from
the sidewalk end with a volt meter it tests out just fine. I verified that
it is plugged into the correct place at the Hub-End and got some additional
clear labels onto this status cable.
With the newest setup of the Cal 5k Tests Stand (that now uses SBCs for
"real" readout of its data to L3) Dean was not getting triggers on $4F.
It's 99% clear that the problem was that I had a criss cross in the $4E
and $4F long fiber optic cables. This all worked before because Dean's
trigger configuration file for this was using both $4E and $4F in exactly
the same way. But in the new setup only $4F is being used (at least in
the initial tests). Note also the trick that Dean is doing by having two
Geographic Sections in the COOR Resources file that both resolve to $4F,
one is Non-Readout for use with the old setup, and the other is L3-Readout
for use with the new system. The COOR Resource file holds both of these
definitions so on the fly by downloading different trigger files one
can change the characteristics of the Geographic Section (Readout vs
Non-Readout).
I pulled the SCL Receiver from the logic analyzer test setup on top of the air
conditioner so that Dean has access to one next week if he finds that one of
his is dead. The SCL Receiver situation has gotten out of control. I need to
contact all of the groups and Ted and find out what is going on.
The back door is off of rack M107, the TAB GAB crate rack, and the MSU ECL
Box that was providing the external And-Or Term for a scope trigger for Dean
and company is gone. I assume that the Muon trigger people may have taken it.
The And-Or Term extension cables are also back in the cables that plug the
muon trigger and the cal-track match trigger into the And-Or Term patch panel.
After whining at people about leaving batteries in equipment I found that I
left the batteries in our Fluke clip on DC current meter probe for too long.
They have rotted batteries leaking junk all over the place. I pulled it apart
and cleaned it up in hot water. I think that everything survived except for
the battery holder itself.
Bring back to MSU the timing and control signal checker card for the ADF Crate
and the label maker.
------------------------------------------------------------------------------
DATE: 13-OCT-2006 At: Fermi TOPICS: Replace a fan in the Routing Master
power supply chassis
The left hand (viewed from the front) front panel fan in the Routing
Master power supply chassis had stopped turning. This is TFW power supply
chassis SN# 11. The easiest way to swap these fans is to hot glue the 6-32
nut and lock washer to the bottom mounting holes on the new fan. That way
you only need to move the power supply chassis 3 or 4 inches forward and
you can get enough space to change the front panel fans.
Things started back up OK, i.e. the TFW cards in the Routing Master crate
configured with no problem and the RM SBC application program must have been
running at some level because it was polling the TFW cards (as seen via
their VME activity LEDs). But runs would not go and the DAQ shifter could
not ping the RM SBC. The L3 folks booted the RM SBC two more times and then
everything ran OK.
At this time all other fans in the MSU crates look OK. Today I considered
changing (but ran out of time and did not change) the contactor box that
feeds M101. I would like to change the current M101 contactor box for a
bigger nicer one that I kept from the old L1 Cal Trig.
------------------------------------------------------------------------------
DATE: 4:6-OCTT-2006 At: Fermi TOPICS: PMB-16 tests at PAB, spare TFW
power supply chassis, M101 fan not running,
Routing Master power supply fan not running
Brought the 2 channel PreAmp setup with power supply and input cables
to PAB. They have the steel NEMA box mounted on the cryostat head plate.
Noise level looks OK when the pickup probe is in the cryostat. Bring all
of the stuff back to MSU to move to 16 channel test before assembly. Dean
very nicely gave me 96 ICD type PreAmps with their feedback caps and
resistors pulled off.
Got back the +3.3V brick for the second spare TFW power supply chassis.
This +3.3V brick had been lent to CFT CTT about a year ago but they are
finished needing it. This is brick number ASTEC model VS3-D1-D1-20
Serial Number #96390261. This is TFW power supply chassis SN #2.
Find yet some more spare or early version Patch Panel Cards and 8
clearly early version (can not be used in the real system) ATC Cards
out on the sidewalk. This stuff appeared since the last time that I
completely cleaned up our stuff on the sidewalk. I expect that it was
brought down by John and company from their production efforts. I box
and labeled it and put it in our locked storage cabinet with the rest
of the spare L1 Cal Trig BLS Transition System parts. I think that the
early version ATC Cards had OK BLS trace stuff and bad LVDS stuff.
Thursday night during a walk through I noticed that the main air circulation
fan in M101 was not running. Waited an hour until the end of the Store and
then investigated the problem. The fuse up in the contactor box for the phase
of the 208 feed to M101 that runs the blower had opened. Only the blowers
run off of this phase. Rotating the blower impellers by hand they felt fine.
Replaced the fuse and started them running again. The motors sound fine.
After one hour they do not feel hot at all. Friday morning checked both
motors again and they do not feel hot. Borrowed Tim Martin's clip on AC
current meter and the blower motor phase reads 9.4 Amps. Each motor is
rated at 5.2 Amps.
How long was this motor off ? It most likely blew the fuse at the last
restart which I think was after the TFW was accidently triped off when some
one was checking the exposed AC in the SCL copper to fiber panel on top of
M122. That accidental trip off of the TFW happened about the first of
September. If that's true then I missed this problem on my last trip to Fermi.
To add confusion to all of this, there is also a dead fan in the power supply
chassis for the Routing Master. I need to get this fixed but it is not urgent.
The other fans in that chassis are running OK and there is very little load on
this set of supplies.
I asked again at Fermi about money to get the power supply chassis for
the Wiener 6U VME-64x crate that came back from Saclay repaired/modified
so that it can be a spare crate for the ADF-2 system. No answer about
this so far.
------------------------------------------------------------------------------
DATE: 13:16-SEPT-2006 At: Fermi TOPICS: Worked on the
Meetings at PAB. Decide to make a noise test in the BO cryostat as soon
as possible - on the order of within the next two weeks.
Sent note to the L1 Cal about Excluding TTs.
------------------------------------------------------------------------------
DATE: 24:26-AUG-2006 At: Fermi TOPICS: Worked on the SCL Hub-End, Tested
TFW spare Power Supply, Put current
firmware into the spare SCLD card,
Excluded +5,9 HD
Take to Fermi two spare fans for cooling the transition module section
of the SCL Hub-End crate. This was the D-Zero Workshop week in Manchester UK.
I replaced the broken fan under the Status Concentrator cards in the
SCL Hub-End crate. As you stand in the back of the M124 rack it is the
fan on the left that was replaced. By this trip the old fan had quit
turning altogether. The thermometer temperature senssor is now
possitioned right between two Status Concentrator cards near the top
of the cards by there "Spare 1" connectors. It reads about 95 degrees F
with the back door closed. I think this is the hotest point in the
air flow that I can access.
The SCLD card in the spares cabinet is SCLD SN#2. Burn into it the
current version of the SCLD firmware. Use the MSUL1A computer to do this
before I bring this computer back to MSU. This is the 9-MAY-2006 version
of the SCLD T5 firmware, scld_t5.exo. With the Xilinx JTAG programmer
use: erase before programming, verify, and PROM parallel mode.
The checksum from the Xilinx "iMPACT" programmer was 0031c2e33.
The two spare TFW Power Supply Chassis at D-Zero are: SN#2 and SN#4.
TFW Power Supply SN#2 is the one that has had it +3.3V bricks
removed and lent to CFT in the fall of 2005. I think that they
are finished with them and I need to get them back and prove
the SN#2 is still a good spare TFW power supply.
TFW Power Supply SN#4 is all put togther and ready to use.
I ran it, with no load, for 1/2 hour and it looks all OK.
Friday evening the L1 Trigger rate went nuts. It was clearly a L1Cal
trigger that was causing the problem. We could see it in the normal big
Cal event display monitor. The problem was in both the trigger and in
the precision readout. It lasted for about 45 minutes or so and then the
Captain (Norm) decided that we should try to get rid of it. It was all
from HD and in the precision readout it was all from just one layer of the
Cal.
I edited the file
/tcc/L1Cal_IIb_Work/Config/Excluded_Trigger_Towers.msg
to point the Exclude finger at +5,9 HD and then executed this file as
a "Self Msg" file from the TCC Com File menu. The trigger rate instantly
returned to normal. Looking at this BLS signal on a scope (which is what
we did to verify the TT eta,phi of the noise) you see a triangle waveform
of 200 or 300 mVols with a period of 8.8 or 9.0 usec. The sharp edge of
the triangle comes first and then it falls off.
For reference on Excluding at TT look in:
www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/tcc/l1cal_iib_tcs/config_files/
Bring back to MSU:
the MSUL1A computer with the ADF-2 production testing software
the Saclay Channel Link Test Receiver
the Saclay BLS signal Splitter modules 3 of them
------------------------------------------------------------------------------
DATE: 10:12-AUG-2006 At: Fermi TOPICS: Work on L1 Cal Trig, Work on M122
Top crate Monitor data VME reads
Brought Meastro and non-Meastro versions of ADF-2 species A, B, D cards to
Fermi and put them in the spares cabinet. They are ADF-2 SN#: A20, A21,
B20, B21, D36, and D37. We already had cards C3 and C5 here at Fermi which
are Maestro and non-Maestro.
Brought a spare SCLD card to Fermi. Is is SCLD card #2. SCLD card #1 is
in the running system. I still need to configure the current firmware into
the SCLD #2 before it is a spare that is ready to use. I will leave the
old msul1a machine at Fermi until I can get this done.
Work on M122 Top Crate VME monitor data readout
- Moved SM-50 into Slot #11 and verified that during Configuration I could
see the VME LED in slot 11 flash when TCC was configuring slot 8. Yes,
I could easily see this LED flash. This was noted a couple of weeks
ago and has been seen years ago in other cards and crates.
- Keep everything the same but now put in the VI-TOM that delays the
AS* by 100 nsec. Now SM-50 in slot 11 does not flash during Configuration
except when TCC is talking to it. But now SM-05 in slot 21 flashes when
TCC is configuring slot 18. Did this happen before ? I don't think so
but I did not explicitly check for this today.
- Try SM-54 in slot 21 and it does the same thing, i.e. flash its VME_LED
when TCC is configuring slot 18.
- Time is up so I give up and put back in all of the original SM cards.
Slot 11 is SM-31 slot 14 is SM-4 slot 21 is SM-05
slot 1 has VI SN# 34295 with TOM SN# ?? with the 100 nsec delay on AS*.
- I put on a new RAY card.
- The documentation on the VI-TOM with the 100 nsec delay on both edges
of AS* is in the TFW FPGA 3 ring note book.
Notes:
- When watching the VME LEDs flash every 5 seconds for the monitor
data reads I clearly see the LEDs in M122 Top Crate flash twice.
The time distance between these flashes varies from so close that you
can just detect it with your eyes up to a good fraction of a second
apart. M122 Top Crate flashes once and then it flashes again when
all of the rest of the TFW crates flash for their monitor data readout.
M122 Middle (the other PBS crate) does not do this. I also could
detect this two scans through the M122 Top cards when I had the
scope connected to the M122 Top VME backplane.
First, a red herring, as the monitoring service reads the
Exposure Group Scalers (M122-mid crate) twice:
- The origin of that effect is that *two* monitoring block types
include the exposure group scalers, and even though TCC could manage
this information better and read it once but store it twice
... but this is not currently the case.
- This is not what is seen on the LEDs, as this effect is not present
for the foreign scalers, i.e. M122-top is read only once.
- This is also very unlikely to be visible in M122-mid, as there is
no significant time lapse between the two reading sweeps.
But TCC has two independent monitoring services.
- The standard monitoring service (cf. above) reads data every ~5 sec,
and uses the support circuitry for best try capture of a L1_Accept.
The information retrieval for this service is a pull system
where the client(s) have to ask TCC for data.
- The Luminosity monitoring service also reads data every ~5 sec,
but only uses the "capture now" feature for getting data.
The information retrieval for this service is a push system
where TCC will send that information to (one) Luminosity server.
- These two independent processes have to synchronize and share
the hardware allowing to capture, hold, and read monitoring data.
It is thus not surprising that these two *independent* processes
would tend to fall in lockstep, a fraction of a second apart.
- I thought that the pattern of module addresses that we had selected
guaranteed that the distance between any two slot base addresses
included at least one high order address line going 0 --> 1 and at
least one high order address line moving 1 --> 0. But it does not.
- AS* could be bouncing at the end of the cycle when it goes back to
its higher Voltage state again. This may be the cause of the flash
at adjacent slots during configuration.
- I don't see how the VME state engine can hang. Its just not possible
in the VME control unit as written.
- Is this an issue of 4013L executables not being made with M1.4 ?
- The control unit state engine for the VME Interface FPGA is at:
/home2/designs/fpgas/vme_uber/control_unit/source.vhdl_5
- Look at the 5 spare Scaler Module cards that are at Fermi to see
which type of FPGA they have for their VME Interface and to see
which mark is on their EEPROM for their VME Interface:
Scaler Module VME I/F EPROM
Serial Number FPGA Type Mark
------------- --------- ------
50 4013L UR
54 4013L UR
48 4013L LL
01 4013L LL
55 4013L LL
It is Scaler Modules SN# 50 and 54 that I brought from MSU
a couple of weeks ago. I do not know what mark is on the
EPROMs on the SM cards in M122 Top. I should have checked earlier.
A description of the different versions of the VME FPGA Interface
Serial Configuration EPROM is in the document on the web at:
www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/general/
characterization_of_run_ii_components.txt
- Use the scope to check the waveforms on the VME backplane in M122 Top.
Record 8 scope pictures on disk #5. They are:
File Yellow Blue Pink Green
Number Trace Trace Trace Trace
------ ------ ----- ------ -------
0 AS* DS0* DTACK* Adrs_05
1 AS* DS0* DTACK* Adrs_05
2 AS* DS0* DTACK* Data_00
3 AS* DS0* DTACK* AM_1
4 AS* DS0* DTACK* Adrs_14
5 AS* DS0* DTACK* Adrs_15
6 AS* DS0* DTACK* DS1*
7 AS* DS0* DTACK* AM_1
Most of these scope pictures are at 200 nsec per division but a couple
were at 1 usec per division to so two consecutive cycles (which are
about 6.6 usec apart. General view - everything looks nice and clean.
I looked at all adress lines that are used for card selection (plus
one on each side) A21:A14 and they are all clean.
These scope pictures have been moved to the web and are available at:
www.pa.msu.edu/hep/d0/ftp/l1/framework/pictures/
They have filenames of the form: vme_bus_m122_top_?.tif
The index digit in the filename matches the file number
in the table above.
I need to test the spare TFW Power Pan that is at Fermi and I need to put
the second spare TFW Power Pan back together which requires getting back its
3.3V brick.
I still need to replace the fan under the Status Concentrators. This should
get bumped up in priority before there is a problem.
------------------------------------------------------------------------------
DATE: 9-AUG-2006 Action at Fermi Note from MSU TOPICS: M122 Top Crate Hang
This looked like a "classical" hang of the M122 top crate VME read cycles.
Marco accidently pressed the "AC FAIL" push button instead of the "VME Reset"
push button so he had to Initialize the TFW again to get things running.
This was in store. He said it was SM-50 at slot 14.
------------------------------------------------------------------------------
DATE: 8-AUG-2006 Action at Fermi Note from MSU TOPICS: M122 Top Crate Hang
Tuesday morning it appreas that the monitor data VME readout of the M122
Top Crate got hung up again. It was hard to tell what the problem was
from the Rolling Rate Plots because the Luminosity in that plot just
held constant at its previous value. Brendan says that he just reset
M122 top crate to get things running again. He said it was SM-50.
------------------------------------------------------------------------------
DATE: 1-Aug-2006 At: MSU - action at Fermi TOPICS: Reload TRICS
Stop TRICS V10.5 Start TRICS V11.1 The V11.1 of TRICS has:
- does not write any scaler count
on the front panels of M122-TOP nor M122-MID
- has all the dialog buttons related to L1Cal
disabled, i.e. inaccessible.
------------------------------------------------------------------------------
DATE: 31-July-2006 At: MSU - action at Fermi TOPICS: M122 Top Crate
Paged about 1AM Eastern time because the Luminosity scalers were not
reading out OK. Brendan noted that it was SM-50 that had hung.
------------------------------------------------------------------------------
DATE: 26:29-JULY-2006 At: Fermi TOPICS: Work on L1 Cal Trig, Work on M122
Top crate Monitor data VME reads,
Thursday early AM work on the Foreign Per Bunch Scalers, work on ADF-2 cards
to compensate for broken BLS signals, make And-Or Term 177 external.
Foreign Per Bunch Scalers
From M122 Top Crate the Foreign Per Bunch Scalers
from Slot #11 pull SM-31 and install SM-50
from Slot #14 pull SM-4 and install SM-54
The setup for Slot #11 was ID $20 Adrs $1f
The setup for Slot #14 was ID $20 Adrs $28
The card in slot
When configuring the M122 Top Crate FPGAs while TCC was working in Slot #8
(or there abouts) it made the Slot #11 VME LED flash a bunch. All other VME
LED activity looked normal during the configuration process.
ADF-2 BLS signal compensation work
Crate A Slot 10 work on ADF-2 card SN# A9 Channel 4
pull off C222 move R225 & R226 to 220 Ohm
Crate A Slot 11 work on ADF-2 card SN# A10 Channel 4
pull off C221 moce R255 & R256 to 220 Ohm
Crate C Slot 14 work on ADF-2 card SN# D5 Channel 12
pull off C621 move R625 & R626 to parallel 1370 Ohm
Crate D Slot 2 work on ADF-2 card SN# D13 Channel 1
pull off C52 move R55 and R56 to parallel 1370 Ohm
Make And-Or Term 177 external
Add the two section flat cable to the L1 Cal Trig #3 And-Or Term
cable. This extension cable breaks out the 2nd diff pair which is
And-Or Term 177. But this through our Diff ECL to single ended
ECL box and route that to a 1U BNC Lemo patch panel that I installed
in the bottom of M107. Send an detailed note to folks explaining
the setup of the Cal Noise external trigger signal.
Thursday
Spend a lot of time looking a BLS signals. It does look like the channels
that show a difference between Find_DAC Pedestal and event readout data
pedestal. +10,9 HD is one with clearly a lot of synchronous noise on it.
Recall the layout of the now totally un-labled BLS signals.
Looking at the Patch Panel with the door folded down, i.e. sitting in front
of the rack and fold down the Patch Panel panel and look down on it.
These are the relative eta,phi
+--------------------------------------------------------------------+
| |
| 0,0 2,0 0,1 2,1 0,2 2,2 0,3 2,3 |
| |
| 1,0 3,0 1,1 3,1 1,2 3,2 1,3 3,3 |
| |
| |
| PFC Conn to Upper PFC Conn to Lower |
| Paddle Board Conn Paddle Board Conn |
| |
+--------------------------------------------------------------------+
Pin #1 of the BLS Cable Connectors in this diagram is in
the Lower Lefthand corner of each of the 16 connectors.
Now fold up the Patch Panel panel door, stand in front of the rack, and
look at the Monitoring connectors. They are arranged as shown below.
Note that the Ground row is the Top row of these connectors.
These are the relative eta,phi
ETA 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3
PHI 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3
EM E H E H E H E H E H E H E H E H E H E H E H E H E H E H E H E H
or M D M D M D M D M D M D M D M D M D M D M D M D M D M D M D M D
HD
Note it increases in eta and then in the next connector block it
has incremented in phi.
There are 4 panels of this BLS Transition stuff in each rack.
For example rack M103 has the following 256 BLS signals to monitor:
Top Panel +1,1 EM +1,1 HD +2,1 EM .... +3,8 HD +4,8 EM +4,8 HD
+1,9 EM +1,9 HD +2,9 EM .... +3,16 HD +4,16 EM +4,16 HD
+1,17 EM +1,17 HD +2,17 EM .... +3,24 HD +4,24 EM +4,24 HD
Bot Panel +1,25 EM +1,25 HD +2,25 EM .... +3,32 HD +4,32 EM +4,32 HD
Friday
TT Eta range label the BLS Transition system in the 10 racks.
It ends up that And-Or Term 177 is a single electron term and that term 193
(i.e. 16 higher) is the "Noise_2" term. I was told in email to use 177.
We ran for a day in a big Store and no one noticed the zero rate on the
triggers that required Term 177. In the Operations Meeting I'm blamed for
unplugging the wrong And-Or Term but graciously offered a chance to
explain why I screwed up.
Friday afternoon, Monitor data read VME hang in M122 Top crate slot #11.
This is after about only 36 hours of running. So the failure was in the
same slot but with a different card.
Meet Jim Strait at picnic and in the afternoon visit with Ray Yarema.
Saturday
After the end of the Store at 5:30AM I did the following work on
M122 Top Crate:
Pull out the TOM card and install a spare. Pulled out TOM SN# 16
which has only the ECO for the Crystal Oscillator on it.
Install TOM card SN# 07 which has both the Crystal Oscillator ECO
and the IRQ4* ECO on it.
Pull the RAY card off the back and look at it. I do not have a
spare here at Fermi so I need to bring one. It looks OK and there
is no choice so I put the same RAY card back on M122 Top.
Swap the VI Masters for M122 and M101. The intent here is that I
want a known good VI Master to put into M101 and M122 now only
needs the 3rd channel of its VI Mater to work OK so even if the
one that I'm pulling from M101 has a once a week flaky first
channel it will not make any difference. So
Pull VI Master SN# 189 from servicing M101. It was setup
as switches: all ON except switch #4 OFF.
Pull VI Master SN# 31 from servicing M122. It was setup
as switches: all ON except switch #4, 5, 6 OFF.
Install VI Master SN# 31 to service M101.
Install VI Master SN# 189 to service M122.
While I have the power off in the TFW Communications Crate I also
pull out from it the old L1 Cal Trig IRONICS card.
Pulled all 20 Scaler Modules and inch out of their sockets and
then plug them back in and check that all are fully seated.
Power up and Configure M122 Top. While doing this I notice that
as card SM-33 in Slot 8 is getting its load that I once in a while
see card SM-50 in slot 11 flash its VME LED. I also saw this Thursday
early AM when I first installed the two replacement SM cards and we
have seen this other places. To work at this I swap the two
replacement SM cards. Thursday AM I had put SM-50 in Slot 11
and SM-54 in Slot 14. Now I swap so that now SM-54 is in Slot 11
and SM-50 is in Slot 14. Try a couple of Configure M122 Top.
All LEDs look clean.
There is a fan not turning normally that cools the Status Concentrator
cards. I need to bring a spare fan next trip and figure out how to
replace this fan. Need to bring fan cord parts too.
The big dewer at the pit level holds 20,000 gal of Ar which is I think
225,000 lbs. It currently has about 3,500 gal in it.
------------------------------------------------------------------------------
DATE: 17-July-2006 At: MSU - action at Fermi TOPICS: M122 Top Crate
I was called at about 8:10 AM because the, "our luminosity number goes nuts".
Marco was on shift. He had tried to page me but I did not hear the page.
He recorded that it was M122 Top Crate card SM-31 that had its VME LED
stuck ON. He pushed the slot #1 TOM card VME Reset button and the VME Monitor
Data readout started back up again just fine. We lost about 20 minutes of
Luminosity Monitor Data. The previous failure of the Luminosity Monitor Data
readout was on 19-June-2006.
Recorded history to date of M122 VME Monitor Data Readout Failures.
This shows when the problem started and what Scaler Module was involved.
7:00 AM Monday July 17th failure at slot #11 which is card SM-31
8:48 AM Monday June 19th failure at slot #11 which is card SM-31
4:54 AM Thursday June 15th failure at slot #14 which is card SM-4
10:56 PM Wednesday June 7th failure at slot #14 which is card SM-4
6:44 PM Saturday May 17th Begin investigating this at Fermi
during the 23:27-May trip. It is a
failure at slot #11 which is card SM-31
sometime before 1:40PM Friday May 12th failure at slot ??
7:41 AM Wednesday May 3rd failure at slot ??
Action Plan:
Although it seems unlikely that after 5 or 6 years of error free operation
that two Scaler Modules would fail in exactly the same rare way, i.e. once
every two weeks or so, let's try replacing them and see what happens.
So, this week I will check out two replacement SM cards here at MSU and
package them up to take to Fermi next week. There is clearly the big
question of how to test them at MSU - but it is probably a good idea to
get some TFW stuff running in the new Physics building. The goal is to
have power on these two cards for at least 2 days, get all 18 FPGAs
on each card configured, and to make Random I/O run for two days. Then
package up these two cards and take them to Fermi on Tuesday July 25th.
------------------------------------------------------------------------------
DATE: 6:8-JULY-2006 At: Fermi TOPICS: Work on L1 Cal Trig, BST2005
running from Fermi, Bring Saclay ADF Crate to MSU
for repair by Wiener, Spare ADF-2 cards at Fermi,
need to replace a fan in the SCL Hub-End crate.
Worked on the reported problem of no SCL signals out on the sidewalk.
The SCL Hub-End was just fine. The three runs out to the sidewalk are
plugged in just as described in the Official Crate List file on the web.
SCL cabled clearly were pawed through at the SCL Hub-End while people
were "tracing" the sidewalk cables.
The cables to the sidewalk were just fine. The two SCL Receiver cards
in use out on the sidewalk are just fine. The assumption is that the
new/different VME/SCL card now in use on the sidewalk has a problem
(perhaps just wrong firmware loaded).
Tried to run BST2005 on Moto with the display at Fermi on D0sunmsu1 and
had the not unexpected trouble with fonts. Bring the Board Station 2005
fonts from Moto to D0sunmsu1 (aka Becane_too) and put them into
/home2/edmunds/Fonts_bst2005/ Then just add these fonts to the font
path via:
xset fp+ /home2/edmunds/Fonts_bst2005
and now BST2005 running on Moto can display on Becane_too at Fermi.
I brought the Saclay ADF Crate (Wiener VME-64X) back to MSU so that we
can figure out what needs to be done with it to make it into a "standard"
ADF-2 Crate and then get it sent off to Wiener to get the work done.
There is enough space in the "spare cards cabinet" to put in a 6U card
storage file if we want to to hold ADF-2 and VI cards ... Currently at
Fermi we have 2 spare ADF-2 cards, they are: SN# C3 which is setup as
a Maestro and SN# C5 which was also setup as a Maestro. This means
that we had two spare maestro ADF-2 cards at Fermi and no plane flavor.
So I "un-Maestro'd" the card SN# C5.
There is a fan not turning normally that cools the Status Concentrator
cards. I need to bring a spare fan next trip and figure out how to
replace this fan. Need to bring fan cord parts too.
------------------------------------------------------------------------------
DATE: 19-June-2006 At: MSU action at Fermi TOPICS: M122 Top Crate VME
Monitor Data readout failure.
The shift captain page me about 9:30 AM on Monday June 19th because the
"luminosity numbers started jumping around like mad". The VME LED was
stuck ON on the Per Bunch Scaler card in slot #11 which is SN# SM-31.
I left the Monitor Data Server running while the shift captain pushed
the VME Reset button. Doing just that cleared up the problem.
We did not stop and restart the Monitor Data Server.
We did not re-configure any FPGAs.
We did not re-load any control register information.
------------------------------------------------------------------------------
DATE: 12:15-JUNE-2006 At: Fermi TOPICS: Work on L1_Cal_2B, BLS Signal
Latency Compensation Values, Operating L1Cal_TCC
software remotely
Collect more ADF Raw ADC Data to verify the timing alignment with the
peak of the BLS signals. Start by working in CC. Recall that the
quick check this past Friday night (9-June-2006) showed that the ADF
was using the ADC data about one sample after the peak of the BLS
signal for calculating the Et to send to the TABs.
Recall how the TT Phi's are layed out:
Top
9 | 8
|
16 | 1
West -------+------- East
17 | 32
|
24 | 25
Bottom
To study CC I need to look at both positive and negative TT Eta and at
EM and HD. Picking TT Phi's near either West or East will keep this in
the middle of the range.
The log files from capturing ADF Raw ADC data are in:
/tcc/L1Cal_IIb_Work/LogFiles/L1Cal_IIb_TCC/
with file names like:
AdcCapture_V4_2_B_20060613.dat;1
For the Raw ADC Memory Block that starts at Register Address 2048 the
Monitor Data for the first Live BX, i.e. Tick #7, is stored at Reg
Adrs 2073. The "AdcCapture_V4_2_B_2006ijkl.dat;n" files have on their
first line, i.e. line #1 in xemacs, the data from Reg Adrs 2048. Thus
the Monitor Data from Reg Adrs 2073 is on line number 26 in these files.
The following table shows for each of the 36 Live Crossings: the Tick
Number (Hex and Dec), the Reg Adrs of the Raw ADC Memory Block where this
Monitor Data is stored, and the Line Number in the ADC Capture file where
this Monitor Data is located.
First Super Raw ADC
Bunch Raw ADC Monitor Data in
----------- Monitor Data ADC Capture File
BX dec hex at Reg Adrs at Line Number
---- --- --- ------------ ----------------
1st 7 07 2073 26
2nd 10 0a 2085 38
3rd 13 0d 2097 50
4th 16 10 2109 62
5th 19 13 2121 74
6th 22 16 2133 86
7th 25 19 2145 98
8th 28 1c 2157 110
9th 31 1f 2169 122
10th 34 22 2181 134
11th 37 25 2193 146
12th 40 28 2205 158
Second Super Raw ADC
Bunch Raw ADC Monitor Data in
----------- Monitor Data ADC Capture File
BX dec hex at Reg Adrs at Line Number
---- --- --- ------------ ----------------
13th 60 3c 2285 238
14th 63 3f 2297 250
15th 66 42 2309 262
16th 69 45 2321 274
17th 72 48 2333 286
18th 75 4b 2345 298
19th 78 4e 2357 310
20th 81 51 2369 322
21st 84 54 2381 334
22nd 87 57 2393 346
23th 90 5a 2405 358
24th 93 5d 2417 370
Third Super Raw ADC
Bunch Raw ADC Monitor Data in
----------- Monitor Data ADC Capture File
BX dec hex at Reg Adrs at Line Number
---- --- --- ------------ ----------------
25th 113 71 2497 450
26th 116 74 2509 462
27th 119 77 2521 474
28th 122 7a 2533 486
29th 125 7d 2545 498
30th 128 80 2557 510
31st 131 83 2569 522
32nd 134 86 2581 534
33th 137 89 2593 546
34th 140 8c 2605 558
35th 143 8f 2617 570
36th 146 92 2629 582
Recall the Tick Numbers of the Live BXs from our log book for 24:28-APR-2001.
SCL Frame L1 Accept Tick Number of the
36x36 Accelerator Live Crossings
---------------------------------------
First Second Third
Super Super Super
Bunch Bunch Bunch
--------- --------- ---------
BX dec hex dec hex dec hex
---- --- --- --- --- --- ---
1st 7 07 60 3c 113 71
2nd 10 0a 63 3f 116 74
3rd 13 0d 66 42 119 77
4th 16 10 69 45 122 7a
5th 19 13 72 48 125 7d
6th 22 16 75 4b 128 80
7th 25 19 78 4e 131 83
8th 28 1c 81 51 134 86
9th 31 1f 84 54 137 89
10th 34 22 87 57 140 8c
11th 37 25 90 5a 143 8f
12th 40 28 93 5d 146 92
First study the Central Calorimeter
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De-
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
A 4 +1:+4 9:12 EM ;1 152 580 582 2
EM ;14 193 580 582 2
HD ;3 113 100 98 98 0
HD ;4 197 554 556 558 2
A 10 -1:-4 1:4 EM ;5 160 484 486 2
EM ;7 188 284 286 2
HD ;9 201 321 320.5 322 1.5
HD ;13 176 34 36.5 38 1.5
B 5 +5:+8 29:32 EM ;15 192 543 543.5 546 2.5
EM ;16 176 496 498 2
HD ;21 117 298 297 298 1
HD ;26 145 474 473 474 1
out of time ---> HD ;31 668 608 607
B 10 -5:-8 17:20 EM ;33 155 119&120 119.5 122 2.5
EM ;34 262 332 331.5 334 2.5
EM ;35 164 568 570 2
HD ;36 137 250 249 250 1
HD ;43 127 331 331.5 334 2.5
HD ;44 158 508 508.5 510 1.5
In all cases the channel that was studied on the card was the relative
eta,phi 0,0 of that card.
The "Peak at" column shows the ADC sample with the highest value (pk)
and shows the ADC sample that was in the middle of the top of the
peak (Mid) if that sample is different than that of the peak.
"Delta" is the difference between the ADC sample at the middle of the
top of the peak and the ADC sample that was used to determine the output
Et value of the Filter.
Now back for some more CC data.
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De-
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
A 2 +3,2 EM ;50 155 48&49 48.5 50 1.5
EM ;51 284 235&236 235.5 238 2.5
EM ;52 174 308 310 2
HD ;53 194 507&509 508.5 510 1.5
HD ;54 136 322 321 322 1
HD ;55 132 359 357 358 1
A 4 +3,10 EM ;56 259 47&48 47.5 50 2.5
EM ;57 166 72 74 2
EM ;58 196 235&236 235.5 238 2.5
HD ;59 130 288 286 286 0
HD ;60 136 459 460 462 2
HD ;61 150 23 24.5 26 1.5
A 6 +3,18 EM ;62 186 120 122 2
EM ;63 211 332 334 2
EM ;64 154 472 474 2
HD ;65 139 546 545.5 546 0.5
HD ;66 134 62 61 62 1
HD ;67 213 38 38 38 0
A 8 +3,26 EM ;68 166 155 155.5 158 2.5
EM ;69 178 109 108 110 2
EM ;70 153 295 296 298 2
HD ;71 133 569 568.5 570 1.5
HD ;72 170 487 485 486 1
HD ;73 152 74&75 73.5 74 0.5
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De-
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
A 10 -3,2 EM ;74 179 119 119.5 122 2.5
EM ;75 157 131&132 131.5 134 2.5
EM ;76 258 367 370 3
HD ;77 179 247 248.5 250 1.5
HD ;78 139 237 236.5 238 1.5
HD ;79 140 71 72 74 2
A 12 -3,10 EM ;80 164 483 486 3
EM ;81 153 543&544 543.5 546 2.5
Out of time --> EM ;82 340 616 -
HD ;83 180 158 156.5 158 1.5
HD ;85 138 473 472 474 2
HD ;86 160 107 108.5 110 1.5
A 14 -3,18 EM ;87 215 247 250 3
EM ;88 182 507&508 507.5 510 2.5
EM ;89 182 319 322 3
HD ;90 129 570 568.5 570 1.5
HD ;91 270 486 484.5 486 1.5
HD ;92 143 298 297 298 1
A 16 -3,26 EM ;93 272 283&284 283.5 286 2.5
EM ;94 169 132 134 2
EM ;95 256 308 307.5 310 2.5
HD ;96 129 530 532 534 2
HD ;97 146 558&559 557 558 1
HD ;98 130 286 285 286 1
Now study the End Cap Calorimeters
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
B 18 +9:+12 17:20 EM ;45 295 569 570 1
EM ;46 219 97 98 1
EM ;47 166 357 358 1
HD ;49 126 472 474 2
HD ;50 143 556 558 2
HD ;51 127 122 121 122 1
C 2 -9:-12 1:4 EM ;52 153 556 558 2
EM ;53 193 356 355.5 358 2.5
EM ;54 329 460 462 2
HD ;55 147 143 146 3
HD ;56 135 234 235 238 3
HD ;57 128 307 310 3
C 6 -9:-12 17:20 EM ;58 222 24 24.5 26 1.5
EM ;59 214 84 84.5 86 1.5
EM ;60 190 285 284.5 286 1.5
HD ;61 128 271 272 274 2
HD ;62 124 282 283.5 286 2.5
HD ;63 130 320 322 2
B 14 +9:+12 1:4 EM ;64 294 484 486 2
EM ;65 156 36 38 2
EM ;66 156 72 72.5 74 1.5
HD ;68 202 143 146 3
HD ;69 132 447 450 3
HD ;70 130 306 306.5 310 3.5
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De-
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
C 10 +13,1 EM ;1 156 555&556 555.5 558 2.5
EM ;2 153 235&236 235.5 238 2.5
EM ;3 261 519&520 519.5 522 2.5
HD ;5 149 470 471 474 3
HD ;6 145 35 36 38 2
HD ;7 129 470 471 474 3
C 12 +13,9 EM ;8 166 531 531.5 534 2.5
EM ;9 203 483 486 3
EM ;10 162 283 286 3
HD ;11 148 306 306.5 310 3.5
HD ;12 147 469&470 470 474 4
HD ;13 161 34 34.5 38 3.5
C 14 +13,17 EM ;14 170 273 272.5 274 1.5
EM ;15 155 485 486 1
EM ;16 158 121 120.5 122 1.5
HD ;17 129 59 59.5 62 2.5
HD ;18 131 459 462 3
HD ;19 141 119 119.5 122 2.5
C 16 +13,25 EM ;20 153 568 570 2
EM ;21 159 472 472.5 474 1.5
EM ;22 153 460 462 2
HD ;23 158 579 579.5 582 2.5
HD ;24 226 567 570 3
HD ;25 128 331 334 3
Collect the following ADF Raw ADC data: Filter
Peak at Uses
Result Peak Line No ADC
Crate File ADC 1:636 Sample De-
Slot Eta Phi EM/HD Version Value Pk Mid Num. lta
------ ----------------- -------- ----- ---------- ------ ---
C 18 -13,1 EM ;26 161 447 450 3
EM ;27 153 579 582 3
EM ;28 156 579 579.5 582 2.5
HD ;29 142 106 106.5 110 3.5
HD ;30 136 94 95 98 3
HD ;31 155 142 142.5 146 3.5
C 20 -13,9 EM ;32 153 23 26 3
EM ;33 163 543 546 3
EM ;34 153 447&448 447.5 450 2.5
HD ;35 170 458 458.5 462 3.5
HD ;36 162 270 274 4
HD ;37 131 118 122 4
D 2 -13,17 EM ;38 248 108 110 2
EM ;39 220 544 546 2
EM ;40 177 484 486 2
out of time --> HD ;41 203 614
HD ;42 137 446 447 450 3
HD ;43 138 83 83 86 3
D 4 -13,25 EM ;44 153 35 35.5 38 2.5
EM ;45 163 47 47.5 50 2.5
EM ;46 186 283&284 283.5 286 2.5
HD ;47 142 130 134 4
HD ;48 132 305 306.5 310 3.5
HD ;49 136 94 94.5 98 3.5
Now separately for each major section of the Calorimeter human
histogram the deltas noted above.
CC EM 0 @0, 0 @0.5, 0 @1, 1 @1.5, 14 @2, 13 @2.5, 4 @3
CC HD 3 @0, 2 @0.5, 10 @1, 12 @1.5, 5 @2, 1 @2.5, 0 @3
South (+) EC EM 4 @1, 4 @1.5, 4 @2, 4 @2.5, 2 @3, 0 @3.5, 0 @4
South (+) EC HD 1 @1, 0 @1.5, 3 @2, 3 @2.5, 7 @3, 3 @3.5, 1 @4
North (-) EC EM 0 @1, 3 @1.5, 5 @2, 6 @2.5, 4 @3, 0 @3.5, 0 @4
North (-) EC HD 0 @1, 0 @1.5, 2 @2, 1 @2.5, 6 @3, 5 @3.5, 3 @4
Conclusion of Friday night's and two days this week of looking at the
ADF vs BLS signals timing:
For CC EM increase the delay by 2 ADC samples. pass over 0/32
For CC HD increase the delay by 1 ADC sample. pass over 5/36
For South (+) EC EM increase the delay by 1 ADC samples. pass over 0/18
For South (+) EC HD increase the delay by 2 ADC samples. pass over 1/18
For North (-) EC EM increase the delay by 1 ADC samples. pass over 0/18
For North (-) EC HD increase the delay by 2 ADC samples. pass over 0/17
The details of this change to the BLS Signal Latency Compensation Values
is in the "Operating Data" file on the web:
www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/
adf_2_l1_cal_trig_operating_data.txt
These new BLS Signal Latency Compensation Values were put into use with
the Store starting Thursday morning 15-June-2006.
Recall how to run things from another unix machine:
ssh -l d0l1 d0tcc3
If necessary setenv DISPLAY to point to your local machine's
x-windows server. Then start the L1 Cal Trig TCC gui by:
/tcc/L1Cal_IIb_Work/L1Cal_IIb_TCC/linux/build/run_gui &
You probably also want a "Remote Console". This runs right in
a terminal window so if you want start a second terminal window
to d0l1 on d0tcc3 and then:
/tcc/L1Cal_IIb_Work/L1Cal_IIb_TCC/linux/build/run_remote_console
You can start an ADF ADC Mon in the same way, i.e. it displays its
output right in the terminal window that it is started from. As with
the old system you can pick which "slice" now BX you want to looks
at the data for, or you can average all the Live BXs in a turn "V".
What is displayed are the Et values that are sent to the TAB.
/tcc/L1Cal_IIb_Work/L1Cal_IIb_TCC/linux/build/run_trigmon_adc
When finished with the Remote Console or the trigmon_adc just close
the terminal window and ITC will clean up everything on d0tcc3.
Recall that only one instance of Remote Console, i.e. the Remote
Console, runs at a time.
Thursday morning I noticed that the M122 Top Crate VME monitor data readout
was stuck. Slot #14 SM-4 had its VME LED stuck ON. Ton of red on the TCC
log window.
- Stop the Monitor Server.
Try to reconfigure the M122 Top Crate.
That did not work (but it probably murdered all the FPGAs in that crate.
- Push the M122 Top crate TOM card VME Reset button (the button ABOVE
the array of LEDs on the TOM card).
That caused Slot #14 SM-4 PBS card to clear its stuck ON VME LED.
Start the Monitor Server and get a ton of red (probably from
FPGAs that were murdered in step #1.
Stop the Monitor Server again.
- Now re-configure M122 Top FPGAs and now that goes OK.
Start the Monitor Server and that is OK.
There was no power cycle required to get things running.
Wait for the full TFW Init which is coming soon to get M122 Top crate
re-loaded with all of its control data.
------------------------------------------------------------------------------
DATE: 6:9-JUNE-2006 At: Fermi TOPICS: Work on L1_Cal_2B, Work on TFW
M122 Top VME monitor readout and TCC copy of event
data readout to DAQ.
Tuesday: Pull out the rest of the AMP LVDS cables from the Sidewalk test stand.
This was a non trivial effort - they were stuffed down between racks
and caught on on the bolts and shelf support hardware and on their
own cable ties. They were held in with large cable ties that easily
dug into the thin LVDS cables. Because of the criss-cross between
ADF and TAB it was almost like one big glob of cables. If we had
used these AMP cables in the real system I don't know how we were
supposed to get them out of the Sidewalk test stand with 100% safety.
All of this was made much harder because two ADF crates had been
jammed into one rack.
Make the L1_Acpt signal available for scope trigger in MCH-1.
Wednesday: Work mostly on BSTN2005 on Moto.
Thursday: M122 Top gets into VME monitor data readout trouble again.
This time it is the PBS card in slot #14 SM-4 that hung with its
VME LED always ON. I thought that I would try to reset the VME IF
FPGA by pushing the lower push button (the one under the LED) on
the TOM card. This is the "AC Failed" push button. When I did this
all the BSF LED in that crate went out but TCC was still showing
a ton of errors. It ends up that this lower TOM push button, the
"AC Failed" push button causes the VME IF FPGA to re-Configure.
It is the upper TOM push button, the one above the LEDs, the VME
Reset push button that should cause the state engine in the VME IF
FPGAs to reset (but we have some evidence that this does not work).
Anyway, even after the VME IF FPGA re-Configure, VME cycles were
still not working in M122 Top. The shift captain and Bill wanted to
use the quiet time for a cosmic run so I power cycles M122 Top and
Configured it and returned to running OK.
Because this is a different SM card that hung, and because this does
not look like a loss of timing signal issue, and because this does
not look like a power supply issue (we don't think that any FPGAs
spontaniously lost Configuration) the plan is to replace the
remaining common part, i.e. the VME Slv module on the slot #1 TOM.
Install the 9U card file in the Spares storage rack. Threw out
some more old L1 Cat Trig spare, straighted things up, and put in
the new spare TRM that I brought to Fermi this trip, TRM-17.
Get from Sabine their analysis of the calibration of the old L1
Cal Trig from beam runs taken near the end of Run 2A. We will
call this the 8-JUN-06 calibration data. What she called eta 1:20
is TT eta +1:+20. What she called eta 21:40 is TT eta -1:-20.
Friday: Get the TFW system in the early AM to work on the M122 Top crate
Foreign PBS VME monitor data readout and the issue that the
dump of the copy of our main TFW readout data to the DAQ system
does not look right.
From M122 Top pull out the TOM and remove its VI Slv. Pull off VI
Slv SN# 34295. This VI has been in there for the past 6 years or so.
The *theory* is that this VI Slv may be screwing up a VME cycle once
overy 2 weeks or so while the TFW_TCC is either reading the PBS
monitor data from M122 Top or while it is painting the scaler display
in the BSF LEDs on those 20 cards. Put VI Slv SN# 36136 onto the TOM
and put M122 Top back together and Configure its FPGAs.
Philippe's theory about why the TFW_TCC dump of TFW readout data does
not look right is that there are two VME adress lines shorted together
in the VRB-VRBC-SBC VIPA readout crate. Power down the crate and
probe with the Fluke. There is a clear A8-A9 short. Pull cards one
at a time until the short goes away. This indicates that the problem
is on the VRBC card. It was a short between pins 36 and 37 of the
VME Bus Adrs receiver chip U65 on the VRBC card (address lines A08
and A09). I removed this solder bridge and cleaned up some of the
other clear soldering problems on this card.
It's clear that we were given a completely different VRBC card
when we asked for the VRBC firmware update. I must have
misunderstood - I thought that they were going to put the current
VRBC firmware onto the "our" VRBC card which had been running
OK for the past N years.
I started a new log file on TFW_TCC and after events were flowing
again I put two hex event dumps along with their formated dumps
into the log file.
------------------------------------------------------------------------------
DATE: 23:27-MAY-2006 At: Fermi TOPICS: Work on L1_Cal_2B, SCLD, Et data
in Et Lookup Memory, BLS cables, L1_Acpt Timing Change
Test, Rearrange And-Or Term Cables, M122 Top Read
Problem, TRM SN# 8, Master Clock config file,
L1Cal_TCC "hang", Spares List at D-Zero
Tuesday:
Asked to edit the official crate list file to change just two names:
L1CT1 --> L1CTT1 L1CT2 --> L1CTT2
No other changes.
Work on the top crate in M122, the Foreign Per Bunch Scalers to see why
it is giving I/O problems. Its power supply voltages look fine, both on
DC and AC with Fluke.
- The VME LED on the Scaler Card in slot #11 is always ON.
- The AS* and DTACK* LEDs on the TOM are both flashing. I *think*
that all cards is this crate are completing both Read and Write
cycles OK - but we can not prove this and we did not explicitly
test for this. E.G. slot #11 may not be DTACK*ing (see below).
- The BSF LED, the LED that is used for a scaler display that is
updated every 1/10 sec is working on all Scaler Cards except the
one in slot #11 - where it is off.
- None of the read data from this crate looks good. The read data
from Scalers Cards in slots 2:10, 12:21 looks different from the
read data from the Scaler Card in slot #11.
- We kind of think that maybe Scaler Card in slot #11 is stuck in
the middle of a cycle (perhaps a read cycle) and is screwing up
the data lines on the VME Bus.
- From the log book we think that *this instance* of M122 top crate
failure starting with all cards in M122 top not responding to
VME cycles and then at some point morphed into what looks like
mostly a problem in slot #11.
- If the power supply had failed, and thus the FPGAs lost configuration,
then the BSF FPGA would not have its control register that is driving
the BSF LED and apprears to be working.
Switch to running with Summer 2003 calibration data in the ADF Et Lookup
memories.
Finish work on SCL_Helper FPGA for operation at spread of 40.
Wednesday:
Work on the top crate in M122, Foreign Per Bunch Scalers.
- Verified that all still looks as described above.
- Pulled the "timing cable" i.e. pulled the TOM Paddle Board from slot #1
of this crate. This caused the VME LED on slot #11 to go out. It caused
TFW-TCC to log a ton of errors from all slots in this crate. I assume
that the TOM AS* LED was still flashing and that the DTACK* LED was not
flashing but I did not get this written down.
- Tried to plug the TOM PB back in (the intent was to see what the crate
looked like after a known Clock outage. I miss-aligned the TOM PB, saw
a flash, and it had burned a set of contact fingers out on the 160 pin
TOM PB connector. It cooked what I would call the contacts for pin
D31. Looking into the TOM PB 160 pin connector it is the next to the
bottom row, next to the right hand side column.
- Replaced the TOM PB. I used the only spare at Fermi and need to bring
another TOM PB to Fermi. Power up M122 Top OK. Siclence TCC Monitoring
reads. Configure just M122 Top. Did not Initialize. Turn back on
TCC Monitoring. At some point in here I restarted the log file.
Repair 4 BLS cable connectors (center conductor open at the connector).
Try to repair a 5th but it looks all OK inside - just clean it up.
Finished the L2_Helper FPGA for a spread of 40.
Thursday: flat tyre at high rise.
Tested the M122 Top Foreign Per Bunch Scalers
M122 Top was reading out 5 second monitor data just fine. I pulled the
TOM_PB timing and control cable. The TOM LEDs were still showing AS*
but no DTACK*. This clearly should have caused Bus Timeout Errors on
the Bit-3 which I assume when TCC discovers them will appear in the TRICS
log file. Understanding were these Bus Timeouts appear in the log file
may help us decode what actually happens when the readout from M122 Top
gets into trouble.
I then plugged the TOM_PB back in and the M122 Top readout just started
back up with no problem. Perhaps you only get into trouble if the 53 MHz
stops in the middle of a VME cycle ? Different versions of THE_Card
have different versions of VME_I/O FPGA silicon. All the same firmware
"source code" but targeted at different versions of FPGAs. Perhaps it
is only one of these versions of silicon that gets into trouble when the
53 MHz goes away.
Tested the L1_Acpt Latency shift to 3 ticks later
The version revision of the FPGAs to implement the Spread of 40 change in
the L1_Acpt latency are listed in the log book entry for 18-MAY-2006.
Before touching anything look at the current operation:
Use the TrgMon And-Or Term Display to see
And-Or Terms 208:239 have 20 or 21 ticks of alignment delay
And-Or Terms 80:95 have 0 or 1 ticks of alignment delay
And-Or Terms 32:63 have 0 or 1 ticks of alignment delay
Use the Logic Analyzer to see
The L1_Turn Number increments when the Current BX Number is $26.
Setup TFW_Only run and then add to it the BOT And-Or Term
And-Or Terms 242 -247 255 set prescale 10,000
This runs at about 5 Hz. Look at the Logic Analyzer.
LA says, L1_Acpt only at Current BX $26 L1 Bx $01.
Pause the run and silince the Monitor Reads. Move the SCL_Helper to
version for Spread 40 operation. Resume and look at the Logic Analyzer.
Now LA says, L1_Acpt only at Current BX $29 L1 Bx $04.
The TrigMon display of the And-Or Terms shows the same number of
"ticks of alignment delay" as listed above.
Now move the TTS to the version for Spread 40 operation. TFW Init
to get everything going and setup the TFW_Only trigger to fire on
the BOT And-Or Term as described above. The Logic Analyzer now sees:
The L1_Turn Number increments when the Current BX Number is $29.
The L1_Acpt is only at: Current BX Number $29 L1 BX Number $01.
Now move the L1_TRM's in M123 Top slots 2,3,9,10 to the version for
operation at Spread 40. Then Initialize the TFW. This Init blows up
on the TRM in slot 3 after doing TRMs in slots 10 and 9. The problem
that it has with the TRM in slot #3 is:
Post Write Mismatch Read feff Wrote ffff
Mast 0 Slv 3 Chip 3 Reg 2.
Now many tests on this problem:
Just configuring the old spread 37 version of the firmware into these
TRM slots does not cure the problem. I need to power cycle the crate
and then configure the old spread 37 firmware into these 4 TRM cards
to make the Post Write Mismatch error go way.
Put new TRM firmware into just TRM slots 9,10 (M123 Top) TFW Init
and all is OK. This let me see (using TrgMon) that:
And-Or Terms 32:63 have 3 or 4 ticks of alignment delay
And-Or Terms 80:95 have 3 or 4 ticks of alignment delay
i.e. a good sign that the spread 40 L1 TRM version is doing something OK.
Put the Spread 40 FPGA code into TRM M123 Top slot 3. FPGA site #3
continues to the the Reg 2 Read feff Wrote ffff I/O problem.
I checked all the other FPGA sites on this card and they were all OK.
Give up on the TRM card in M123 Top slot #3. Pull out from that slot
TRM SN# 8 and put in TRM SN# 21. This is a big deal. What is the
history of TRM SN# 21. It does not have any note tag string tied to it.
It does have a front panel label of Glb_Disab_TRM. Was it once the Global
Disable TRM in the TFW or in the MSU Test Stand ? I grepped the log books
and did not find much. It would be nice to be able to run the Single
Chance test with it in. It would be nice to see its readout data with the
TRICS TFW HSRO formatted data dump.
Changing this TRM card was very very hard because of the short cables to
the Pass-Through card in slot #4. I had forgotten about this. It is a
big deal to change the card next to the Pass-Through. This was the only
spare TRM card at Fermi. I need to bring another and to look at the
TFW spares stored here.
Anyway, with the TRM installed in M123 Top slot #3, and the Spread 40
TRM code now the system does a TFW Init OK. Put in the Spread 40 L2_Helper
Init and load the TFW_Only trigger and setup to fire using the BOT And-Or
Term. All looks OK.
Full Configure back to the normal FPGA versions. Load the TFW_Only trigger
and setup to fire using the BOT And-Or Term. The Logic Analyzer says that
everything is back to normal. The TrgMon display of And-Or Terms says the
alignment delays are back to normal.
Moved the And-Or Term inputs to the TFW to Marco's new rational arrangement.
Marco had a new rational order for the And-Or Term cables going into the
TFW. I moved cables (put on rational labels and removed many meters of
extenders and tap in adapters). Marco edited the COOR Resource file.
I edited the Current And-Or Term List on the TFW web site.
Loaded the new 9-MAY-2006 firmware onto the SCLD.
This is the current version of SCLD firmware. I adds 2 RF buckets of
delay to the Clock and Control signals to the ADF Crates. This is to
compensate for the shorter SCL cables in the MCH-1 (wrt the SCL cables
that were used on the Sidewalk). All this is just to hold the ADF Crates
at the same time absolute time wrt the BX as they had on the Sidewalk.
I.E keep the BLS signals in the same place. This just holds the ADF Crate
at its offical timing with no slack.
This new SCLD firmware also implements the new set of Meastro to SCLD
control signals to allow the capturing of ADF Monitor Data on "triggered"
BXs. This new SCLD firmware implements:
Force Save_Monit right now crate 0 signal 1
Enable assertion of Save_Monit crate 0 signal 0
at next L1_Acpt with L1_Qual #7
With this new firmware the control lines to the logic that generates
the Save_Monitor_Data signal appear to be working. One can see the
Save_Monitor_Data LED flash with its 8.6 msec stretch. It is not
bright but it is very clear that it flashes.
From working with the old version of the SCLD firmware from last fall
(27-Oct-2005) I believe there is a problem getting the Crate #1 Signal #0
into the SCLD FPGA, at least on the SCLD card which is hear at Fermi in
the Comm/Ctrl crate right now. It is SCLD SN# . Or else there is a UCF
file error.
Master Clock work for L1_Acpt Latency Change
First move the #2 Sequencer file out of the directory that the DAQ Shifter
can see and put it in the obsolete_files directory. We now have only one
Sequencer. That is:
move clk_sequencer_2_12NOV03.txt from /online/config/trg/master_clock
and put it in /online/config/trg/master_clock/obsolete files
Now make a new version of the #1 Sequencer file that moves the 3 Time Lines
that become And-Or Terms. They must move 3 ticks, i.e. 21 RF Buckets
later. These 3 Time Lines are:
Time Line 20 Ticks 43,57,96,110 Live Cosmic BX And-Or Term 241
Time Line 21 First Interaction in any Super Bunch And-Or Term 249
Time Line 22 Last Interaction in any Super Bunch And-Or Term 250
The delay setting for each of these time lines is changed from 223 to 244.
TCC formatted display of HSRO data from the TFW.
Philippe dug into this problem. Current theory is that the window mapping
VME Adrs space onto the SBC memroy that holds this data is too short in
the TFW SBC. From the look of the data Philippe thinks that the window is
only 0x40 longwords long. In the Cal Trig readout crate SBC this appears
to be 0x400 longwords long.
L1Cal_TCC quit working. The L1_Cal gui hung. Philippe could not get into
this machine from MSU. It appeared to "accept" the network connection but
then do nothing to allow the ssh application level stuff to run. I power
cycle booted it. It said that it could not find /home. I visited Jim. OK
they just moved the /home mount point. Something like the mount points are
no longer in the / director but a directory up from that with links back to /.
This issue is if the mount points are in the / directory and if some machine
can see one and if some one does an ls or such on that disk from that machine
then it hangs things. If the mount point is a directory up from / then you
do not have this hang (becaus there is no longer the connection with root)
or something like that. Anyway he quickly fixed it, then I could > startx
and then start Philippes gui and engine applications.
Friday:
Dug out a replacement spare BLS cable for -13,25 which has its EM+ coax
broken about 60ft from the MCH-1 end. Checked with the Tektronix 1502B TDR.
We used a spare cable to replace just the half of the ribbon cable that
carries the signals for TT -13,25 and -14,25. This means that now both
-13,25 and -14,25 will be carried on a spare cable.
At the BLS end these signals come from the top crate in rack PN05.
At the trigger end these signals go to rack M110.
The half ribbon that was disconnected today:
TT -13,25 was carried on a gray ribbon cable. It was carried on
the 4 coaxes at the blue stripe edge of the ribbon. At the MCH-1
end it has the label: PN05-0B-10/M110-2A-09 P25 E-13
TT -14,25 was carried on the same gray ribbon cable. Its 4 coaxes
are the next 4 in from the blue stripe edge (i.e. adjacent to
coaxes for -13,25). At the MCH-1 end it has the label:
PN05-0B-09/M110-2B-09 P25 E-14
At the BLS end these 8 coaxes that go into a single connector.
These 8 coaxes have two labels - one with each of the cable ID
numbers listed above.
The spare half ribbon that was connected today:
TT -13,25 will now be carried on the 4 coaxes in the spare ribbon
cable that has the label PN05-0B-S1/M112-SP-S1 at its MCH-1 end.
These 4 coaxes are on the blue striped edge of a gray ribbon cable.
TT -14,25 will now be carried on 4 coaxes in this spare ribbon
that have the label PN05-0B-S2/M112-SP-S2 at its MCH-1 end.
These 4 coaxes are adjacent in the ribbon to those that carry -13,25.
At the BLS end these 8 coaxes that go into a single connector.
These 8 coaxes have two labels - one with each of the cable ID
numbers listed above.
Spares at D-Zero
2x FM Gold 2x SM Blue 1x TOM
2x FOM Green 1x GS Blue
11x AONM A Orange 2x TDM Yellow
1x AONM B Brown 1x TRM Red (SN#8)
Need to bring at least one TOM_PB and one good TRM.
------------------------------------------------------------------------------
DATE: 18-MAY-2006 At: MSU TOPICS: Preparing for the L1_Acpt timing
change to 3 ticks later.
Preparatory Notes about the MAY-2006 Timing Move, i.e. moving
the timing of the L1_Accepts 3 ticks later.
The intent is to change the spread in the TFW from 37 to 40.
This change in the latency of the L1_Acpts from the TFW is accomplished
by modifying the firmware that is used in 4 of the TFW FPGA designs.
These FPGA designs are: SCL_Helper (1 instance), L2_Helper (1 instance),
TTS (16 instances), and the L1_TRM (176 instances).
The new EXO files that will be used for this May-2006 change in the
L1_Acpt timing are the following:
Spread = 37 Spread = 40
FPGA Version Version Installed Locations
-------------- ----------- ----------- ----------------------------
SCL_Helper _8_1 _9_1 M122B Slot 21 Site 13
L2_Helper _18_1 _19_1 M122B Slot 20 Site 4
TTS _17_3 _19_1 M123B Slot 21 Site 1:16
L1_TRM _7_1 _9_2 M123T Slots: 2,3,9,10,16,17
M123B Slots: 2,3,5,6
Sites 1:16
For this May-2006 change in the L1_Acpt timing we will also need
to edit Boot_Auxi.mcf to move:
Send_Msg_To_Self: "TrgMgr_Time_Zone_Spread 40"
For this May-2006 change in the L1_Acpt timing we will also need
to change the Master Clock configuration file to delay the 3 time
lines that become And-Or Terms by 3 ticks, i.e. 21 RF buckets.
These Master Clock And-Or Term time lines are:
241 Live Cosmic BX Ticks 43,57,96,110 CMC TL 20
249 Select FIRST BX in any Super Bunch CMC TL 21
250 Select LAST BX in any Super Bunch CMC TL 22
They currently have an offset value of 223 which will need to
change to 244.
The following are clips from old log book entries from other time
when we were asked to change the L1_Acpt timing. The most interesting
data is: what was done, and how it was tested.
.........................................................................
Clip from the log book 25:27-SEPT-2002
Wednesday 25-Sept early AM moved the timing of the L1_Acpt later by 2 ticks.
Put clk_sequencer_1_11APR02.txt into obsolete_files
Move clk_sequencer_1_18SEPT02.txt from test_files into /master_clock
and load it into Sequencer #1. This moves the First BX in Super Bunch and
the Last BX in Super Bunch and the Liver Crossings in the Cosmic Gap
And-Or Terms to their new locations. Verify that these have moved and
are correct by using one of them for a trigger and seeing where the
L1 Accept is issued.
The new EXO files that will be used are the following:
Spread = 35 Spread = 37
FPGA Version Version Installed Locations
-------------- ----------- ----------- ----------------------------
TTS _16_1 _17_3 M123B Slot 21 Site 1:16
L1_TRM _6_1 _7_1 M123T Slots: 2,3,9,10,16,17
M123B Slots: 2,3,5,6
Sites 1:16
SCL_Helper _7_1 _8_1 M122B Slot 21 Site 13
L2_Helper _17_1 _18_1 M122B Slot 20 Site 4
CT_Read_Helper _10_1 _14_1 M101M Slot 21 Site 4
Tied the CMC front panel D-Zero BOT marker up to the logic analyzer.
It is at Cur BX 9a L1 BX 77 i.e. a spread of 35. Measure this again
after all the changes and it is not at Cur BX 9a L1 BX 75 i.e. a spread
of 37.
Look at the TRM FIFO Depth:
L1 Cal Trig now 7,8 after all changes 9,19
Dean now 19 after all changes 21
L0 Rich now 18,19 after all changes 20,21
Muon now 0,1 after all changes various 1 through 4
Trigger on BOT. With all current FPGA's it fires on L1_BX 01. Swap
just SCL Helper and it fires on L1 BX 03
Swap TTS and now it fires on 01. The spread is 37. Test the Tick Selects
and they are OK.
Verify that triggering from: BOT, Tick_sel #3, First in SB, Last in SB,
Live BX in Cosmic Gap, Live Accelerator BX are all OK. Observed 29 of the
36 with no errors.
Watch about 75 L2_Decisions to verify that the new L2_Helper is correct.
Edit : CT_Readout_Helper.dci
fomppl_miguel.dci
l1_tdm.dci
L2_Helper.dci
SCL_Helper.dci
TTS.dci
And now a full Configuration of the 1,634 FPGA's in the TFW to prove that
it will deadstart OK.
Edit the Boot_Auxi.mcf to add
Send_Msg_To_Self: "TrgMgr_Time_Zone_Spread 37"
Michael check the Exposure Group Per Bunch scalers and they now look OK.
Verified that the Foreign PBS still look OK.
.........................................................................
Prepare the Master Clock for the 25-Sept-2002 timing change.
! 18-SEPT-02 D.E. We are changing the timing to issue the L1_Acpt 2 ticks
! later. Normally this would not require touching the Master Clock except
! that we now have 3 And-Or Terms that come directly from the CMC Time Lines.
! These are:
!
! TL20 Tick 43,57,96,110 first last Cosmic Gap AO Net Input
! TL21 First Interaction in Super Bunch AO Net Input
! TL22 Last Interaction in Super Bunch AO Net Input
!
! The offset value used for all three of these is currently +211. Normally
! one would just add 14 to this to move these signals 2 ticks later. But
.........................................................................
From a note with Dmitri on 30-SEPT-2002 about the move of the
L1_Acpt timing on 25-Sept-2002 to is current position.
"Since the timing was moved last week, the TFW issues the L1 Decision
about 3.63 usec after the beam crossing. That is when the L1 Decision
leaves the TFW. This is 27.5 "ticks".
The L1 Decision then passes through:
the SCL Hub-End,
the SCL cable to detector system,
the SCL Receiver
and is then finally available to the detector system electronics.
These steps take about 480 nsec (for cable runs to MCH-3).
So the L1 Decision reaches the detector system electronics on MCH-3
about 4.11 usec after the beam crossing. This is about 31 "ticks".
MCH-1 and MCH-2 are about 26 nsec less. Platform (the CFT and SMT
Sequencer Controllers) is about 125 nsec more."
.........................................................................
Clip from the log book 12:16-JUNE-2001
Install the timing change to move the L1 Decision 2 Ticks later
Verify timing before making the change: the spread is $21, The first
live accelerator crossing happens at the beginning of current tick $0d,
the CMC BOT output happens during current tick $9A.
Verify that swapping just the SCL_Helper does the right thing. Yes, firing
on the BOT AOIT, i.e. AOIT 244, causes the L1_Acpt to issue during current
tick $24, L1 tick $03.
Move to the new FPGA's for spread of 35. That is edit and copy to MSU:
tts.dci moves to 14.1 L1_trm.dci moves to 6.1 scl_helper.dir moves to 7.1
No change of any kind to the Master Clock.
Verify that the spread is 35.
Run with a BOT AOIT trigger and see that the L1_Acpt is issued during
current tick $24, L1 tick $01.
Check the logic analyzer against the time of the real BX. As usual this is
at the output of the SCL Receiver with 44 ft of SCL cable.
SCL BOT is at: current tick $01, L1 tick $7D
CMC BOT is at: current tick $9A, L1 tick $77
first real BX is at the beginning of: current tick $0D, L1 tick $89
Check the AOIT TRM Input FIFO Depth:
And-Or FIFO
Input Term Depth
---------- -----
31 22
80 4
128 10
223 19 these look OK
.........................................................................
Clip from the log book 5:9-JUNE-2001
First simple test of the Spread 35 FPGA's. First try the L1_TRM and see
how much things change in the AOT FIFO Depth Analyzer.
Depth in TRM Input FIFO
------------------------
Current 5_1 NEW 6_1
AOT L1_TRM L1_TRM
--- ----------- --------
31 20 22
128 8 10
223 17 19
So it looks like the new spread 35 L1_TRM FPGA does this part OK.
Try the Tick and Turn Scaler. Chacking just the Current vs L1 BX numbers
on the SCL Receiver, it has moved it from a spread of 33 to a spread of 35.
Have not checked that the Tick Selects are still working.
To check the SCL Helper do the following.
Change just it, run a trig based on one of the markers, e.g. BOT
and see where it fires.
------------------------------------------------------------------------------
DATE: 12-MAY-2006 At: MSU TOPICS: List of broken BLS Crate
BLS Cable Connector pins
The following is the current list of broken BLS Crate backplane pins.
- From the log book entry for 10:13-DEC 2002.
We have broken pins at:
-2,1 HD M104 Broken BLS Backplane
center conductor pin.
BLS HD- signal is OK.
Broken pin on HD+ signal.
-2,5 HD M104 Broken BLS Backplane
center conductor pin.
BLS HD+ signal is OK.
Broken pin on HD- signal.
- From email from Dean on 17-May-2006 we have another broken pin at:
+16,17 HD M109 Broken BLS Backplane
center conductor pin.
BLS HD+ signal is OK.
Broken pin on HD- signal.
- There are some other (perhaps order of 3) broken GND pins
on the BLS Crate connectors to the BLS Cables. We have "fixed"
these by opening the BLS Cable connector and bussing together
all 4 of the shield grounds so that they can all connect to the
BLS Crate using the remaining 3 good GND pins. In a quick look
I had trouble finding a reference to this in log book.
------------------------------------------------------------------------------
DATE: 12-MAY-2006 At: MSU TOPICS: VME lockup in L1FW,
Disk full and TCC survives.
The L1FW was failing commands from COOR and replying that the L1FW
was not initialized. Scrolling up the screen shows that the last
initialization had failed when trying to program the first Foreign
Per bunch Scaler. The VME cycles fail as if there had been an
interruption of the 53 MHz clock. We successfully power off and reload
FPGAs for M122-Top (and also M122-Bottom by mistake) and initialize.
Marco had called on Monday or Tuesday with a similar issue, but we had
powered off and reloaded the whole system. Philippe tries to investigate
that earlier problem by looking in the logfile. There are no logfile
entries for that earlier probelm. The logfile had filled the disk
a week earlier on 3-May also with failures to write to M122-Top
starting at 7:41am and filling the disk by 9am.
These Per Bunch scalers are being accessed often to update the scaler
count accross the front pannels. They are in Master#0/Slave#0 and the
failure corresponds to TCC trying to write to the Board Support FPGA
Reg #1, to update the LED state. It makes sense that these would be the
most likely place to notice a momentary interruption of 53 MHz.
We already had mixed feelings about the extra VME IOs to display
the scalers accross the front pannels of the per bunch scalers.
We should decide if we want to continue or drop this feature for Run IIb.
This was a live test of Trics' ability to survive a disk full failure.
Deleting that 500MB file and telling Trics to start a new logfile
was successful in returning to normal logfile activity on the fly.
------------------------------------------------------------------------------
DATE: 2:5-MAY-2006 At: Fermi TOPICS: Work on Run IIB L1 Cal Trig,
Tuesday: Install 1/2 of the LVDS cables. Now 3/4 of the LVDS cables are
installed. Mikes says that all looks OK except for 3 flaky channels
all in ADF Crate "B" the crate with zero Pre_Emphasis. All of the
rest of the LVDS cables are now prep'd.
Install on cards B5:B16 from Crate "B" 4.9k Ohm Pre-Emphasis
resistors. This is the first 12 cards in ADF Crate "B". The
intent is for all cards in Crate "B" to have 4.9k Ohm Pre-Emphasis.
Visit Carl and Stephen at PAB. The new idea is to put only the
preamps in a circular structure 5" diameter and about 12 inches
long.
Meet with John Musson from MSU order of 1988-1990 who is now
doing RF and beam instrumentation at Jefferson Lab.
Wednesday: Install 4.9k Ohm Pre-Emphasis on ADF cards C6:C13 i.e. the final
8 cards in ADF Crate "B". Now all 20 ADF cards in crate "B" have
4.9k Ohm Pre-Emphasis resistors.
Installed the final 1/4 of the GORE LVDS cables. Packaged up and
labeled the spare LVDS cables.
Status: for a given configuration of TABs we typically have 2 or 3
channels that show errors. These are not hard error but rather are
typically parity errors at a few 10 of Hz or 100 Hz. If you move
TABs the errors move around. I'm sure if you move ADFs or cables
the errors would move too. Doing a "deskew" operation does not
fix these errors. These errors are typically in crates "C" and "D".
We decide to leave the TABs put in a standard configuration and try
to make everything work. To this end we crank up the Pre-Emphasis
even more on the couple of channels that were showing errors.
Crate "C" Slot #2 ADF SN# C14 Pre-Emph set to 1k Ohms
Crate "C" Slot #10 ADF SN# D1 Pre-Emph set to 1k Ohms
Crate "C" Slot #18 ADF SN# D9 Pre-Emph set to 1k Ohms
These were the 3 errors seen in the TABs. Moving to 1k Ohm fixed
slot #2 and slot #10 but slot #18 still showed some errors.
Change the cable for slot #18 bottom connector from a 5m cable
to a 365cm cable. Now zero errors.
After some minutes of running we see one more error this time
from crate "D" so also move it to 1k Ohm Pre-Emphasis.
Crate "D" Slot #19 ADF SN# D30 Pre-Emph set to 1k Ohms
We will now run an overnight test. We also realize that we
20 spare 425cm cables and 20 spare 365cm cables we did not need
to make crate "C" all 5m cables. Recall that crate "C" should
have been 305cm but GORE shipped us 5m cables.
Big push now needs to be working on strain relief and LVDS cable
clean up in the ADF Crates.
Thursday: The overnight run Wednesday night indicates that a a low level we
still have the same problems from Crate "C" Slots 2,10,18 and
Crate "D" Slot 19. We think that the solution is to run with
shorter cables to these crates. Mike installs 365 (or maybe even
shorter cables in the problem channels and I move the ADF cards
back to 3k Ohm
Crate "C" Slot #2 ADF SN# C14 Pre-Emph set back to 3k Ohm
Crate "C" Slot #10 ADF SN# D1 Pre-Emph set back to 3k Ohm
Crate "C" Slot #18 ADF SN# D9 Pre-Emph set back to 3k Ohm
Crate "D" Slot #19 ADF SN# D30 Pre-Emph set back to 3k Ohm
Now all cards in Crates "C" and "D" are at (back to) 3k Ohm Pre_Emph.
Work on dressing the ADF end of the LVDS cables. Rework the clamps
so there are 3 holders for the LVDS cables with 4,3,3,3,3,4
arrangement. Put a shelf 6 to 8 inches above each ADF Crate to hold
the spare slack LVDS cable. The shelf is made from the G10 tops from
the old Cal Trig crates. There is also a shelf between "C" and "D"
to hold the about 2m of slack cable in the runs to Crate "C".
With the 4 shorter cables to the appropriate output of the ADF cards
shown above we ran over lunch (about one hour) with zero LVDS
errors.
Worked with Ted and we have the LVDS cables in Crates "A", "B", and
"C" all dressed in. Ted had a number of good ideas about doing this
and it is very nicely setup. If Mike needs to move things around by
a couple of inches at his end - it is still easy to do that even
though things are all dressed at the ADF crate end. Selcuk made
nice tables of the cable labels as viewed from the ADF end so now
it is easy to understand the cables from either end.
Friday: At least the first 40 minutes of the overnight ADF to TAB LVDS test
look error free. I do not know the rest of the results yet.
Philippe is going to run the Find_DAC to get another look at the
ADF Pedestals right before the Pleated Foil BLS Signal cables are
plugged in. John Foglesong and Selcuk are going to plug in Pleated
Foil cables starting on Monday. The lists from Selcuk about the view
of the LVDS cables as seen from the ADF end look have been checked and
are correct for crates A, B, and C. I have not checked D yet.
------------------------------------------------------------------------------
DATE: 24:27-APR-2006 At: Fermi TOPICS: Work on Run IIB L1 Cal Trig,
Brought to Fermi the 4th cable for the console switch box on top of M101.
Monday: Channel Link signals on the scope do not look very good.
I learn that, working with the longest cables on all 30
channels, some TABs are 100% happy and some are not. The new
GORE cables appear to have 100% fixed the skew problem.
Working at Columbia Jaro measured skew as bad as 1.3 nsec on
the AMP cables.
Tuesday: They now have a 3 GHz scope and a 1.7 GHz differential probe to
look at the LVDS Channel Link. Have modified the Pre-emphasis
on a number of ADF cards so that we can look at waveforms with
various amounts of pre-emphasis.
SN# D16 pull 9k install: top 22k mid 22k bot 51k
SN# D19 pull 9k install: 3x 3k Ohm
SN# D20 pull 9k install: 3x 1k Ohm
SN# D21 pull 9k install: 3x 4.3k Ohm
SN# D23:D32 pull 9k install: 3x 3k Ohm on all 10 cards.
We received the last shipment of GORE cables today. Checking their
lengths we find:
PO Line # Ordered Quantity Received ADF Label
GORE Lot # Cable Length Ordered Cable Length Crate Color
---------- ------------ -------- ------------ ----- -----
1 245 cm 80 245 cm B blue
--> 2 305 cm 80 2 m C green
3 365 cm 80 365 cm A red
4 425 cm 80 425 cm D blank
The cables that we received for item #2 are 5m long instead of 305cm.
I sent a note to managers and Johnny. He has contacted GORE.
The boxes from Denis at Saclay with the remaining items from their
L1 Cal Trig work have arrived and are on the sidewalk.
Inside Box #1: The Wiener ADF Crate. It's clear that this
crate has been worked on (there are some loose
backplane wires). I don't know (but can not
imagine) that this crate was setup for +-5V
on the VME +-12V buses. So this crate will take
come cleanup and rework to make it a standard
D-Zero L1 Cal Trig ADF Crate. For now I will
just label this box and leave it on the Sidewalk.
Inside Box #2: A set of Vertical Interconnect cards and cables.
I will store these in the spare VI parts in the
MSU brown cabinet that had been L1 Cal Trig spare
power supplies.
A Bit-3 VME <-> PCI pair of cards. They are copper
Bit 3 and have the cable. I have no idea what
version this is or if it can be a spare. Take back
to MSU for Philippe to test.
The 3rd and final SCLD card. Take this back to
MSU to get it ready to run with ADF-2 cards.
A spare un-installed full length BLS cable.
It is a gray one. Label and store it in the old
MSU spare L1 Cal Trig power supply cabinet.
Wednesday: Johnny has heard back from GORE about Item/Lot #2 the 305 cm cables.
They are looking into it. I sent him a note about our schedule for
needing cables for installation at D-Zero.
Working with Mike we prep'd 30 of the 245cm cables. That took 1/2
hour (including an interruption). Installation of the prep'd cables
is fast. Where possible, clip together the 3 cable assemblies that
go to a given TAB connector, and feed that end of the cable into the
rack first. Actual installation can use 3 people, one making up the
assembly of 3 cables, and two feeding in cables. The 3x3 trays
will be just about full. By the end of the day 5/8 of the cables
are prep'd and Mike has the installation lists printed.
URL for the cold H Cal End Cap stuff:
www.nevis.columbia.edu/~ban/cold/
There are now tons of pictures looking at the Channel Link LVDS
signals with the 3 GHz scope and 1.7 GHz probes. I think the
result in words is:
425 cm select 3k Ohm "4.3K is not as good as 1k or 3k."
"1k and 3k look very much alike."
365 cm select 3k 245 cm select 4.3k
Thursday: Johnny has the proposal back from GORE. They want us to return to
them the 5m cables and they will rework them into 305cm cables.
They will ship them back to us on the 5th of May. We talk about
this at the morning meeting and decide to permanently use the 5m
cables for the "C" ADF Crate. So 3 of the 4 crates will get the
cable length purchased for them and crate "C" will get a 5m cables
instead of the 305 cm cable that we ordered. Sent a note to Johnny
and bosses saying that we would keep the 5m cables.
Work on actually installing cables with Mike and Sulcuk. It takes
about 1 to 1 1/2 hour do install the cables for 2 TABs We installed
cables for TABs 0 and 7 then mike and Jaro tested. Crate "C" with
no Pre-Emphasis and 5m cables did not look good. I added 3k Ohm
Pre-Emphasis to Crate "C" and now it looks OK.
To cards C14:C21 and D1:D12 i.e. all of the cards from Crate "C"
and to cards D13:D22 from Crate "D" put on 3k Ohm Pre-Emphasis.
Now all cards in Crates "C" and "D" have 3k Ohm Pre-Emphasis.
The current Pre-Emphasis plan based on a ton of pictures by Ted and
Jaro from the 3GHz scope with 1.7GHz diff probes is:
Installed Current Optimum
ADF LVDS Cable Pre-Emphasis Pre-Emphasis
Crate Length Resistor Resistor
----- ---------- ------------ ------------
A 365 cm 9 k 3 k
B 245 cm 1 meg 4.3 k
C 500 cm 3 k 3 k or perhaps less
D 425 cm 3 k 3 k
The plan is to run this way until all of the cables are in and
then evaluate the situation.
Mike and Ted and Jaro also noticed that a TAB channel with a missing
bypass cap on a Channel Link PLL Vcc would not lock at all. Once
the cap was re-installed the channel worked OK. There are two PLL
Vcc caps on each channel.
By chance I learned from Jaro that the ICD channels are supposed
to have a Zero Energy Response (pedestal) of 0. Jaro had email
notes from Hal from late 2004 or early 2005 saying this. I have
no recollection of this.
All 100 of the Amphenol cable connectors for four coax ribbon
cables have been taken from the MSU storage drawers under our work
bench. John said that he was only going to take the connectors that
he needed and that he was not going to take the whole sack. They
have left the sack on the MCH-1 floor along with a lot of other
waiting to be stepped on or tripped over.
------------------------------------------------------------------------------
DATE: 3:5-APR-2006 At: Fermi TOPICS: Work on Run IIB L1 Cal Trig,
Scheduled Power Outage, Work on Master
Clock, Network work, multics, New Firmware
in the TFW Readout Crate
I forgot to log it at the time but I think this is the trip on which all the
firmware in the TFW Readout Crate (the VIPA readout crate in M124) was
brought up to date. That is the TFW readout was given current VRB, VRBC, and
SCL Receiver firmware. I should have logged this at the time.
Monday: Scheduled Power Outage for substation switch over.
Pull the 2nd Sequencer from the Master Clock Crate. The 2nd
Sequencer ran only the Run I Level 1 Cal Trig.
Swap the PCC modules in the Master Clock. Pull out the spare from
CDF and install one of the two D-Zero PCC modules that have the new
Steve Chappa PLL circuit board in it.
At turn on run the Master Clock PCC in Normal Mode and the ClockGui
appears to work OK with just the one Sequencer in the crate.
Update the document for turning on the Master Clock and downloading it.
Send a note about the DAQ Shifter Check List for MCH-1: only one
sequencer to check, new RMIs for the new L1 Cal Trig to check.
Still need to: verify that the Alarms for the 2nd Sequencer have
been removed from the SES, and still need to update the MSU cold
start procedure, which is now only for: TFW, SCL hub-end, and
Routing Master.
To get the RM to work we had to do the now "normal" 2nd boot of its
SCB (by pressing the reset button on its SBC). Is this due to the
RM being turned on before the L3 System is ready for it, before the
"L3_Master" thing is ready to take care of waking up the RM's SBC ?
Tuesday: Lab 8 capacitance measurements. Not soldered "solder connections"
on plane "C". Thus I could not get real data.
The SUN workstation has not been able to get of fsite since mid
afternoon on Monday. OK the problem is that the network folks
changed their setup . The solution is:
edit /etc/defaultrouter_fnal
change 131.225.224.200 to 131.225.227.200
cp defaultrouter_fnal defaultrouter
edit /etc/inet/netmasks_fnal
change 131.225.0.0 255.255.0.0
to 131.225.0.0 255.255.252.0
cp netmasks_fnal netmasks
Wednesday: Scan the 256 BLS signals in M103 with the scope and record all
of the amplitudes. Do we want, can we actually use this pulser
amplitude information for anything ?
The Pulser ADC was set to 2000. The hadronic signals have
a strong "M" shape. Things look more or less OK. The
problems are:
noticable noise on +3,3 HD- and +3,4 HD-
+1,11 EM not symmetric: +1,11 EM+ 2.68 +1,11EM- 3.34
Missing diff signal +2,28 HD+ 0.632 +2,28 HD- zero
Low amplitude signal: +4,29 HD 0.480 (norm about 0.63)
Missing diff signal +2,30 HD+ zero +2,28 HD- 0.656
Need to look up which TTs have broken BLS crate backplane pins
and thus a missing side of the differential signal. OK this
information is in the log book entry for 10:13-DEC 2002.
The broken pins are at:
-2,1 HD M104 Broken BLS Backplane
center conductor pin.
BLS HD- signal is OK.
Broken pin on HD+ signal.
-2,5 HD M104 Broken BLS Backplane
center conductor pin.
BLS HD+ signal is OK.
Broken pin on HD- signal.
Remaining things on the technicians todo list: Install the
Can-Bus cables, clean up the RMI - RM cables in M106:M109,
do not cut cable try fingers at this time.
------------------------------------------------------------------------------
DATE: 20:24-MAR-2006 At: Fermi TOPICS: Work on Run IIB L1 Cal Trig, Power
Supply Monitoring,
Monday:
The RM boxes on time of M122 that provided power supply monitoring for both
the old L1 Cal Trig and for the TFW were mostly disconnected when the old
L1 Cal Trig was removed. But we still need them both. Specifically we still
need to monitor:
Voltage Monitor Signals Listed in Shea Box Channel Order
--------------------------------------------------------------
Original Rev. 15-JAN-2003
Current Rev. 20-MAR-2006
Shea Box Remote Terminal = 25
Shea Box Voltage Monitor Signal
Analog ---------------------------------------------------------
Channel Power Supply Rack Eta Phi Crate Type
-------- ---------------- ---- -------------------- ----------
0:31 Channels 0:31 in this Shea Box are not currently used
32 +5.0 Volt supply M101 Bottom Crate Routing Master
33 +3.3 Volt supply M101 Bottom Crate Routing Master
34 -2.0 Volt supply M101 Bottom Crate Routing Master
35 -4.5 Volt supply M101 Bottom Crate Routing Master
36 +5.0 Volt supply M101 Mid & Top Crates L1 Cal Trig Readout
37 +3.3 Volt supply M101 Mid & Top Crates L1 Cal Trig Readout
38 -2.0 Volt supply M101 Mid & Top Crates L1 Cal Trig Readout
39 -4.5 Volt supply M101 Mid & Top Crates L1 Cal Trig Readout
40:63 Channels 40:63 in this Shea Box are not currently used
Shea Box Remote Terminal = 26
Shea Box Voltage Monitor Signal
Analog ---------------------------------------------------------
Channel Power Supply Rack Eta Phi Crate Type
-------- ---------------- ---- -------------------- ----------
0:15 Channels 0:15 in this Shea Box are not currently used
16 +5.0 Volt supply M122 All Crates L2 TFW & Per Bunch Scalers
17 +3.3 Volt supply M122 All Crates L2 TFW & Per Bunch Scalers
18 -2.0 Volt supply M122 All Crates L2 TFW & Per Bunch Scalers
19 -4.5 Volt supply M122 All Crates L2 TFW & Per Bunch Scalers
20 +5.0 Volt supply M123 All Crates L1 TFW
21 +3.3 Volt supply M123 All Crates L1 TFW
22 -2.0 Volt supply M123 All Crates L1 TFW
23 -4.5 Volt supply M123 All Crates L1 TFW
24 +5.0 Volt supply M124 All Crates TFW Readout & SCL Hub-End & VME Comm
25 +3.3 Volt supply M124 All Crates TFW Readout & SCL Hub-End & VME Comm
26 -2.0 Volt supply M124 All Crates TFW Readout & SCL Hub-End & VME Comm
27 -5.2 Volt supply M124 All Crates TFW Readout & SCL Hub-End & VME Comm
28::63 Channels 28:63 in this Shea Box are not currently used
Note that the connections into M101 were cut when the old L1 Cal Trig was
removed. These need to be repaired before we return to Beam Physics running.
For now the decision was taken to keep these remaining signals spread across
two RMs even though they could all be stuffed into a single RM.
Monday afternoon at about 2:15 we get permission to move the Sidewalk equipment
into the MCH. Actually start work to make the move at about 4 PM. No problem
moving the stuff but once it is finally inside the real racks there are a
number of changes that need to be made in the way that equipment is arranged
in the racks. These changes are:
1. The heat exchanger hoses in the back of the ADF Crates block the access
to change the ADF Crate Power Supplies. Move these hoses/manifolds
down in racks M104, M106, M109, M111.
2. Move the RM out of the TAB/GAB Crate M107 to make more room for the
ADF to TAB LVDS cables. Move this RM to M106 ?
3. Notch or shorten the shelf brackets holding up the Pulizzi Boxes in
TAB/GAB Crate M107 and the Ctrl/Comm Crate M108 to make more room
for the ADF to TAB LVDS cables.
4. Move the TAB/GAB Crate M107 and the Ctrl/Comm Crate M108 down so that
they are on top of their heat exchangers to make more room for the
ADF to TAB LVDS cables.
5. Use cable trays inside the racks to carry the ADF to TAB LVDS cables.
Separate trays for the cables from each ADF Crate.
Use no cable ties.
Route these cable ways above the area of the ATC cards.
Use shelf brackets to support these cable ways about 4 inches
above the ADF Crates
PAB LArTPC meeting: move to Doc DB, 1/4 reports, another sample to MSU
Tuesday:
Discuss the required changes in the arrangement of equipment in the MCH racks
with John and Mike. They agree to the 5 changes.
Get the L1 Cal Trig TCC connected and running. It is on a shelf in M103.
It gets unswitched power from M104.
Edit the coor_resources.xml file as described in the previous log book entry.
Install the Vertical Interconnect cables. This includes moving the M101
Cal Trig Readout Crate i.e. the top crate in M101 over to control by the
L1 Cal Trig TCC. This leaves the M101 middle crate, i.e. the Quad Region
and Spark cards, and the M101 bottom crate, i.e. the Routing Master, under
control of the TFW TCC. The drawing of the Vertical Interconnect links
from the TFW TCC needs to be updated to show this change. The Vertical
Interconnect cables are all on top of the racks out of the way of the ADF
to TAB LVDS cables. They make use of the cable tray along the back of the
racks.
Install the SCLD cables from the SCLD card to the 4 ADF Crates. All of this
is on top of the racks, i.e. out of the way of the ADF to TAB LVDS cables.
Some of these SCLD runs are rather tight, well not tight but not much slack.
We need to limit who plays on top of these racks.
Run the 4 ADF Crates and the Comm/Ctrl Crate, and the TAB-GAB Crate and the
M101 L1 Cal Trig Readout Crate. VME is working to all and I know that SCLD
timing is working to ADF Crate B.
At the end of this running cover up all the crate and pull the power cords
so that things are set for infrastructure work on Wednesday. There is still
mechanical work to do above the crates.
Wednesday:
Remove the 10 Spark cards, the Quad-Region card, and the old L1 Cal Trig
Helper card from the middle crate in rack M101. This leaves only the TOM
card with its Vertical Interconnect slave in the middle crate of rack M101.
The middle crate of M101 no longer serves any active function.
Unplug the remaining outputs from the Sequencer #2 in the Master Clock.
This should not hurt anything and it does not appear to hurt anything.
Unplugging this just disconnected the Master Clock Sequencer #2 outputs
that ran over to the old L1 Cal Trig Helper card in Mid M101. DAQ is still
running fine. As of this, no outputs fron Master Clock Sequencer #2 are
connected to anything. We can remover Master Clock Sequencer #2.
Put the aluminum covers back on top of the 24" cable trays on top of the
M103:M112 racks.
Work on the Voltage Monitoring cables for the two Power Supplies in rack
M101 that were accidentally cut when the old L1 Cal Trig was removed. The
workers did not screw anything up on this because these two cables were
looped through the old Cal Trig racks. I got the monitor lines for "M101C"
i.e. the Routing Master reconnected and could see its readout just fine in
the TFW monitor display. I reconnected the monitor lines for "M101AB" i.e.
the M101 Top VIPA crate for L1 Cal Trig readout and for M101 Mid the now
unused TFW style crate - but I could not see the power supply in the old Cal
Trig monitor display. I think that I could not see it because of some
display size issue with the old SUN xserver. When I asked for a small display
the display crashed with TK complaints. Anyway, Philippe moved the "M101AB"
power supply to the TFW monitor display and I can see it fine and it is
connected OK. I copied the new L1TFW.runme from Philipp's area to the
d0l1 rackmon area.
The VESDA check for the TFW M101, M122, M123, M124 will take place tomorrow
at 7:30 in the morning. The M122, M123, M124 pipe is 3/4" ID i.e.
284 sqmm. A 1/4" dia hole is 32 sqmm. A 0.13" dia hole (#30 drill) is
8.6 sqmm. M122 (the end of the pipe) has 5x 1/4" dia holes. M123 and M124
have 2x 1/4" and 3x 0.13" dia holes. This is a total of 340 sqmm of holes.
The crew did NOT arrive at 12 today as scheduled. Thus we got zero work done
on infrastructure and zero work done running the system. There were notes
from Hal implying that MSU was taking care of the TAB to VTM optical
components.
Thursday:
VESDA Test: air flow is at 52%, test smoke blows out, response at
about 20 seconds but not good.
SiDet LArTPC meeting: effect of det wire resistance, other wire types,
what have other groups thought about this, wire parameters to MSU.
With Sulcuk scan through all the channels in rack M110 using a scope with
the Precision Cal Pulser running. Found 4 shorted cables and about 4
bad Hybrids. Sulcuk has the details and will think about the record keeping.
Talk about record keeping and working with Cal folks on BLS problems.
Repair the shorted cables: -14,23 -16,23 -15,30 -13,31. Used the
normal tubing over the center contuctor repair and lifted only the center
conductor where possible. Pat suggests just squirting in varnish and
moving the connector to center the wire (e.g. as indicated by an Ohm meter)
and then letting it dry.
Put the back doors back on and put on the last of the major front panels.
Pull off the cardboard covers and put on the cords and run the system
(4x ADFs and Comm/Ctrl) for about 2 hours. Did a ton of VME I/O and all
looks OK.
Friday:
Finish the last of the front panels, meeting: focus on running over all else,
clean up sidewalk (tools cards net connections), Cables (move to eta 1, BLS HB
log, shorts Joshua), under fan cables, signs not to run.
Summary: 3 weeks to get from start of removal to Mike working in MCH.
2 days for removal of the Run I Level 1 Cal Trig.
3 days to complete most of the infrastructure installation.
6 hours to move the 6 sidewalk crates into the MCH and
get them running again.
What was done on the other 9 working days ?
------------------------------------------------------------------------------
DATE: 5:10-MAR-2006 At: Fermi TOPICS: Work on Run IIA L1 Cal Trig removal
and Run IIB L1 Cal Trig Infrastructure Installation
Return the repaired Wiener power supply to Fermi. It is currently stored
in the old Spare Power Supply Storage cabinet.
Sunday: Test CHTCR PROMs and CTFE PROMs pg 7 EM/HD pg 2 PxPy all OK
All PROM Tests were over +-1:16 1:32
Run the exerciser over +-1:16 1:32 pg7 EM/HD 0:3 EM,Tot,Veto
1k loops and 1M loops all OK
Run Find DAC +-1:20 1:32 EM/HD keep every 2 write TTI & Histo
Make 2 passes of Find DAC.
Monday: Pull all cards, all twist and flat cable, learn how to disassemble
the crates in place, pull about 1/4 of the crates and supplies,
get about 1/2 of the BLS cables protected, get out the East 8 pack
and two normal racks worth of radiators, get the blower and air
ducts down, pull out the M113 safety system and get things changed
over for VESDA protection of just the TFW and M101.
Tuesday: Finish removal of all crates and power supplies, get the rest of the
BLS cables protected, finish removal of all radiators and all
vertical yellow bars. All removal of the old system is finished.
Regular Tuesday trigger meeting - all time spent thinking of excuses
to delay moving.
Wednesday: Start new installation. Install vertical yellow tracks in their
new locations, install 2/3 of the shelf brackets, install all of
the RMIs and power distribution boxes, install 3 racks of Patch
Panel mechanical parts, route up and label the power distribution
box input cables, cable meeting and decide to go with GORE,
install new top covers on M102 & M113, .
Make the two new SCL cables (for the Saclay SCLD card and for
the Columbia VME/SCL card) 30 ft long. The Comm/Ctrl Crate
is in M108.
Need to bring 40 conductor cable to Fermi for And-Or Terms from
the GAB in M107 to the And-Or Term Patch Panel input on top of
M123.
Thursday: Make 4 cables, 20 pair twist-and-flat, to carry the And-Or Terms
From the GAB to the TFW. These cables are 20 feet long and labeled
L1 Cal #1:#4. Finish getting the water hooked up to the very nice
looking in rack manifolds. Check the Pulizzi distribution box
circuit breakers and edit the web file describiing what wall box
circuit breaker feeds what.
Friday: Switch the VESDA TFW interlock box over to running from the outlet
strip in M113 that is feed from breaker MCR 1B 20. Removed the
contactor box that had been feeding this and updated the file that
describes the AC power feed to the TFW and L1 Cal Trig. Back to a
full crew working today - expect all of the new infrastructure to be
installed by the end of the day.
The crew that worked on removal and then infrastructure installation is: John
foglesong, Mike Cherry, Victor Martinez, Shoua Moua, Bruce Merkle, Tim
Martin, and the Jim Fagan's second shift crew including Rolando Flores.
During this work no one was hurt, nothing wrong cut, and equipment damaged.
There was an And-Or Term called once per 5 seconds that came out of the
Run I MTG in the L1 Cal Trig. Clearly it is now gone. This was And-Or
Term 246.
When we cold start now, there are 1531 FPGAs configured in the TFW and 51
FPGAs configured in the Routing Master.
John Foglesong has a couple of drawings that we need access to, e.g. the
rack layout in the new L1 Cal Trig. One path to them is something like:
www.fnal.gov Fermilab at work divisions and sections Particle
Physics Division PPD Departments (pull down) Electrical Engineering
Projects (under quick links) D-Zero Run IIB L1 Cal Trig Cabling
Installation Installation Drawings Table of Contents
www-ppd.fnal.gov/EEDOffice-w/Projects/dzero/L1_Cal_Trig_Patch_Panel/default.html
Then you can dump the end of this and use either:
/INSTALLATION/434273--1.pdf or under
/pdf/M100-M113.pdf
I worked to get the two new Geographic Sections ready for the L1 Cal Trig in
the MCH. These are the Geographic Sections for the SCLD --> ADFs and for
the VME/SCL --> TAB/GAB in the MCH. These are setup as:
0 : NR 124 7C L1CalADF M108-0 L1 Cal Trig
SCLD card --> ADFs
0 : NR 125 7D L1CalTAB M108-0 L1 Cal Trig
VME/SCL -->
TABs & GAB
I also need to completely remove:
0 : NR 126 7E L1CALRH M101-1 L1 Cal Trig
Data Source
I have edited the MSU maintained Official Crate List but I was not able
to edit the coor_resources.xml file in /online/data/coor/resources/
because it is currently owned by bartlett group d0. What is currently in
the coor_resources.xml is:
...
------------------------------------------------------------------------------
DATE: 22:24-FEB-2006 At: Fermi TOPICS: Work on ADF to TAB Communications
Brought soldering equipment to Fermi and replaced the 1 Meg Ohm pre-emphasis
resistors on all ADF-2 cards in crates "A" (0) and "D" (3) with 9.09 k
Ohm 0603 resistors. This moves the Channel Link Transmitters on these cards
from zero pre-emphasis to the middle level pre-emphasis.
This middle level of pre-emphasis was picked from scope traces that Ted
could make looking right at the 500 MHz LVDS with a good scope and fancy
differential probes. Full pre-emphasis has over and under shoot. Middle
level looks very good with a very good eye pattern.
Then worked with the 120 links from crates "A" and "D" and tried to make
all of these links work. So far the "fix" apprears to be replacing the
AMP cable with an ERNI cable. Mike tests this with 600 starts in an
over night run. Then move the 3 ERNI cables to other flaky links and
test with 600 starts again.
Ted sees line to line skew of about 0.5 nsec between different lines in
some of the AMP cables.
We could have an underlying problem, for example either of:
AMP cable line to line skew that is hard for this version of the
Channel Link Receiver with its 1/3 bit cell skew compensation to
deskew properly.
Is there a problem caused by the missing 8th link data line screwing
up the control information between the Channel Link transmitter and
receiver or screwing up the deskewing operation because of no edges
on the 8th link data line.
Recomendations given to the project managers:
Dump the AMP cables.
Purchase Meritec cables in two lengths: shorter cables for the two
inner ADF Crates (better Channel Link signals and less slack cable
to coil up) and longer cables for the two out rigger ADF Crates.
Add middle level pre-emphasis to all ADF-2 cards in the two out
rigger ADF Crates. We may or may not want to increase from zero
the pre-emphasis on the ADF-2 cards in the two inner ADF Crates.
Wednesday night the Tevatron pops a magnet in F sector and the long
delayed shutdown starts.
------------------------------------------------------------------------------
DATE: 15:17-FEB-2006 At: Fermi TOPICS: Work on ADF to TAB Communications
Brought the Denis Saclay Channel Link Tester and its PC back to D-Zero.
Made many many tests on various ADF to TAB links under different conditions.
The details of these three days of ADF to TAB Channel Link Tests are
available on paper but I not going to copy them into this web log book at
this time.
Basic conclusions:
All but one of the 280 links work some of the time and all 280
fail some of the time. I.E there is a system wide problem.
Links that frequently fail with the 5m AMP cable never fail with
the short AMP cable (both working through the ATC card).
Some AMP cables working through the ATC fail very frequently.
ERNI cable working through the ATC typically fails about once
in 45 starts.
Add mid level pre-emphasis to the ADF-2 Channel Link Transmitter
and the ERNI cable working through the ATC appears to always work.
------------------------------------------------------------------------------
DATE: 1:3-FEB-2006 At: Fermi TOPICS: ADF Crate "B" Power Supply, ADF to
TAB Communication,
Mike had spotted that the ADF Crate "B" power supply looked funny last
week and he turned it off. Its +5V digital supply was floppying around.
It looked like it would over current and then shutdown and then try to
start up again. This must have been very hard on the ADF-2 cards especially
the DC/DC converters.
I verified that there was a problem and would characterise it as starting
when more than 16 Amps or so is drawn from the supply. This looks mostly
like it involves just the +5 Digital supply in that power chassis. Swapping
with the supply from a different crate and then Crate "B" ran fine.
So pull power supply SN# 5196006 from ADF Crate "B" and install in the crate
the spare power supply which is SN# 5196009. ADF Crate "B" now runs fine.
The second problem was that people have changed many of the settings for
these supplies. The ADF Crate "A" supply +3.3 brick was set to crowbar
at 4.5 Volts. I will put signs on these supplies saying not to play with
them.
I one at a time power cycled and watched the start up of all 4 ADC Crates.
They all have current draw within the range shown below:
U0 U1 U3 U5
+5.0 V +5.0 V +3.3 V -5.0 V
Digital Analog Analog Analog
------- ------ ------ ------
Stable Power 10.5 A 9.3A
Not Configured 13A 10.8 A 10A 9.6A
Configured but 10.5 9.3
Not Initialized 16 10.8 6 to 7 9.5
Initialized and 10.5 34 9.3
Running T7_Phy 17 10.8 35 9.6
See the log book entry from 29-NOV,2-DEC-2005 for information about
the turn on current spike.
See the log book entry from 26:28-OCT-2005 about Wiener Crate Serial
Numbers. The current setup is:
ID of the 4 ADF Crates:
ADF-2 Crate Power Supply MSU Property
Crate Serial Number Serial Number Tag Number
----- ------------- ------------- ------------
A 5196039 5196008 017734
B 5196041 5196009 017721
C 5196038 5196007 017760
D 5196040 5196010 017747
Lyn does not know which ADF Crate had its backplane pins repaired
last summer.
Setup of all 4 of the ADF Crates
ADF U0 U1 U3 U5
Crate +5.0 V +5.0 V +3.3 V -5.0 V
Setting Digital Analog Analog Analog
------- ------- ------ ------ ------
Ilim 80 A 20 A 80 A 20 A
Uadj 0 % 0 % 0 % 0 %
Unom 5.00 V 5.00 V 3.29 V 5.00 V
OVP 6.25 V 6.25 V 3.50 V 6.25 V
Imax 70 A 16 A 70 A 16 A
Umin 4.75 V 4.75 V 3.10 V 4.75 V
Umax 5.25 V 5.25 V 3.50 V 5.25 V
Fans 3300 rpm
CAN-Bus Address ADF Crate "A" = 1 ... ADF Crate "D" = 4
Notes:
Ilim is the supply's output current limit.
Uadj is the fine adjustment on the supply's output Voltage.
Unom is the coarse adjustment on the supply's output Voltage.
OVP is the trip point for the supply's Over Voltage Protection.
Imax is the maximum current that may be drawn from the supply
and still have it report "good" status to the monitoring.
Umin is the minimum output Voltage that can be coming from the
supply and still have it report "good" to the monitoring.
Umax is the maximum output Voltage that can be coming from the
supply and still have it report "good" to the monitoring.
The +5V digital supply and the +3.3V supply are both 115A bricks
The +- 5V analog supplies are both 30A bricks.
During investigation of ADF to TAB problems, to help guess what might
be wrong in the chain, I asked Jorge where he found most of the
problems during production testing. The answer is: 5 bad ATCs out of
80 and 7 bad LVDS cables out of 240.
Repaired some number of bent pin problems at the back of the TAB/GAB
backplane. These were all mild bends that could be straighted. I
think that they were all pin going into adjacent hole problems. An
interesting point is that once the input funnel is scuffed up then
that cable connector does not seem to work well any longer.
Specifically if the cable connector has ever been used to bend a pin,
then that action seems to scuff the tappered input ramp to the hole
and make it much much more likely that that connector will bend more
pins. You can feel that it is not right during insertion.
Techniques: use an old junk ATC as a mechanical fixture to test cables
on. Use the fluke meter on DC Volts to look for juice on cables.
Normal line with a signal on them read about 1.2V. Open pins read 0V.
Shorted pins read 0.9V The two sides of a differential pair read
different enough values that you can be confident that you are not
reading twice the same side of a differential pair. Can check just
the cable by plugging it into the old ATC to get access to the signals
or probe from the card side of the TAB/GAB crate. We straightened
pins and replaced cables in 6 places on the back of the TAB/GAB backplane.
There is one seriously bent pin on the card side of the TAB/GAB backplane.
There is no silkscreen lettering at all on the TAB/GAB backplane on
either side. It is hard to navigate.
George confirms that there is not yet a known timing shift that I should
take action on for the TFW.
------------------------------------------------------------------------------
DATE: 22:23-JAN-2006 At: Fermi TOPICS: L1 Cal Trig M113 Water Leak
L1 Cal Trig tripped off Saturady afternoon 21-Jan-06. It was powered back
up and then tripped off again at about 17:00. Norm told them not to power
it again and the Ops Shifter started looking for the water leak. It was
found in M113.
Arrive early evening 22-Jan-06. The leak is on the next to the bottom
radiator in M112 on the side of the "8 pack" that is next to the electronics
in M112. The "8 packs" do not have as good of shielding as the rest of the
system but I do not think that the electronics was sprayed. The shiled were
wet and a vertical yellow bar was wet. I'm not going to pull cards in M112
to look - but I did look from the front with a flashlight.
It was a standard leak right where the radiator pipe goes into the header.
It was hard to reach. I could not get at it with the wire brush at all.
Spend one hour scraping with a screw driver and working with Scotch Bright
and then put on the magic epoxy. The water flow was shut off and a joint
opened to dump the water pressure. Ran overnight with just the blower
running and had no additional trips.
In the morning I startted the supplies and ran diagnostics:
CHTCR PROM, EM-HD PROM pg 7, and Px-Py PROM pg 2
eta +- 1:16 all phi. Made 2 passes through each check.
Ran the exerciser: eta +-1:16 all phi, EM/HD towers, Page 7,
EM-Tot-HD_Veto Ref Sets, check global qty. Ran 500k, 500k,
500k, 500k, and 1 Meg.
Looked at HSRO data from L1 Cal Trig and it looks OK. Studied the power
supply display and: M111B -2V and M110B -5.2V are a couple of the
worst.
------------------------------------------------------------------------------
DATE: 19:21-JAN-2006 At: Fermi TOPICS: SCL Cable Work, Checked out L1
Cal Trig, Installation meeting, Wire Pulser to Lab 8,
Purple Haze Noise, Verified SCL Cable length with FPD,
New L1 Cal Trig Installation Meeting
For the two new DFEA2 crates on the platform connect up two new Geographic
Sections. These are G.S. $1A and $1B. The new DFEA2 crates will be in
rack PC03. They will run using existing spare SCL cables to the platform
(which have been located). Plug in these at the SCL Hub-End as follows:
G.S. 0x1a will use cable 01SCL077 Spare PC03
G.S. 0x1b will use cable 01SCL079 Spare PC19
Next an L2 person thinks that they need two more G.S. routed to the L2 Test
Stand on 2nd FCH. They think that they need these because they think that
a given G.S. is hardwired to a given set of L1 Triggers. I give up trying to
introduce them to the D-Zero DAQ System and just tied up these optical SCL
runs. These 2 G.S. have always been prommised to the L2 Test Stand so now
they have them. Install 2 more Optical SCL boxes in the L2 Test Stand. I
already had two duplex optical cables run to the L2 Test Stand so un-duplex
them (as had been done for other runs) and put labels on everything. There
are only 7 SCL Cu to Optical transmitters down at the Hub-End. There was only
one not in use so I could only fire up one of the new runs to the L2 Test
Stand but I tested all of it and verified what cables was which. The
Geograohic Sections used for this are: $0C and $0D. It is $0D that still
needs a transmitter at the Hub-End. The runs to the L2 Test Stand that
existed before today are: $0A and $0B. All 4 of these runs are optical.
All of this DFEA2 and L2 Test Stand stuff is in the Official Crate List.
Ran the L1 Cal Exerciser and checked: CHTCR PROM, EM-HD PROM pg 7, and Px-Py
PROM pg 2 all for eta +- 1:16 all phi. Made 2 passes through each check.
Then ran the exerciser: eta +-1:16 all phi, EM/HD towers, Page 7, EM-Tot-HD
Veto Ref Sets, check global qty. Made two passes of 1 meg each with 0 errors.
Ran the power supply monitor display and I hope that things will hold together
for another 6 weeks.
Worked with Doug at Lab8. The 21m wires are setup. The noise level is
not too bad. Running the 10 pFd preamps and have 2x 27k Ohm in the pulser
probe. We tied up and pulsed a wire and then went to the middle and pulsed
and compared the amplitudes. No change. I left the preamp board with its
power supply, the trigger optical to electrical board with its power supply,
and the pulser and its probe all at Lab 8. I'm signed up to work there on
the next trip. Doug is going to ask Carl Lindenmeyer to two run copper wires
parallel to and above and spread out from the wire plane array. This is for
pulser grounding and to use to support and aluminum foil shielding tent.
Renewed user ID.
Verified with Duncan that the SCL Cable to FPD with the 32 nsec extension
in it is now OK and that the 32 nsec extension should be left in permanently.
Meeting with Alan and Fohn F and Linda about L1 Cal Trig Installation. Go
through the lists of tasks from Alan and John.
------------------------------------------------------------------------------
DATE: 4:6-JAN-2006 At: Fermi TOPICS: SCL Cable for FPD, PHN scope setup,
Recall the previous L1 timing change,
Meeting about installation of new Cal Trig.
Duncan Brown asked that the SCL cable to the FPD readout crate, Geographic
Section 0x12, be lengthened by about 30 nsec. I added a 32 nsec section of
LMR200 cable to the run. The added cable is at the Hub_End as was used for
testing with other systems some years ago. LMR200 cable has a Velocity
Factor of 0.83
More scope setups for the Purple Haze Noise (PHN) checks. Now there is a
second scope in the collision hall that is remote controlled. The scope
trigger signal from the L1 Cal Trig (20 Jet TT over 7 GeV) was run into
the collision hall on coax. The Diff ECL to Scope Box is now used to drive
this signal. Made an adapter cable so that Dean can tap the collision hall
scope onto the PreAmp signals coming into the back of a BLS Crate.
During a shot early Friday AM Dean and Norm captured a number of Purple
Haze events after the Store was under way (i.e. not during injection or
scrapping). The collision hall scope shows that the individual preamp
outputs stays well within their linear range and that they have a
1.75 MHz oscillation during PHN. The oscillation is in the form of pulses
of order 80 nsec duration. The biggest signal was about 1/10 full scale
preamp output and came from a channel with its detector element nearest the
cryostat wall.
The MCH Scope setup prior to Thursday evening 5-JAN-2006 was:
Channel #1 Yellow Had TT signal +2,15
Channel #2 Blue Had TT signal +4,15
Channel #3 Violet Had TT signal +2,18
The MCH Scope setup Thursday evening and Friday morning was:
Channel #1 Yellow Had TT signal +4,15
Channel #2 Blue Had TT signal +2,18
Channel #3 Violet Had TT signal +2,15
The MCH Scope setup starting Friday morning at 11:15 AM now is:
Channel #1 Yellow Had TT signal +4,15
Channel #2 Blue Had TT signal +2,18
Channel #3 Violet Had TT signal +5,14
Review the last Level 1 Trigger latency change. The last time that the
L1 Accept timing was changed was 25:27-SEPT-2002. From a note with
Dmitri on 30-SEPT-2002.
"Since the timing was moved last week, the TFW issues the L1 Decision
about 3.63 usec after the beam crossing. That is when the L1 Decision
leaves the TFW. This is 27.5 "ticks".
The L1 Decision then passes through:
the SCL Hub-End,
the SCL cable to detector system,
the SCL Receiver
and is then finally available to the detector system electronics.
These steps take about 480 nsec (for cable runs to MCH-3).
So the L1 Decision reaches the detector system electronics on MCH-3
about 4.11 usec after the beam crossing. This is about 31 "ticks".
MCH-1 and MCH-2 are about 26 nsec less. Platform (the CFT and SMT
Sequencer Controllers) is about 125 nsec more."
Meeting with John Anderson and John Foglesong and others about the
installation of the new L1 Cal Trig. Went through a list of tasks.
I must verify cooling with the top and bottom of the racks closed.
I signed up for: pulling out M102 and M113 RPSS, reconnect Vesda,
verify no power in racks, ID cables to be saved.