!
!
!                     Master Clock Signals for the
!
!          Trigger Framework, SCL Hub-End, Level 0 Luminosity
!                          and CFT LED Pulser
!
!
!                       Original Rev.  29-MAR-1999
!                        Current Rev.  25-MAY-2006
!
!
!  Note: See the reference information at the end of this file.

!
!
!  This file will be used to setup the following Master Clock Time Lines
!  Recall that TL0:TL11 are the Static TL's  and  TL12:TL22 are Dynamic
!
!      Time Line         Function                      Used By
!      ---------     ------------------------     -----------------------
!         TL0        FW Tick Clock                Framework
!         TL1        TRM Tick Clock               Framework
!         TL2        Beginning of Turn Marker     FW & AO Net Input & SCL
!         TL3        Interaction Marker                AO Net Input & SCL
!         TL4        Cosmic Gap Marker                 AO Net Input & SCL
!         TL5        Sync Gap Marker              FW & AO Net Input & SCL
!         TL6        Spare Marker                      AO Net Input & SCL
!         TL7        Helper Function Tick Clock   Framework
!         TL8        SCL Tick Clock               SCL

!         TL9        Subsystem Strobe             "NIM" Trigger Input
!        TL10        Subsystem Gap                "NIM" Trigger Input

!        TL11        L0_LUM_TDC_Stop              L0_LUM
!        TL12        L0_LUM_Live_BX_Clock         L0_LUM
!        TL13        L0_LUM_Tick_Clock            L0_LUM
!        TL14        L0_LUM_Gap_Signal            L0_LUM

!        TL15        free - spare                 -

!        TL16        CFT_LED_4                    CFT_LED_Pulser_4
!        TL17        CFT_LED_1                    CFT_LED_Pulser_1
!        TL18        CFT_LED_2                    CFT_LED_Pulser_2
!        TL19        CFT_LED_3                    CFT_LED_Pulser_3

!        TL20        Tick 43,57,96,110  first last Cosmic Gap   AO Net Input
!        TL21        First Interaction in Super Bunch           AO Net Input
!        TL22        Last Interaction in Super Bunch            AO Net Input




!
!
!                     Modification List
!  -----------------------------------------------------------

!   3-APR-01  D.E.   The Framework appears to be sending out L1_Acpts
!   about 32 RF buckets late.  So move just the FW and the SCL earlier
!   in time by 32 RF buckets.   To do this move FW and SCL stuff earlier
!   by 32 RF buckets.
!   This was done by moving the  FW_OS  from  -5  to  -37  and
!   moving the   SCL_OS  from  +0  to  -32.
!
!   ALL SubSystem Strb & Gap signals remain where they are.  To do this
!   the FW_OS was removed from their definitions and the  Subsys_Stb_OS
!   which had been  +5  picked up the old -5 FW_OS  so  Subsys_Strb_OS
!   is now 0     while    Subsys_GAP_Dl which had been -32 picked up the
!   old  -5 FW_OS  so  Sybsys_Gap_Dl is now -37.
!
!   There is no change to the Lo_Lum signals or to the CFT_LED siganls.
!   They did not include the FW_OS or the SCL_OS so there nothing needed
!   to be done to keep then in their same place.


!   4-APR-01  D.E.   Now we want to move to sending out the "Current BX"
!   information "6 ticks early".  Note that this is really now a spread
!   of 33 ticks (Current BX to L1 Decision BX)  were as we have been
!   running with a spread of 26.  So this is a change of 7 ticks or
!   49 RF Buckets.  Only the Trig FW and the SCL move.  SubSystem Strb
!   and Gap do not move and L0_Lum does not move and CFT LED does not
!   move.   So just change  FW_OS from -37 to -86  and change SCL_OS
!   from -32 to -81.
!   On a separate topic move the BC_Trig earlier by 154 RF Buckets to
!   get an initial alignment of it to the real beam crossings.
!

!   5-APR-01  D.E.   All gap signal are short by 1 RF Bucket.  They should
!   119 RF buckets long and right now they are 118 RF buckets long.  This
!   did not cause a problem for the SCL signals because they are "sampled"
!   only once every 7 RF buckets.   The starting point of the Sync Gap
!   and Cosmic Gap and Sub System gap is correct so they just need to be
!   one tick longer.  For L0 Lum  make it one tick longer and move it back
!   by one tick.

!   2-MAY-01  D.E.  Work on the Sub-System Gap and Strobe signals.  TL_9
!   is Strobe and TL_10 is Gap.  Make the Stobe asserted for 2 RF Buckets
!   instead of just 1.  Move the Gap 2 ticks later so that the NIM And-Or
!   terms spend 2 ticks less time in the TRM input FIFO.

!   1-JUNE-01   D.E.   Setup on Time Line #15 a very temporary test pulse
!   to fire the Calorimeter Pulser.   This is just for a test.

!   7-JUNE-01   D.E.   Move the Sync_Ref signal forward by 605 RF buckets
!   to compensate for the new fiber optic TeV_Sync signal coming at a 
!   different time than the old copper one.

!   9-AUG-01    D.E.   Make Time Line 21  asserted for the first
!   interaction crossing in each of the 3 Super Bunches.   Make Time
!   Line 22  asserted for the last interaction crossing in each of the
!   3 Super Bunches.   These two time lines will be  used only as an
!   input to the And_Or Network.    Note that if we change the spread
!   between Current Time Zone and L1 Decision Time Zone that the offset
!   of these signals will need to be adjusted.

!   17-AUG-01   D.E.   The CFT people would like to have their 2nd  CFT
!   LED Pulser Time Line (i.e. TL=18)  moved so that it is 320.4 nsec
!   after their first LED Pulser Time Line (i.e. TL=17).     320.4 divided
!   by 18.831 is just about 17 RF buckets.  So I will make TL 18 follow
!   TL 17 with a delay of 17 RF Buckets.

!   29-AUG-01   D.E.   The CFT people would like to have their 2nd  CFT
!   LED Pulser Time Line (i.e. TL=18)  moved so that it is 472 nsec
!   before their first LED Pulser Time Line (i.e. TL=17).   472 nsec divided
!   by 18.831 is just about 25 RF buckets.  So I will make TL 18 lead
!   TL 17  by  25 RF Buckets.

!   14-SEP-01   D.E.   The CFT people would like to have their 3rd  CFT
!   LED Pulser Time Line (i.e. TL=19)  moved so that it is 800 nsec
!   after their first LED Pulser Time Line (i.e. TL=17).   800 nsec divided
!   by 18.831 is just about 42 RF buckets.  So I will make TL 19  42 RF
!   Buckets behind TL 17.

!   01-MAR-02   D.E.
!   Drop the very temporary test trigger to the CAL Pluser that was TL15
!   and make TL15 a free spare. 
!   Move CFT LED Pulser Number 4 from  TL20  to TL16.   TL16 had been a
!   free spare.   No change to the setup of this CFT LED Pulser signal
!   number 4.  The other 3 CFT LED Pulser signals, i.e. TL17, TL18, and TL19
!   were not touched.
!   Make TL20 into an And-Or Term that is asserted for Ticks 43, 57, 96, 110.
!   These are the first and last "crossings" during each of the two
!   Cosmic Gaps.  This has the same timing arrangement as the TL21 and TL22
!   i.e. the first and last accelerator crossing in each Super Bunch.

!   11-APR-02  D.E.
!   Change the position of the 3rd CFT LED Pulser,  i.e. Time Line 19,  from
!   791 nsec After the 1st CFT LED Pulser, i.e. Time Line 17,  to  866 nsec
!   Before it.

!   18-SEPT-02  D.E.   We are changing the timing to issue the L1_Acpt 2 ticks
!   later.  Normally this would not require touching the Master Clock except
!   that we now have 3 And-Or Terms that come directly from the CMC Time Lines.
!   These are:
!
!        TL20    Tick 43,57,96,110  first last Cosmic Gap    AO Net Input
!        TL21    First Interaction in Super Bunch            AO Net Input
!        TL22    Last Interaction in Super Bunch             AO Net Input
!
!   The offset value used for all three of these is currently +211.  Normally
!   one would just add 14 to this to move these signals 2 ticks later.  But
!   currently they are being generated rather late in the window that gets
!   them to the TFW in time with the correct BX.  So I'm only going to add
!   12 to the current offset to make the new offset +223.  This should give
!   2 RF Buckets of hold time and 5 RF Buskets of setup time on these signals
!   at the TFW.
!
!   The other change made in this interation is to start generating the BC_REF 
!   signal for all 36 beam crossings and to line it up with the PD beam pickup
!   signal.  Recall that BC_REF runs the beam crossing phase detector and also
!   is available on the front panel output.  To line this up should be easy 
!   because we know that it is 995 or 996 nsec from the current BC_TRIG signal
!   to the middle of the PD signal.   So just generate the BC_REF signal 996 ns
!   divided by 18.83 ns/bucket = 53 RF Buckets later than the BC_TRIG signal.

!   18-SEPT-02  D.E.   Would like to move the BC_REF signal 2 RF Buckets
!   earlier.  We started generating it in the last update to this file.
!   Right now the BC_REF signal is about 38 nsec after the center of the PD
!   signal so a 2 RF Bucket move should just about make them match.

!   10-APR-03  D.E.   Rich Partridge needs another Master Clock signal for
!   the Luminosity Monitor system.  This is the Stop signal for his new TDC
!   cards.  This will be put on Time Line #11.   It is a 132 nsec Clock just
!   like his other Tick Clock which is on TL #13.

!   25-MAY-06  D.E.   We are moving the L1_Acpt latency so that the L1_Acpt
!   will be issued from the TFW 3 ticks later than it has been for the past
!   4 years.  All of this L1_Acpt latency change is taken care of in the
!   TFW itself except for 3 And-Or Terms that are generated simply as Time
!   Lines in the #1 Sequencer.  The offset for these 3 time lines will need
!   to be increased by 21 RF Buckets, i.e. 3 ticks x 7 RF Buckets per tick.
!   The three time lines, which directly become And-Or Terms, and thus need
!   to be adjusted are:
!
!   Time Line 20    Ticks 43,57,96,110  Live Cosmic BX      And-Or Term 241
!   Time Line 21    First Interaction in any Super Bunch    And-Or Term 249
!   Time Line 22    Last Interaction in any Super Bunch     And-Or Term 250
!
!   This change is implemented by:
!
!      change  Live_Cosmic_BX_Dl  from  223  to  244
!      change  Fst_BX_in_SB_Dl    from  223  to  244
!      change  Lst_BX_in_SB_Dl    from  223  to  244








!   Use of OFFSETs in the Definition of the Time Lines
!   -------=======------------------------------------

!  In general three different offsets will be used in the definition
!  of a Time Line.

!    The Global Offset is included in the definition of ALL Time Lines.  It
!    allows us to rotate the entire pattern with respect to the Accelerator.

!    Next each system (e.g. FW SCL CAL) has a system offset that is included
!    in just the Time Lines of that system.  This allows us to easily move
!    one system with respect to the rest.  If a signal is used by more than
!    one system then it is assigned the system offset of its principal
!    consumer.

!    Finally each signal in a given system will typically include an offset
!    for just that signal.  This signal specific offset typically will not
!    include the fixed known understandable timing offset of that signal
!    with respect to the other signals in its system.  The fixed known part
!    is typically included as an integer appearing in the definition of the
!    Time Line and described in the accompanying text.


!  So first let's assign the Global Offset value for ALL Master Clock Signals.

Assign  Glb_OS =  +619   !  Global Offset to be used by all signals





!  First let's setup the time signals that control the operation of
!  the Master Clock Sequencer Module.

!  Setup the Sync_Ref signal that is internally compared to the once per
!  turn Sync_Inp signal from the PCC Module.

Set SYNC Up 606 For 1




!  Setup the BC_Ref signal that is internally compared to the signal
!  BC_Inp from the proton beam pickup.

Assign  BC_Ref_OS  =  -104          ! Alignment to match BX_REF and
                                    ! the PD beam pickup signal.

Set  BCREF  Up  BC_Ref_OS +140    For  1
Set  BCREF  Up  BC_Ref_OS +161    For  1
Set  BCREF  Up  BC_Ref_OS +182    For  1
Set  BCREF  Up  BC_Ref_OS +203    For  1
Set  BCREF  Up  BC_Ref_OS +224    For  1
Set  BCREF  Up  BC_Ref_OS +245    For  1
Set  BCREF  Up  BC_Ref_OS +266    For  1
Set  BCREF  Up  BC_Ref_OS +287    For  1
Set  BCREF  Up  BC_Ref_OS +308    For  1
Set  BCREF  Up  BC_Ref_OS +329    For  1
Set  BCREF  Up  BC_Ref_OS +350    For  1
Set  BCREF  Up  BC_Ref_OS +371    For  1

Set  BCREF  Up  BC_Ref_OS +511    For  1
Set  BCREF  Up  BC_Ref_OS +532    For  1
Set  BCREF  Up  BC_Ref_OS +553    For  1
Set  BCREF  Up  BC_Ref_OS +574    For  1
Set  BCREF  Up  BC_Ref_OS +595    For  1
Set  BCREF  Up  BC_Ref_OS +616    For  1
Set  BCREF  Up  BC_Ref_OS +637    For  1
Set  BCREF  Up  BC_Ref_OS +658    For  1
Set  BCREF  Up  BC_Ref_OS +679    For  1
Set  BCREF  Up  BC_Ref_OS +700    For  1
Set  BCREF  Up  BC_Ref_OS +721    For  1
Set  BCREF  Up  BC_Ref_OS +742    For  1

Set  BCREF  Up  BC_Ref_OS +882    For  1
Set  BCREF  Up  BC_Ref_OS +903    For  1
Set  BCREF  Up  BC_Ref_OS +924    For  1
Set  BCREF  Up  BC_Ref_OS +945    For  1
Set  BCREF  Up  BC_Ref_OS +966    For  1
Set  BCREF  Up  BC_Ref_OS +987    For  1
Set  BCREF  Up  BC_Ref_OS +1008   For  1
Set  BCREF  Up  BC_Ref_OS +1029   For  1
Set  BCREF  Up  BC_Ref_OS +1050   For  1
Set  BCREF  Up  BC_Ref_OS +1071   For  1
Set  BCREF  Up  BC_Ref_OS +1092   For  1
Set  BCREF  Up  BC_Ref_OS +1113   For  1





!  Setup the BC_Trig signal.  This signal is available only on a front
!  panel Lemo and can be setup to match when the BX's happen in the 
!  center of the D-Zero detector.

Assign  BC_Trig_OS  =  -155         ! Initial alignment to real BX
                                    ! in center of D-Zero.

Set  BCTRIG  Up  BC_Trig_OS +140    For  1
Set  BCTRIG  Up  BC_Trig_OS +161    For  1
Set  BCTRIG  Up  BC_Trig_OS +182    For  1
Set  BCTRIG  Up  BC_Trig_OS +203    For  1
Set  BCTRIG  Up  BC_Trig_OS +224    For  1
Set  BCTRIG  Up  BC_Trig_OS +245    For  1
Set  BCTRIG  Up  BC_Trig_OS +266    For  1
Set  BCTRIG  Up  BC_Trig_OS +287    For  1
Set  BCTRIG  Up  BC_Trig_OS +308    For  1
Set  BCTRIG  Up  BC_Trig_OS +329    For  1
Set  BCTRIG  Up  BC_Trig_OS +350    For  1
Set  BCTRIG  Up  BC_Trig_OS +371    For  1

Set  BCTRIG  Up  BC_Trig_OS +511    For  1
Set  BCTRIG  Up  BC_Trig_OS +532    For  1
Set  BCTRIG  Up  BC_Trig_OS +553    For  1
Set  BCTRIG  Up  BC_Trig_OS +574    For  1
Set  BCTRIG  Up  BC_Trig_OS +595    For  1
Set  BCTRIG  Up  BC_Trig_OS +616    For  1
Set  BCTRIG  Up  BC_Trig_OS +637    For  1
Set  BCTRIG  Up  BC_Trig_OS +658    For  1
Set  BCTRIG  Up  BC_Trig_OS +679    For  1
Set  BCTRIG  Up  BC_Trig_OS +700    For  1
Set  BCTRIG  Up  BC_Trig_OS +721    For  1
Set  BCTRIG  Up  BC_Trig_OS +742    For  1

Set  BCTRIG  Up  BC_Trig_OS +882    For  1
Set  BCTRIG  Up  BC_Trig_OS +903    For  1
Set  BCTRIG  Up  BC_Trig_OS +924    For  1
Set  BCTRIG  Up  BC_Trig_OS +945    For  1
Set  BCTRIG  Up  BC_Trig_OS +966    For  1
Set  BCTRIG  Up  BC_Trig_OS +987    For  1
Set  BCTRIG  Up  BC_Trig_OS +1008   For  1
Set  BCTRIG  Up  BC_Trig_OS +1029   For  1
Set  BCTRIG  Up  BC_Trig_OS +1050   For  1
Set  BCTRIG  Up  BC_Trig_OS +1071   For  1
Set  BCTRIG  Up  BC_Trig_OS +1092   For  1
Set  BCTRIG  Up  BC_Trig_OS +1113   For  1







!  Now Program the Trigger Framework Time Lines
!  ----------------=================-----------

!  Note that many of these lines are used by both the FW and the SCL.

!  Recall that all Framework Timing Signals are delayed by 2 periods of
!  the 53 MHz clock in the BSF FPGA.  To get from the Master Clock to the
!  Trigger Framework the timing signals travel through about 30 feet, i.e.
!  18 sections of twist and flat cable.  This is about 50 nsec.  Therefore
!  the Carmen Master Clock signals to the Framework must run about 88 nsec
!  AHEAD of the actual time that they cause action in the Framework.

!  Assign the offset to be used by all Trigger Framework signals.
!  Start FW signals 5 Ticks (about 88 nsec) ahead of time.

Assign  FW_OS  =  -86


!  Program the FW Tick Clock which is Time Line 0
!  -----------=========--------------------------

!  Assign the Tick Clock offset.

Assign  FW_Tick_OS  =  0   ! Tick Clock marks the start of a FW Tick.
                           ! This signal is used only by the Framework.

!  The Tick Clock is up at 0, 7, 14..... and should be up for 1 bucket only.

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +0     For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +7     For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +14    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +21    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +28    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +35    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +42    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +49    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +56    For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +63    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +70    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +77    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +84    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +91    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +98    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +105   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +112   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +119   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +126   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +133   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +140   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +147   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +154   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +161   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +168   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +175   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +182   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +189   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +196   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +203   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +210   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +217   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +224   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +231   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +238   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +245   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +252   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +259   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +266   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +273   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +280   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +287   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +294   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +301   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +308   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +315   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +322   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +329   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +336   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +343   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +350   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +357   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +364   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +371   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +378   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +385   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +392   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +399   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +406   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +413   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +420   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +427   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +434   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +441   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +448   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +455   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +462   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +469   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +476   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +483   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +490   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +497   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +504   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +511   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +518   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +525   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +532   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +539   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +546   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +553   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +560   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +567   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +574   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +581   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +588   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +595   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +602   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +609   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +616   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +623   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +630   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +637   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +644   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +651   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +658   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +665   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +672   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +679   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +686   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +693   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +700   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +707   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +714   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +721   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +728   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +735   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +742   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +749   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +756   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +763   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +770   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +777   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +784   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +791   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +798   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +805   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +812   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +819   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +826   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +833   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +840   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +847   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +854   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +861   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +868   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +875   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +882   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +889   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +896   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +903   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +910   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +917   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +924   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +931   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +938   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +945   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +952   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +959   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +966   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +973   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +980   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +987   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +994   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1001  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1008  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1015  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1022  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1029  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1036  For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1043  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1050  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1057  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1064  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1071  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1078  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1085  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1092  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1099  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1106  For  1





!  Now program the Trigger Framework TRM Clock which is Time Line 1
!  ---------------------------------=====--------------------------

!  It should be 1 bucket later than the Tick Clock and otherwise identical.
!  So the TRM Clock is up at 1, 8, 15..... and should be up for 1 bucket only.

!  Assign the TRM Clock offset.

Assign  FW_TRM_OS  =  +1   ! TRM Clock starts 18.8 nsec into the FW tick.
                           ! This signal is used only by the Framework.


Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +0     For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +7     For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +14    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +21    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +28    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +35    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +42    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +49    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +56    For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +63    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +70    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +77    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +84    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +91    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +98    For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +105   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +112   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +119   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +126   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +133   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +140   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +147   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +154   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +161   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +168   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +175   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +182   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +189   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +196   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +203   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +210   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +217   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +224   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +231   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +238   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +245   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +252   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +259   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +266   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +273   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +280   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +287   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +294   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +301   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +308   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +315   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +322   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +329   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +336   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +343   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +350   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +357   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +364   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +371   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +378   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +385   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +392   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +399   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +406   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +413   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +420   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +427   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +434   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +441   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +448   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +455   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +462   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +469   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +476   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +483   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +490   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +497   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +504   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +511   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +518   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +525   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +532   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +539   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +546   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +553   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +560   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +567   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +574   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +581   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +588   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +595   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +602   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +609   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +616   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +623   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +630   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +637   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +644   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +651   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +658   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +665   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +672   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +679   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +686   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +693   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +700   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +707   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +714   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +721   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +728   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +735   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +742   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +749   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +756   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +763   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +770   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +777   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +784   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +791   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +798   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +805   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +812   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +819   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +826   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +833   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +840   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +847   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +854   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +861   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +868   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +875   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +882   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +889   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +896   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +903   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +910   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +917   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +924   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +931   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +938   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +945   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +952   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +959   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +966   For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +973   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +980   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +987   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +994   For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1001  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1008  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1015  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1022  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1029  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1036  For  1

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1043  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1050  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1057  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1064  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1071  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1078  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1085  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1092  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1099  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1106  For  1





!  Now program the Beginning of Turn marker which is Time Line 2
!  ----------------=================----------------------------

!  This is the once per accelerator turn marker.  It should be up for
!  7 buckets and should rise 3 buckets before the FW Tick Clock.
!  The Beginning of Turn Marker is used both by the FW and the SCL.
!  The SCL must send out this signal early enough so that it reaches
!  front-end by the actual beginning of turn.  Note also that the
!  FW needs it 1 tick earlier (for its Tick and Turn Scalers) then
!  when the SCL should receive it.

!  Assign the Beginning of Turn Marker delay.

Assign  Beg_Trn_Dl  = -31       ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

!  Assign the Beginning of Turn Marker offset.

Assign Beg_Trn_OS  = +98        ! The offset indicates the RF Bucket
                                ! that we are aiming for out in the 
                                ! Geo Section.  This is chosen so that
                                ! the first live crossing in Super Bunch #1
                                ! corresponds to Current Crossing #7.

Set  T2  Up  Glb_OS+FW_OS+Beg_Trn_Dl+Beg_Trn_OS  For  7





!  Program the  Interaction Marker  Signal which is Time Line 3
!  ------------====================----------------------------

!  The Interaction Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  one tick long and occurs for each of the 36 crossings in an
!  accelerator turn

!  Assign the Interaction Marker delay.

Assign  Interaction_Dl = -31    ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +140    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +161    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +182    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +203    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +224    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +245    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +266    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +287    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +308    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +329    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +350    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +371    For  7

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +511    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +532    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +553    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +574    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +595    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +616    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +637    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +658    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +679    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +700    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +721    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +742    For  7

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +882    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +903    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +924    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +945    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +966    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +987    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1008   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1029   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1050   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1071   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1092   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl +1113   For  7





!  Program the  COSMIC GAP Marker  Signal which is Time Line 4
!  ------------===================----------------------------

!  The COSMIC GAP Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  asserted during the gap between Super Bunch 1 and Super Bunch 2
!  and during the gap between Super Bunch 2 and Super Bunch 3.

!  Note that as defined near the top of this file the gap between
!  SB #1 and SB #2  begins with RF Bucket 372.  However, the Cosmic
!  Gap marker will not be asserted until the RF Bucket which would 
!  contain a live crossing if this were not a gap, i.e. RF Bucket 392.
!  The same is true for the Cosmic Gap between SB #2 and SB #3, it does
!  not start until RF Bucket 763.

!  Assign the COSMIC GAP Marker delay.

Assign  COSMIC_Gap_Dl  =  -31   ! The delay is  an integral 
                                ! multiple of 7 RF Buckets.  It
                                ! It reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set T4  Up Glb_OS+FW_OS+COSMIC_Gap_Dl+392  For  119
Set T4  Up Glb_OS+FW_OS+COSMIC_Gap_Dl+763  For  119





!  Now program the  Sync GAP Marker  which is Time Line 5
!  ----------------=================---------------------

!  This is the once per accelerator turn marker.  It is
!  asserted during the gap between Super Bunch 3 and Super Bunch 1
!  and is exactly the same as Cosmic Gap markers.  That is, it is
!  asserted when the next live crossing would happen if this were not a gap
!  and remains active until just before the next live crossing.
!  The Sync Gap Marker is used both by the FW and the SCL and is also
!  an And-Or Network input.
!  The SCL must send out this signal early enough so that it reaches
!  front-ends by the time that we need Sync Gap to occur.   This signal
!  will be delayed in the FW for its use in the TRM's and as an And-Or
!  Network input.

!  Assign the Sync Gap Marker delay.

Assign  Sync_GAP_Dl = -31       ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! It reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3


Set  T5  Up  Glb_OS+FW_OS+Sync_GAP_Dl+21  For  119





!  Now program the  Spare Marker  signal which is Time Line 6
!  ----------------==============----------------------------

!  The Spare Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  very similar to the Interaction Marker in that it is
!  one tick long and occurs for each of the 36 crossings in an
!  accelerator turn.  The only difference is that the Spare Marker 
!  continues through the gaps.  At some point during the gap (currently
!  in the middle) the Spare Marker "stutters", i.e. is asserted
!  after only 14 RF Buckets instead of the usual 21.  This allows the
!  Spare Marker to be correctly aligned with the Interaction Marker
!  after the gap.

!  Assign the Spare Marker delay.

Assign  Spare_Dl = -31          ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Spare Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+140    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+161    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+182    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+203    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+224    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+245    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+266    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+287    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+308    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+329    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+350    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+371    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+392    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+413    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+434    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+448    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+469    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+490    For  7

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+511    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+532    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+553    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+574    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+595    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+616    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+637    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+658    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+679    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+700    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+721    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+742    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+763    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+784    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+805    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+819    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+840    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+861    For  7

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+882    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+903    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+924    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+945    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+966    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+987    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1008   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1029   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1050   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1071   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1092   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1113   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+21     For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+42     For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+63     For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+77     For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+98     For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+119    For  7





!  Now program the Framework HELPER Function Clock which is Time Line 7
!  --------------------------=====================---------------------

!  It should be 2 bucket later than the Tick Clock and otherwise identical.
!  So the HELPER Clock is up at 2, 9, 16... and should be up for 1 bucket only.

!  Assign the HELPER Clock offset.

Assign  FW_HELP_OS  =  +2   ! HELPER Clock starts 37.7 nsec after the FW tick.


Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +0     For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +7     For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +14    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +21    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +28    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +35    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +42    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +49    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +56    For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +63    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +70    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +77    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +84    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +91    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +98    For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +105   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +112   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +119   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +126   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +133   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +140   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +147   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +154   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +161   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +168   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +175   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +182   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +189   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +196   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +203   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +210   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +217   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +224   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +231   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +238   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +245   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +252   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +259   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +266   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +273   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +280   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +287   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +294   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +301   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +308   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +315   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +322   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +329   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +336   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +343   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +350   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +357   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +364   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +371   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +378   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +385   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +392   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +399   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +406   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +413   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +420   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +427   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +434   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +441   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +448   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +455   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +462   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +469   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +476   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +483   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +490   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +497   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +504   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +511   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +518   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +525   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +532   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +539   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +546   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +553   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +560   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +567   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +574   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +581   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +588   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +595   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +602   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +609   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +616   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +623   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +630   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +637   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +644   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +651   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +658   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +665   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +672   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +679   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +686   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +693   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +700   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +707   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +714   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +721   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +728   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +735   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +742   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +749   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +756   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +763   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +770   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +777   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +784   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +791   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +798   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +805   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +812   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +819   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +826   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +833   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +840   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +847   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +854   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +861   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +868   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +875   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +882   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +889   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +896   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +903   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +910   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +917   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +924   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +931   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +938   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +945   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +952   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +959   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +966   For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +973   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +980   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +987   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +994   For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1001  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1008  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1015  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1022  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1029  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1036  For  1

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1043  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1050  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1057  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1064  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1071  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1078  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1085  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1092  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1099  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1106  For  1







!  Now Program the SCL Hub-End Time Lines
!  ----------------===========-----------

!  The signals generated for use only by the SCL Hub-End are the following:

!         TL8        SCL Clock, Frame Clk, 132 nsec Clk

!  First assign the offset to be used by all the SCL Hub-End signals.
!  For now start with SCL signals with zero offset.

Assign  SCL_OS  =  -81


!  Program the SCL FRAME Clock  which is Time Line 8
!  ---------------=============----------------------------------

!  The SCL Frame Clock is the once every 132 nsec clock that defines
!  "ticks" i.e. frames for the SCL.  It is distributed to the Front-Ends.
!  It is one RF Bucket long and and occurs once every 7 RF Buckets (132 nsec).

!  Assign the SCL Frame Clock offset.

Assign  SCL_TICK_OS  =  +3     ! SCL Frame Clock offset   It is set 57 nsec
                               ! after the FW Tick Clk to allow transport
                               ! and setup of the FW data in the SCL.


Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +0     For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +7     For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +14    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +21    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +28    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +35    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +42    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +49    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +56    For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +63    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +70    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +77    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +84    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +91    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +98    For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +105   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +112   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +119   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +126   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +133   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +140   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +147   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +154   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +161   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +168   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +175   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +182   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +189   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +196   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +203   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +210   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +217   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +224   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +231   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +238   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +245   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +252   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +259   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +266   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +273   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +280   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +287   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +294   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +301   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +308   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +315   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +322   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +329   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +336   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +343   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +350   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +357   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +364   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +371   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +378   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +385   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +392   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +399   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +406   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +413   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +420   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +427   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +434   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +441   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +448   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +455   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +462   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +469   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +476   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +483   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +490   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +497   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +504   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +511   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +518   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +525   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +532   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +539   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +546   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +553   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +560   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +567   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +574   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +581   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +588   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +595   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +602   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +609   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +616   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +623   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +630   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +637   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +644   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +651   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +658   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +665   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +672   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +679   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +686   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +693   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +700   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +707   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +714   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +721   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +728   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +735   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +742   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +749   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +756   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +763   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +770   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +777   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +784   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +791   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +798   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +805   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +812   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +819   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +826   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +833   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +840   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +847   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +854   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +861   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +868   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +875   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +882   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +889   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +896   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +903   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +910   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +917   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +924   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +931   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +938   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +945   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +952   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +959   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +966   For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +973   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +980   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +987   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +994   For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1001  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1008  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1015  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1022  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1029  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1036  For  3

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1043  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1050  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1057  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1064  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1071  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1078  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1085  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1092  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1099  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1106  For  3







!  Now program the Subsystem Strobe which is Time Line 9
!  ----------------================----------------------

!  It should be 5 buckets later than the Tick Clock and up for 3 RF buckets.
!  So the Subsystem Strobe is up at 5, 12, 19.......

!  Assign the Subsystem Strobe offset.


Assign  Subsys_Stb_OS  =  +0    ! Subsys Strobe starts 5 RF
                                ! buckets into the Tick Clock
                                ! This comes from FW_OS being -61 which is
                                ! which is 7 ticks plus 5 RF buckets.


Set  T9  Up  Glb_OS+Subsys_Stb_OS  +0     For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +7     For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +14    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +21    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +28    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +35    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +42    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +49    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +56    For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +63    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +70    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +77    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +84    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +91    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +98    For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +105   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +112   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +119   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +126   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +133   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +140   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +147   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +154   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +161   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +168   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +175   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +182   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +189   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +196   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +203   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +210   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +217   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +224   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +231   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +238   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +245   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +252   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +259   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +266   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +273   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +280   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +287   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +294   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +301   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +308   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +315   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +322   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +329   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +336   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +343   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +350   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +357   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +364   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +371   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +378   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +385   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +392   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +399   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +406   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +413   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +420   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +427   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +434   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +441   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +448   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +455   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +462   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +469   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +476   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +483   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +490   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +497   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +504   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +511   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +518   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +525   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +532   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +539   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +546   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +553   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +560   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +567   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +574   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +581   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +588   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +595   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +602   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +609   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +616   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +623   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +630   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +637   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +644   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +651   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +658   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +665   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +672   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +679   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +686   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +693   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +700   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +707   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +714   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +721   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +728   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +735   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +742   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +749   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +756   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +763   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +770   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +777   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +784   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +791   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +798   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +805   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +812   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +819   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +826   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +833   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +840   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +847   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +854   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +861   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +868   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +875   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +882   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +889   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +896   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +903   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +910   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +917   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +924   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +931   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +938   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +945   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +952   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +959   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +966   For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +973   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +980   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +987   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +994   For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1001  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1008  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1015  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1022  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1029  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1036  For  2

Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1043  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1050  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1057  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1064  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1071  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1078  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1085  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1092  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1099  For  2
Set  T9  Up  Glb_OS+Subsys_Stb_OS  +1106  For  2





!  Now program the  Subsystem GAP Marker  which is Time Line 10
!  -----------------====================-----------------------

!  This is a once per accelerator turn marker.  It should rise 4 buckets
!  before the Subsystem Strobe and be asserted for 118 RF Buckets.
!  The Subsys Gap Marker is used by the FW and can also be an
!  And-Or Network input.
!  The Subsys Gap Marker mimics the gap signal coming from a front end.
!  It should be delayed relative to the Sync Gap Marker to account for
!  the delay between the front end and the framework, taken to be about
!  300 ns.

!  Assign the Subsys Gap Marker delay.

Assign  Subsys_GAP_Dl = -37     ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  
                                ! In this case, the delay is derived from
                                ! the corresonding delay for the Sync Gap.
                                ! In addition this signal should be
                                ! generated 4 RF Buckets before the Subsys
                                ! Strobe. So its value should be -Nx7 -4
                                ! This is relative to the FW which is at a
                                ! 7 ticks and 5 RF buckets early.  So it is
                                ! -Nx7 -4 -5 

!  Assign the Subsys Gap Marker offset.

Assign Subsys_GAP_OS = +26      ! The offset indicates the RF Bucket
                                ! that we are aiming for.  This is
                                ! 3 Ticks (21 RF buckets) after the
                                ! Sync Gap.  Additionally, it should be
                                ! 5 RF buckets later to account for the
                                ! phase of the Subsys Strobe relative
                                ! to the Tick Clock.

!  Assign the Subsys Gap Adjust offset.

Assign Subsys_Adj_OS = 21       ! This allows the position of the
                                ! Subsystem Gap to be tweaked for
                                ! specific tests without
                                ! altering the two more fundamental
                                ! values.

Set  T10  Up  Glb_OS+Subsys_GAP_Dl+Subsys_Adj_OS+Subsys_GAP_OS  For 119





!  Setup the  L0 Luminosity  Time Lines 11, 12, 13, 14
!  ----------===============--------------------------

!  First assign the offset to be used by all the L0 Lum Master Clock signals.
!  For now start with zero offset.

Assign  LUM_OS  =  +0



!  Program the L0 Luminosity TDC Stop Signal on Time Line 11
!  Assing the offset for the L0 Luminosity TDC Stop Signal.

Assign LUM_Stop_Clk_OS = 5     ! Rich wants the Stop 13 RF Buckets
                               ! after the real BX in center D-Zero

Set  T11  Up  LUM_Stop_Clk_OS  +0     For  2
Set  T11  Up  LUM_Stop_Clk_OS  +7     For  2
Set  T11  Up  LUM_Stop_Clk_OS  +14    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +21    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +28    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +35    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +42    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +49    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +56    For  2

Set  T11  Up  LUM_Stop_Clk_OS  +63    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +70    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +77    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +84    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +91    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +98    For  2
Set  T11  Up  LUM_Stop_Clk_OS  +105   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +112   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +119   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +126   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +133   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +140   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +147   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +154   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +161   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +168   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +175   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +182   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +189   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +196   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +203   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +210   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +217   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +224   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +231   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +238   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +245   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +252   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +259   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +266   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +273   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +280   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +287   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +294   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +301   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +308   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +315   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +322   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +329   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +336   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +343   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +350   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +357   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +364   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +371   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +378   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +385   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +392   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +399   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +406   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +413   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +420   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +427   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +434   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +441   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +448   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +455   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +462   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +469   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +476   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +483   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +490   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +497   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +504   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +511   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +518   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +525   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +532   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +539   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +546   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +553   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +560   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +567   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +574   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +581   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +588   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +595   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +602   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +609   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +616   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +623   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +630   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +637   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +644   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +651   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +658   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +665   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +672   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +679   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +686   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +693   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +700   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +707   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +714   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +721   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +728   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +735   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +742   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +749   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +756   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +763   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +770   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +777   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +784   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +791   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +798   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +805   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +812   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +819   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +826   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +833   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +840   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +847   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +854   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +861   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +868   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +875   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +882   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +889   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +896   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +903   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +910   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +917   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +924   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +931   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +938   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +945   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +952   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +959   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +966   For  2

Set  T11  Up  LUM_Stop_Clk_OS  +973   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +980   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +987   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +994   For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1001  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1008  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1015  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1022  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1029  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1036  For  2

Set  T11  Up  LUM_Stop_Clk_OS  +1043  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1050  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1057  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1064  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1071  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1078  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1085  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1092  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1099  For  2
Set  T11  Up  LUM_Stop_Clk_OS  +1106  For  2




!  Program the L0 Luminosity Live BX Clock on Time Line 12
!  Assing the offset for the L0 Luminosity Live BX signal.

Assign LUM_BX_OS = 597            ! Timed to proton halo on 30-mar-01


Set  T12  Up  LUM_BX_OS +140    For  6
Set  T12  Up  LUM_BX_OS +161    For  6
Set  T12  Up  LUM_BX_OS +182    For  6
Set  T12  Up  LUM_BX_OS +203    For  6
Set  T12  Up  LUM_BX_OS +224    For  6
Set  T12  Up  LUM_BX_OS +245    For  6
Set  T12  Up  LUM_BX_OS +266    For  6
Set  T12  Up  LUM_BX_OS +287    For  6
Set  T12  Up  LUM_BX_OS +308    For  6
Set  T12  Up  LUM_BX_OS +329    For  6
Set  T12  Up  LUM_BX_OS +350    For  6
Set  T12  Up  LUM_BX_OS +371    For  6

Set  T12  Up  LUM_BX_OS +511    For  6
Set  T12  Up  LUM_BX_OS +532    For  6
Set  T12  Up  LUM_BX_OS +553    For  6
Set  T12  Up  LUM_BX_OS +574    For  6
Set  T12  Up  LUM_BX_OS +595    For  6
Set  T12  Up  LUM_BX_OS +616    For  6
Set  T12  Up  LUM_BX_OS +637    For  6
Set  T12  Up  LUM_BX_OS +658    For  6
Set  T12  Up  LUM_BX_OS +679    For  6
Set  T12  Up  LUM_BX_OS +700    For  6
Set  T12  Up  LUM_BX_OS +721    For  6
Set  T12  Up  LUM_BX_OS +742    For  6

Set  T12  Up  LUM_BX_OS +882    For  6
Set  T12  Up  LUM_BX_OS +903    For  6
Set  T12  Up  LUM_BX_OS +924    For  6
Set  T12  Up  LUM_BX_OS +945    For  6
Set  T12  Up  LUM_BX_OS +966    For  6
Set  T12  Up  LUM_BX_OS +987    For  6
Set  T12  Up  LUM_BX_OS +1008   For  6
Set  T12  Up  LUM_BX_OS +1029   For  6
Set  T12  Up  LUM_BX_OS +1050   For  6
Set  T12  Up  LUM_BX_OS +1071   For  6
Set  T12  Up  LUM_BX_OS +1092   For  6
Set  T12  Up  LUM_BX_OS +1113   For  6



!  Program the L0 Luminosity Tick Clock on Time Line 13
!  Assing the offset for the L0 Luminosity Tick Clock.

Assign LUM_Tick_Clk_OS = 0      ! Start with zero offset.


Set  T13  Up  LUM_Tick_Clk_OS  +0     For  1
Set  T13  Up  LUM_Tick_Clk_OS  +7     For  1
Set  T13  Up  LUM_Tick_Clk_OS  +14    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +21    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +28    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +35    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +42    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +49    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +56    For  1

Set  T13  Up  LUM_Tick_Clk_OS  +63    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +70    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +77    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +84    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +91    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +98    For  1
Set  T13  Up  LUM_Tick_Clk_OS  +105   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +112   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +119   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +126   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +133   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +140   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +147   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +154   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +161   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +168   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +175   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +182   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +189   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +196   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +203   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +210   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +217   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +224   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +231   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +238   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +245   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +252   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +259   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +266   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +273   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +280   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +287   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +294   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +301   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +308   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +315   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +322   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +329   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +336   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +343   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +350   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +357   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +364   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +371   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +378   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +385   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +392   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +399   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +406   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +413   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +420   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +427   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +434   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +441   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +448   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +455   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +462   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +469   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +476   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +483   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +490   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +497   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +504   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +511   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +518   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +525   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +532   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +539   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +546   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +553   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +560   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +567   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +574   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +581   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +588   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +595   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +602   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +609   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +616   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +623   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +630   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +637   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +644   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +651   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +658   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +665   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +672   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +679   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +686   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +693   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +700   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +707   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +714   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +721   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +728   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +735   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +742   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +749   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +756   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +763   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +770   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +777   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +784   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +791   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +798   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +805   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +812   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +819   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +826   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +833   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +840   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +847   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +854   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +861   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +868   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +875   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +882   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +889   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +896   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +903   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +910   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +917   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +924   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +931   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +938   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +945   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +952   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +959   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +966   For  1

Set  T13  Up  LUM_Tick_Clk_OS  +973   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +980   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +987   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +994   For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1001  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1008  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1015  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1022  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1029  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1036  For  1

Set  T13  Up  LUM_Tick_Clk_OS  +1043  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1050  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1057  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1064  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1071  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1078  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1085  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1092  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1099  For  1
Set  T13  Up  LUM_Tick_Clk_OS  +1106  For  1



!  Program the L0 Luminosity Gap signal on Time Line 14
!  Assing the offset for the L0 Luminosity Gap signal.

Assign LUM_Gap_OS = 626           ! Proper Phase wrt L0 Lum Strobe signal


Set  T14  Up  LUM_Gap_OS   For  119








!  Setup the currently not used Time Line 15 
!  -----------------------------------------

!  Time Line 15 is currently a free spare.  TL15 is spare.
!  Set it high.

Set T15 Up 1 For 1113







!  Now program the  CFT LED Pulser  which is Time Lines 16 Through 19
!  ----------------================----------------------------------

!  Note that the  4th CFT LED Pulser had been Time Line 20 and it now
!  is Time Line 16.

!  For now setup 4 of these CFT LED Pulser Time Lines in the same way.
!  It should be up 22 Ticks after BoT and up for 1 RF bucket.

!  First assign the offset to be used by all the CFT signals.
!  For now start with zero offset.

Assign  CFT_OS  =  +0

!  Assign the CFT LED Pulser Trigger offset.

Assign CFT_Pulser_OS = +221     ! The offset indicates the RF Bucket
                                ! that we are aiming for.  This is 
                                ! 22 Ticks (154 RF buckets) after the
                                ! Beginning of Turn.  

Set  T17  Up  Glb_OS+CFT_OS+CFT_Pulser_OS +   0  For 1
Set  T18  Up  Glb_OS+CFT_OS+CFT_Pulser_OS -  25  For 1
Set  T19  Up  Glb_OS+CFT_OS+CFT_Pulser_OS -  46  For 1
Set  T16  Up  Glb_OS+CFT_OS+CFT_Pulser_OS + 556  For 1








!  Setup First and Last "Crossing" in the Cosmic Gaps on Time Line 20
!  ------------------------------------------------------------------

!  This signal becomes an And-Or Term which is asserted for the first
!  and last "crossings" in each Cosmic Gap.  These are ticks 43, 57 and
!  96, 110.  These are the two crossings in each Cosmic Gap when both
!  the CFT and SMT detectors can properly handle L1_Accepts.  Note that
!  the setup of this signal is similar to TL21 and TL22.

!  Assign the Live Cosmic BX delay.

Assign  Live_Cosmic_BX_Dl = 244    ! The delay was adjusted to center this
                                   ! signal in the proper tick when the FW
                                   ! needs to ingest it.  Note that if we
                                   ! change the spread between Current Time
                                   ! Zone and L1 Decision Time Zone this will
                                   ! need to be adjusted.

Set  T20  Up  Glb_OS+FW_OS+Live_Cosmic_BX_Dl +392    For  7

Set  T20  Up  Glb_OS+FW_OS+Live_Cosmic_BX_Dl +490    For  7

Set  T20  Up  Glb_OS+FW_OS+Live_Cosmic_BX_Dl +763    For  7

Set  T20  Up  Glb_OS+FW_OS+Live_Cosmic_BX_Dl +861    For  7








!  Program the  First Interaction in Super Bunch  Signal which is Time Line 21
!  ------------==================================-----------------------------

!  The First Interaction in Super Bunch signal  is only used as an
!  And-Or Network Input Term.  It is one tick long and occurs for
!  the first interaction in each of the 3 super bunches in an
!  accelerator turn

!  Assign the First BX in Super Bunch delay.

Assign  Fst_BX_in_SB_Dl = 244      ! The delay was adjusted to center this
                                   ! signal in the proper tick when the FW
                                   ! needs to ingest it.  Note that if we
                                   ! change the spread between Current Time
                                   ! Zone and L1 Decision Time Zone this will
                                   ! need to be adjusted.

Set  T21  Up  Glb_OS+FW_OS+Fst_BX_in_SB_Dl +140    For  7

Set  T21  Up  Glb_OS+FW_OS+Fst_BX_in_SB_Dl +511    For  7

Set  T21  Up  Glb_OS+FW_OS+Fst_BX_in_SB_Dl +882    For  7

 


!  Program the  Last Interaction in Super Bunch  Signal which is Time Line 22
!  ------------=================================-----------------------------

!  The Last Interaction in Super Bunch signal  is only used as an
!  And-Or Network Input Term.  It is one tick long and occurs for
!  the last interaction in each of the 3 super bunches in an
!  accelerator turn

!  Assign the Last BX in Super Bunch delay.

Assign  Lst_BX_in_SB_Dl = 244      ! The delay was adjusted to center this
                                   ! signal in the proper tick when the FW
                                   ! needs to ingest it.  Note that if we
                                   ! change the spread between Current Time
                                   ! Zone and L1 Decision Time Zone this will
                                   ! need to be adjusted.

Set  T22  Up  Glb_OS+FW_OS+Lst_BX_in_SB_Dl +371    For  7

Set  T22  Up  Glb_OS+FW_OS+Lst_BX_in_SB_Dl +742    For  7

Set  T22  Up  Glb_OS+FW_OS+Lst_BX_in_SB_Dl +1113   For  7








!  <><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
!
!  Below here is some background reference information about how the
!  Master Clock is setup for the 36x36 running.   Everything below 
!  here is comment lines.


!  Before starting the actual description of the Master Clock Time Lines
!  the first part of this file is a description of the expected Run II
!  running configuration.
!
!  For the initial setup of Run II we will assume that we are running
!  with 396 nsec crossings in 3 Super Bunches of 12 crossings each.
!  Also let's number the RF Buckets as 1 through 1113.
!
!  Now if we want to divide the 1113 RF Buckets into 3 even pieces we could
!  arrange these as:
!
!      RF Buckets    1  through   371   called the first 3rd
!      RF Buckets  372  through   742   called the second 3rd
!      RF Buckets  743  through  1113   called the third 3rd
!
!
!  For 396 nsec crossings every 21 RF Buckets has particles in it.  We could
!  pick RF Bucket #1 as the beginning of a gap and then built everything
!  symmetrically in three even pieces and it would result in the following
!
!
!                            RF Bucket Number of the Crossing
!       Crossing        -------------------------------------------
!        in the             1st             2nd             3rd
!     Super Bunch       Super Bunch     Super Bunch     Super Bunch
!     -----------       -----------     -----------     -----------
!          1st              140             511             882
!          2nd              161             532             903
!          3rd              182             553             924
!          4th              203             574             945
!
!          5th              224             595             966
!          6th              245             616             987
!          7th              266             637            1008
!          8th              287             658            1029
!
!          9th              308             679            1050
!         10th              329             700            1071
!         11th              350             721            1092
!         12th              371             742            1113
!
!
!  For the set of RF Bucket numbers for the 36 crossings shown in the
!  table above, the 3 gaps between the Super Bunches would take place
!  between the following RF Bucket numbers.  Note that the gap is not
!  an integral number times 7 RF Buckets long.
!
!      Gap Between      This Gap Begins     This Gap Ends        Gap Lenght
!     Super Bunches      with RF Bucket     with RF Bucket    RF Buckets, nsec
!     -------------     ----------------    --------------    ----------------
!      SB 1 to SB 2          372                 510           139     2617.5
!      SB 2 to SB 3          743                 881           139     2617.5
!      SB 3 to SB 1            1                 139           139     2617.5
!
!  This table shows the Gap beginning at the RF Bucket immediately
!  following the last beam crossing of the Super Bunch before the
!  gap (see notes below concerning when the Gap Markers are asserted),
!  and the gap ending at the RF Bucket immediately before the
!  first beam crossing of the Super Bunch following the gap.
!
!  We will place the Beginning of Turn and the Sync Gap in the Gap
!  before Super Bunch #1.   The Gap between SB #1 and SB #2   and the
!  Gap between SB #2 and SB #3  will be called the Cosmic Gaps.
!
!
!