! ! ! Master Clock Signals for the ! ! Level 1 Calorimeter Trigger ! aka Second Sequencer ! ! ! Original Rev. 11-APR-2001 ! Current Rev. 12-NOV-2003 ! ! ! Note: See the reference information at the end of this file. ! ! ! This file will be used to setup the following Master Clock Time Lines ! Recall that TL0:TL11 are the Static TL's and TL12:TL22 are Dynamic ! ! Time Line Function Used By ! --------- ---------------------------------- ------------- ! TL0 CTFE ADC Clock Tier 1 ! TL1 CTFE Latch-Shift Clock Tier 1 ! TL2 CTFE 2X Clock Tier 1 ! TL3 CTFE X Clock Tier 1 ! TL4 CTFE Energy LUM Page Select Tier 1 ! TL5 CTFE Momentum LUM Page Select Tier 1 ! TL6 CHTCR Input Clock Tier 1 ! TL7 Energy Adder Tree CAT2 Clock Tier 1 ! TL8 Momentum Adder Tree CAT2 Clock Tier 1 ! ! TL9 Sub-System Strobe to Trig FW ! TL10 Sub-System Gap to Trig FW ! ! TL11 Tier 2 Counter Tree CAT2 Latch Clk Tier 2 ! also used by Tier 3 Momentum Tree CAT3 Tier 3 ! ! ! TL12 Sub-System Strobe 2nd copy to Trig FW ! TL13 Sub-System Gap 2nd copy to Trig FW ! ! TL14 Tier 3 Counter Tree CAT2 Latch Clk Tier 3 ! also used by Tier 4 Momentum Tree FMLN Tier 4 ! ! TL15 Tier 2 Momentum Tree CAT2 Latch Clk Tier 2 ! ! TL16 CT_FOM Input_Clk Quad_Terms ! TL17 CT_FOM Output_Clk Quad_Terms ! TL18 ! TL19 ! TL20 Input Clock to ERPB DC ERPB Readout ! TL21 EM/Tot Select to ERPB DC ERPB Readout ! ! TL22 ID Marker for Latch-Shift for 1st real BX in turn ! ! ! Modification List ! ----------------------------------------------------------- ! 11-APR-01 D.E. Initial Version. ! 12-APR-01 D.E. Adjust the position of the BC_Trig signal so that ! it is in the correct position relative to the L1 Cal Trig Signals. ! That is, move the whole pattern via the properly setting the SYNC ! signal position. ! 19-APR-01 D.E. Fix the X Clock pattern (make it 2 pulses) ! Add the Momentum MSB Address signal. Add the two CAT2 Tier 1 ! clocks. Add the Time Line 22 to mark the falling edge of Latch ! Shift that starts the processing of the Trigger Pickoff signal from ! the first real BX of a turn, i.e. the real BX that is labeled ! Current Tick #7. Further line it up with the beam by moving the ! SYNC signal position. ! 24-APR-01 D.E. Add the Tier 2 Counter Tree CAT2 Input Latch Clock ! Adjust the Sub-System Strobe and Gap to get things lined up on the ! natural 132 nsec boundaries. ! 2-MAY-01 D.E. Change the Sub-System Gap signal by 132 nsec to ! center the 3 ticks of aserted And-Or Terms around the tick where ! we want to fire, i.e. the "accelerator live crossing". ! 7-JUNE-01 D.E. Move the Sync_Ref signal forward by 605 RF buckets ! to compensate for the new fiber optic TeV_Sync signal coming at a ! different time than the old copper one. ! 4-OCT-01 D.E. Add the ERPB "Input Clock" on Time Line #20 and ! add the ERPB "EM/Tot Select" on Time Line #21 ! 6-OCT-01 D.E. Move the ERPB "Input Clock" on (TL 20) earlier ! by 6 RF Buckets. Move the and the ERPB "EM/Tot Select" (TL 21) ! earler by 7 RF Buckets. Move the CTFE Energy LUM Address line ! (TL 4) change to 2nd lookup later by 2 RF Buckets. ! 7-NOV-01 D.E. Move the ERPB "Input Clock" on Time Line #20 so that ! it goes up 4 RF Buckets after the ERPB "EM/Tot Select" goes up. In_Clk ! goes up for the second time 3 RF Buckets after EM/Tot comes back down. ! In_Clk is asserted for 4 RF Buckets. The first and second pulse offsets ! of In_Clk were 10 and 21 - now they are 19 and 29. Width was 3 now it ! is 4. ! 14-DEC-01 D.E. Make a second copy of the Sub-System Strobe signal, ! TL 9, on TL 12. Make a second copy of the Sub-System Gap signal, ! TL 10, on TL 13. ! 11-JUN-02 D.E. The generation of the L1 Cal Trig clock signals is ! modified to work with the Run II Timing & Control Distribution. ADC Clk ! TL_0 is moved 2 RF Buckets earlier. The rest of the L1 Cal Trig, i.e. ! TL_1:13 and TL_22, is moved 5 earler. The ERPB, TL_20,21, is not moved. ! Move earlier means reduce the values that control when the TL's are ! asserted. Do this by editing just the assigned offset values, i.e. leave ! the structure of this file as is. ! TR1_OS was 0 now -5 ! TR2_OS was 0 now -5 ! ADC_Clk_OS was -15 now -12 ! FP_ERPB_In_OS was +19 now +24 ! SP_ERPB_In_OS was +29 now +34 ! EM_Tot_OS was +15 now +20 ! 19-JUN-02 D.E. The changes made last week included changing by accident ! the location of the BC_Trig signal which is a problem because the FPD ! people use the BC_Trig signal from the #2 Sequencer as their beam crossing ! signal. So I need to move BC_Trig back where it belongs. I will do this ! by removing the TR1_OS from the lines that define BC_Trig. It also seems ! like a good idea to, at this time, remove CTFE_OS from the definition of ! BC_Trig. CTFE_OS is zero at this time. ! ! Also need to start generating the Tier 3 Counter Tree CAT2 Input Clock ! signal. This will be made on Time Line 14. It looks just like the ! Tier 2 Counter Tree CAT2 Input Clock signal but it runs 14 RF Buckets ! later. ! ! Because the Tier 3 Counter Tree Comparator outputs will now become the ! And-Or Terms, we need to change the Strobe and Gap signals being generated ! on Time Lines 9,10 and 12,13 to match when these Tier 3 signals are ! generated. Tier 3 is running 14 RF Buckets behind Tier 2 so just move ! the Srobe and Gap signal pairs 14 RF Buckets later (bigger number means ! later). ! Subsys_Stb_OS was +5 now is +19 ! Subsys_GAP_OS was +63 now is +77 ! 24-JULY-02 D.E. Need to implement the following changes: ! ! Move all Tier_1, Tier_2, and Tier_3 Timing_&_Control signals, ! except for the ADC_Clk, later by 7 RF_Buckets. ! ! Move the ADC_Clk later by 3 RF_Buckets. ! ! Move both the AOIT Strobe and Gap signals later by 7 RF_Buckets. ! ! Do not disturbe the timing signal that is sent to the ! Forward Proton system/room, i.e. BC_TRIG. ! ! Recall that to move things later means bigger numbers in the Time Line ! definition. This will be accomplished by making the following changes: ! ! TR1_OS is -5 now changed to +2 ! TR2_OS is -5 now changed to +2 ! TR3_OS is -5 now changed to +2 ! ! ADC_Clk_OS is -12 now changed to -16 ! deff includes TR1_OS ! ! Subsys_Stb_OS is +19 now changed to +26 ! Subsys_GAP_OS is +77 now changed to +84 ! ! Recall the Definition of the Time Lines Below ! Definition ! Includes ! Time Line Function Tier Offset ! --------- ---------------------------------- ------------ ! TL0 CTFE ADC Clock TR1_OS ! TL1 CTFE Latch-Shift Clock TR1_OS ! TL2 CTFE 2X Clock TR1_OS ! TL3 CTFE X Clock TR1_OS ! TL4 CTFE Energy LUM Page Select TR1_OS ! TL5 CTFE Momentum LUM Page Select TR1_OS ! TL6 CHTCR Input Clock TR1_OS ! TL7 Energy Adder Tree CAT2 Clock TR1_OS ! TL8 Momentum Adder Tree CAT2 Clock TR1_OS ! TL9 Sub-System Strobe - ! TL10 Sub-System Gap - ! TL11 Tier 2 Counter Tree CAT2 Latch Clk TR2_OS ! TL12 Sub-System Strobe 2nd copy - ! TL13 Sub-System Gap 2nd copy - ! TL14 Tier 3 Counter Tree CAT2 Latch Clk TR3_OS ! TL15 ! TL16 ! TL17 ! TL18 ! TL19 ! TL20 Input Clock to ERPB TR1_OS ! TL21 EM/Tot Select to ERPB TR1_OS ! TL22 ID Marker for Latch-Shift for TR1_OS ! 1st real BX in turn ! ! 1-AUG-02 D.E. The relative phase of Sub-System Gap and Sub-System ! Strobe look fine. But Sub-System Strobe is all screwed up wrt the AOT ! coming from the Cal Trig. Has it been this way since the new timing ! distribution was installed ?? It fires on 5,6,7 instead of 6,7,8. ! The rising edge of the Strobe is about 2 nsec after the AOT becomes ! asserted. I will move Strobe and Gap 3 RF Ticks earlier and then ! verify which BX's it fires on. ! ! Subsys_Stb_OS is +26 now changed to +23 ! Subsys_GAP_OS is +84 now changed to +81 ! 4-APR-03 D.E. We are turning on the Missing Et part of the L1 Cal Trig. ! TL15 so far has not been used. Setup TL15 as the Tier 2 Momentum Tree ! CAT2 Input Latch Clk. That is the only functional change to this file ! but also note that: ! ! TL11 which until now had only been used for the Tier 2 Counter Tree ! CAT2 Latch Clk will now also be used for the Tier 3 Momentum ! Tree CAT3 Latch Clk. ! ! TL14 which until now had only been used for the Tier 3 Counter Tree ! CAT2 Latch Clk will now also be used for the Tier 4 Momentum ! Tree FMLN Input Clk. ! ! This file should then match the 11-OCT-2002 Timing Diagrams. ! 12-NOV-03 D.E. We are turning on the Quad_Terms part of the L1 Cal Trig. ! So far TL16 and TL17 have not been used. ! ! Setup TL16 as the CT_FOM Input_Clk. For now TL16 looks much like ! the Tier 2 Counter Tree Input Latch Clk which is TL11. ! ! Setup TL17 as the CT_FOM Output_Clk. For now TL17 looks much like ! the Tier 3 Counter Tree Input Latch Clk which is TL14. ! Setup Sequencer Control Signals ! ---------------------------------------- ! First let's setup the time signals that control the operation of ! the Master Clock Sequencer Module. ! Setup the Sync_Ref signal that is internally compared to the once per ! turn Sync_Inp signal from the PCC Module. Set SYNC Up 1091 For 1 ! Setup the BC_Ref signal that is internally compared to the signal ! BC_Inp from the proton beam pickup. Set BCREF Up 1 For 1 ! The definition of the BC_Trig signal is at the end of this file where ! it has access to various assigned logical values. ! Use of OFFSETs in the Definition of the Time Lines ! -------=======------------------------------------ ! In general two different offsets will be used in the definition ! of a Time Line. ! ! Let's have an offset for each Tier in the L1 Cal Trig. This may make ! it easier to optimize timing considering the long calbes that typically ! run between Tiers. ! ! Let's include an offset for each group of signals that run one type ! of card in a given Tier in the L1 Cal Trig, e.g. CTFE ! Note how the various signals are defined wrt the falling edge of the ! CTFE F399 Latch-Shift Clock. This is the edge that begins the ! digital part of the processing of a beam crossing. The signals that ! occur before this in the processing of a given beam crossing are ! defined wrt this edge and given a negative offset. The transitions ! in control signals tht occur after the falling edge of Latch-Shift ! for the processing of a given beam crossing are defined using a ! positive offset wrt the falling edge of Latch-Shift for that beam ! crossing. This remains true even of the transition is in the next ! block of 396 nsec. This way of defining the signals keeps everything ! rational. The definition of the control signals for a given beam ! crossing are all defined wrt the falling edge of Latch-Shift that is ! the reference for that beam crossing. ! Program the Time Lines that Control Tier 1 ! --------------------------------------====== Assign TR1_OS = +2 ! The offset for all Tier 1 Time Lines ! Program the CTFE Time Lines ! ------------====----------- Assign CTFE_OS = 0 ! Program the CTFE ADC Clock which is Time Line 0 ! ------------==============--------------------- Assign ADC_Clk_OS = -16 ! ADC Clock Offset Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T0 Up ADC_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Program the CTFE Latch-Shift Clock which is Time Line 1 ! ------------======================--------------------- Assign Ltch_Shft_Clk_OS = -10 ! Latch-Shift Clock Offset Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 119 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 140 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 161 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 182 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 203 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 224 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 245 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 266 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 287 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 308 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 329 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 350 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 371 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 392 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 413 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 434 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 455 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 490 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 511 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 532 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 553 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 574 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 595 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 616 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 637 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 658 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 679 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 700 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 721 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 742 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 763 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 784 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 805 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 826 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 861 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 882 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 903 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 924 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 945 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 966 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 987 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1008 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1029 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1050 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1071 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1092 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 1113 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 21 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 42 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 63 For 10 Set T1 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 84 For 10 ! Program the CTFE 2X Clock which is Time Line 2 ! ------------======================--------------------- Assign FP_2X_Clk_OS = 5 ! FIRST Pulse 2X Clock Offset Assign SP_2X_Clk_OS = 15 ! SECOND Pulse 2X Clock Offset ! First all of the FIRST 2X Pulses Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T2 Up FP_2X_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Now all of the SECOND 2X Pulses Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T2 Up SP_2X_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Program the CTFE X Clock which is Time Line 3 ! ------------============--------------------- Assign FP_X_Clk_OS = 11 ! CTFE X Clock Offset First Pulse Assign SP_X_Clk_OS = 21 ! CTFE X Clock Offset Second Pulse ! First all the FIRST X Clock pulses Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T3 Up FP_X_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Now all the SECOND X Clock pulses Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T3 Up SP_X_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Program the CTFE Energy LUM MSB Adrs Line which is Time Line 4 ! ------------=============================---------------------- Assign Eng_LUM_MSB_OS = 8 ! Energy LUM MSB Address Offset Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 119 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 140 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 161 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 182 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 203 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 224 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 245 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 266 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 287 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 308 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 329 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 350 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 371 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 392 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 413 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 434 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 455 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 490 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 511 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 532 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 553 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 574 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 595 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 616 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 637 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 658 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 679 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 700 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 721 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 742 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 763 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 784 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 805 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 826 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 861 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 882 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 903 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 924 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 945 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 966 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 987 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1008 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1029 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1050 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1071 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1092 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 1113 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 21 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 42 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 63 For 10 Set T4 Up Eng_LUM_MSB_OS + CTFE_OS + TR1_OS + 84 For 10 ! Program the CTFE Momentum LUM MSB Adrs Line which is Time Line 5 ! ------------===============================---------------------- Assign Mom_LUM_MSB_OS = 11 ! Momentum LUM MSB Address Offset Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 119 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 140 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 161 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 182 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 203 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 224 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 245 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 266 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 287 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 308 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 329 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 350 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 371 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 392 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 413 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 434 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 455 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 490 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 511 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 532 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 553 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 574 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 595 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 616 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 637 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 658 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 679 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 700 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 721 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 742 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 763 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 784 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 805 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 826 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 861 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 882 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 903 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 924 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 945 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 966 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 987 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1008 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1029 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1050 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1071 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1092 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 1113 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 21 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 42 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 63 For 10 Set T5 Up Mom_LUM_MSB_OS + CTFE_OS + TR1_OS + 84 For 10 ! Program the CHTCR Input Clock which is Time Line 6 ! ------------=================--------------------- Assign CHTCR_Clk_OS = 17 ! CHTCR Input Clock Offset ! Should pull out CTFE_OS ?? Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 119 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 140 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 161 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 182 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 203 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 224 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 245 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 266 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 287 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 308 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 329 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 350 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 371 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 392 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 413 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 434 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 455 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 490 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 511 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 532 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 553 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 574 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 595 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 616 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 637 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 658 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 679 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 700 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 721 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 742 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 763 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 784 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 805 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 826 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 861 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 882 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 903 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 924 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 945 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 966 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 987 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1008 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1029 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1050 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1071 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1092 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 1113 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 21 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 42 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 63 For 3 Set T6 Up CHTCR_Clk_OS + CTFE_OS + TR1_OS + 84 For 3 ! Program the Tier 1 Energy Adder Tree CAT2 Clock which is Time Line 7 ! ------------===================================--------------------- Assign TR1_Eng_CAT2_Clk_OS = 14 ! Tier 1 Energy Adder Tree ! CAT2 Clock Offset ! Should pull out CTFE_OS ?? Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 119 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 140 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 161 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 182 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 203 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 224 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 245 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 266 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 287 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 308 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 329 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 350 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 371 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 392 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 413 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 434 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 455 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 490 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 511 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 532 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 553 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 574 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 595 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 616 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 637 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 658 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 679 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 700 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 721 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 742 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 763 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 784 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 805 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 826 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 861 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 882 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 903 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 924 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 945 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 966 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 987 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1008 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1029 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1050 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1071 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1092 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1113 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 21 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 42 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 63 For 2 Set T7 Up TR1_Eng_CAT2_Clk_OS + CTFE_OS + TR1_OS + 84 For 2 ! Program the Tier 1 Momentum Adder Tree CAT2 Clock which is Time Line 8 ! ------------=====================================--------------------- Assign TR1_Mom_CAT2_Clk_OS = 10 ! Tier 1 Momentum Adder Tree ! CAT2 Clock Offset ! Should pull out CTFE_OS ?? Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 119 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 140 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 161 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 182 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 203 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 224 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 245 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 266 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 287 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 308 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 329 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 350 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 371 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 392 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 413 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 434 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 455 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 490 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 511 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 532 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 553 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 574 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 595 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 616 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 637 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 658 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 679 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 700 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 721 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 742 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 763 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 784 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 805 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 826 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 861 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 882 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 903 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 924 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 945 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 966 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 987 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1008 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1029 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1050 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1071 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1092 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 1113 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 21 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 42 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 63 For 2 Set T8 Up TR1_Mom_CAT2_Clk_OS + CTFE_OS + TR1_OS + 84 For 2 !=====+++++++====++++====++++===+++====++===++====+===++==++===++===+=== ! Programming the Sub-System Strobe and Gap Signals ! ------------------------------------------------- ! Note that the Sub-System Gap signal must be set up to make its ! transitions at the same time as the And-Or Terms that are generated ! by the L1 Cal Trigger make their transitions. The Sub-System ! Strobe must be setup so that its positive edge occures when the ! And-Or Terms and the Gap signal are all stable. ! Now program the Subsystem Strobe which is Time Line 9 ! ----------------================---------------------- ! This is the 132 nsec clock that is used to send the L1 Cal Trig ! And-Or Terms to the Trigger Framework Term Receiver Module. Assign Subsys_Stb_OS = +23 Set T9 Up Subsys_Stb_OS + 0 For 3 Set T9 Up Subsys_Stb_OS + 7 For 3 Set T9 Up Subsys_Stb_OS + 14 For 3 Set T9 Up Subsys_Stb_OS + 21 For 3 Set T9 Up Subsys_Stb_OS + 28 For 3 Set T9 Up Subsys_Stb_OS + 35 For 3 Set T9 Up Subsys_Stb_OS + 42 For 3 Set T9 Up Subsys_Stb_OS + 49 For 3 Set T9 Up Subsys_Stb_OS + 56 For 3 Set T9 Up Subsys_Stb_OS + 63 For 3 Set T9 Up Subsys_Stb_OS + 70 For 3 Set T9 Up Subsys_Stb_OS + 77 For 3 Set T9 Up Subsys_Stb_OS + 84 For 3 Set T9 Up Subsys_Stb_OS + 91 For 3 Set T9 Up Subsys_Stb_OS + 98 For 3 Set T9 Up Subsys_Stb_OS + 105 For 3 Set T9 Up Subsys_Stb_OS + 112 For 3 Set T9 Up Subsys_Stb_OS + 119 For 3 Set T9 Up Subsys_Stb_OS + 126 For 3 Set T9 Up Subsys_Stb_OS + 133 For 3 Set T9 Up Subsys_Stb_OS + 140 For 3 Set T9 Up Subsys_Stb_OS + 147 For 3 Set T9 Up Subsys_Stb_OS + 154 For 3 Set T9 Up Subsys_Stb_OS + 161 For 3 Set T9 Up Subsys_Stb_OS + 168 For 3 Set T9 Up Subsys_Stb_OS + 175 For 3 Set T9 Up Subsys_Stb_OS + 182 For 3 Set T9 Up Subsys_Stb_OS + 189 For 3 Set T9 Up Subsys_Stb_OS + 196 For 3 Set T9 Up Subsys_Stb_OS + 203 For 3 Set T9 Up Subsys_Stb_OS + 210 For 3 Set T9 Up Subsys_Stb_OS + 217 For 3 Set T9 Up Subsys_Stb_OS + 224 For 3 Set T9 Up Subsys_Stb_OS + 231 For 3 Set T9 Up Subsys_Stb_OS + 238 For 3 Set T9 Up Subsys_Stb_OS + 245 For 3 Set T9 Up Subsys_Stb_OS + 252 For 3 Set T9 Up Subsys_Stb_OS + 259 For 3 Set T9 Up Subsys_Stb_OS + 266 For 3 Set T9 Up Subsys_Stb_OS + 273 For 3 Set T9 Up Subsys_Stb_OS + 280 For 3 Set T9 Up Subsys_Stb_OS + 287 For 3 Set T9 Up Subsys_Stb_OS + 294 For 3 Set T9 Up Subsys_Stb_OS + 301 For 3 Set T9 Up Subsys_Stb_OS + 308 For 3 Set T9 Up Subsys_Stb_OS + 315 For 3 Set T9 Up Subsys_Stb_OS + 322 For 3 Set T9 Up Subsys_Stb_OS + 329 For 3 Set T9 Up Subsys_Stb_OS + 336 For 3 Set T9 Up Subsys_Stb_OS + 343 For 3 Set T9 Up Subsys_Stb_OS + 350 For 3 Set T9 Up Subsys_Stb_OS + 357 For 3 Set T9 Up Subsys_Stb_OS + 364 For 3 Set T9 Up Subsys_Stb_OS + 371 For 3 Set T9 Up Subsys_Stb_OS + 378 For 3 Set T9 Up Subsys_Stb_OS + 385 For 3 Set T9 Up Subsys_Stb_OS + 392 For 3 Set T9 Up Subsys_Stb_OS + 399 For 3 Set T9 Up Subsys_Stb_OS + 406 For 3 Set T9 Up Subsys_Stb_OS + 413 For 3 Set T9 Up Subsys_Stb_OS + 420 For 3 Set T9 Up Subsys_Stb_OS + 427 For 3 Set T9 Up Subsys_Stb_OS + 434 For 3 Set T9 Up Subsys_Stb_OS + 441 For 3 Set T9 Up Subsys_Stb_OS + 448 For 3 Set T9 Up Subsys_Stb_OS + 455 For 3 Set T9 Up Subsys_Stb_OS + 462 For 3 Set T9 Up Subsys_Stb_OS + 469 For 3 Set T9 Up Subsys_Stb_OS + 476 For 3 Set T9 Up Subsys_Stb_OS + 483 For 3 Set T9 Up Subsys_Stb_OS + 490 For 3 Set T9 Up Subsys_Stb_OS + 497 For 3 Set T9 Up Subsys_Stb_OS + 504 For 3 Set T9 Up Subsys_Stb_OS + 511 For 3 Set T9 Up Subsys_Stb_OS + 518 For 3 Set T9 Up Subsys_Stb_OS + 525 For 3 Set T9 Up Subsys_Stb_OS + 532 For 3 Set T9 Up Subsys_Stb_OS + 539 For 3 Set T9 Up Subsys_Stb_OS + 546 For 3 Set T9 Up Subsys_Stb_OS + 553 For 3 Set T9 Up Subsys_Stb_OS + 560 For 3 Set T9 Up Subsys_Stb_OS + 567 For 3 Set T9 Up Subsys_Stb_OS + 574 For 3 Set T9 Up Subsys_Stb_OS + 581 For 3 Set T9 Up Subsys_Stb_OS + 588 For 3 Set T9 Up Subsys_Stb_OS + 595 For 3 Set T9 Up Subsys_Stb_OS + 602 For 3 Set T9 Up Subsys_Stb_OS + 609 For 3 Set T9 Up Subsys_Stb_OS + 616 For 3 Set T9 Up Subsys_Stb_OS + 623 For 3 Set T9 Up Subsys_Stb_OS + 630 For 3 Set T9 Up Subsys_Stb_OS + 637 For 3 Set T9 Up Subsys_Stb_OS + 644 For 3 Set T9 Up Subsys_Stb_OS + 651 For 3 Set T9 Up Subsys_Stb_OS + 658 For 3 Set T9 Up Subsys_Stb_OS + 665 For 3 Set T9 Up Subsys_Stb_OS + 672 For 3 Set T9 Up Subsys_Stb_OS + 679 For 3 Set T9 Up Subsys_Stb_OS + 686 For 3 Set T9 Up Subsys_Stb_OS + 693 For 3 Set T9 Up Subsys_Stb_OS + 700 For 3 Set T9 Up Subsys_Stb_OS + 707 For 3 Set T9 Up Subsys_Stb_OS + 714 For 3 Set T9 Up Subsys_Stb_OS + 721 For 3 Set T9 Up Subsys_Stb_OS + 728 For 3 Set T9 Up Subsys_Stb_OS + 735 For 3 Set T9 Up Subsys_Stb_OS + 742 For 3 Set T9 Up Subsys_Stb_OS + 749 For 3 Set T9 Up Subsys_Stb_OS + 756 For 3 Set T9 Up Subsys_Stb_OS + 763 For 3 Set T9 Up Subsys_Stb_OS + 770 For 3 Set T9 Up Subsys_Stb_OS + 777 For 3 Set T9 Up Subsys_Stb_OS + 784 For 3 Set T9 Up Subsys_Stb_OS + 791 For 3 Set T9 Up Subsys_Stb_OS + 798 For 3 Set T9 Up Subsys_Stb_OS + 805 For 3 Set T9 Up Subsys_Stb_OS + 812 For 3 Set T9 Up Subsys_Stb_OS + 819 For 3 Set T9 Up Subsys_Stb_OS + 826 For 3 Set T9 Up Subsys_Stb_OS + 833 For 3 Set T9 Up Subsys_Stb_OS + 840 For 3 Set T9 Up Subsys_Stb_OS + 847 For 3 Set T9 Up Subsys_Stb_OS + 854 For 3 Set T9 Up Subsys_Stb_OS + 861 For 3 Set T9 Up Subsys_Stb_OS + 868 For 3 Set T9 Up Subsys_Stb_OS + 875 For 3 Set T9 Up Subsys_Stb_OS + 882 For 3 Set T9 Up Subsys_Stb_OS + 889 For 3 Set T9 Up Subsys_Stb_OS + 896 For 3 Set T9 Up Subsys_Stb_OS + 903 For 3 Set T9 Up Subsys_Stb_OS + 910 For 3 Set T9 Up Subsys_Stb_OS + 917 For 3 Set T9 Up Subsys_Stb_OS + 924 For 3 Set T9 Up Subsys_Stb_OS + 931 For 3 Set T9 Up Subsys_Stb_OS + 938 For 3 Set T9 Up Subsys_Stb_OS + 945 For 3 Set T9 Up Subsys_Stb_OS + 952 For 3 Set T9 Up Subsys_Stb_OS + 959 For 3 Set T9 Up Subsys_Stb_OS + 966 For 3 Set T9 Up Subsys_Stb_OS + 973 For 3 Set T9 Up Subsys_Stb_OS + 980 For 3 Set T9 Up Subsys_Stb_OS + 987 For 3 Set T9 Up Subsys_Stb_OS + 994 For 3 Set T9 Up Subsys_Stb_OS + 1001 For 3 Set T9 Up Subsys_Stb_OS + 1008 For 3 Set T9 Up Subsys_Stb_OS + 1015 For 3 Set T9 Up Subsys_Stb_OS + 1022 For 3 Set T9 Up Subsys_Stb_OS + 1029 For 3 Set T9 Up Subsys_Stb_OS + 1036 For 3 Set T9 Up Subsys_Stb_OS + 1043 For 3 Set T9 Up Subsys_Stb_OS + 1050 For 3 Set T9 Up Subsys_Stb_OS + 1057 For 3 Set T9 Up Subsys_Stb_OS + 1064 For 3 Set T9 Up Subsys_Stb_OS + 1071 For 3 Set T9 Up Subsys_Stb_OS + 1078 For 3 Set T9 Up Subsys_Stb_OS + 1085 For 3 Set T9 Up Subsys_Stb_OS + 1092 For 3 Set T9 Up Subsys_Stb_OS + 1099 For 3 Set T9 Up Subsys_Stb_OS + 1106 For 3 ! Now program the Subsystem GAP Marker which is Time Line 10 ! -----------------====================----------------------- ! This is the once per turn Gap signal that is used to send the ! L1 Cal Trig And-Or Terms to the Trigger Framework Term Receiver Module. Assign Subsys_GAP_OS = +81 Set T10 Up Subsys_GAP_OS For 119 ! Program the Time Lines that Control Tier 2 ! --------------------------------------====== Assign TR2_OS = +2 ! The offset for all Tier 2 Time Lines ! Program the Tier 2 Counter Tree CAT2 Clock which is Time Line 11 ! ------------==============================---------------------- ! This TL is also the Tier 3 Momentum Tree CAT3 Clock Assign TR2_Counter_Tree_CAT2_Clk_OS = 34 ! Tier 2 Counter Tree ! CAT2 Clock Offset Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 119 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 140 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 161 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 182 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 203 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 224 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 245 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 266 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 287 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 308 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 329 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 350 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 371 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 392 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 413 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 434 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 455 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 490 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 511 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 532 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 553 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 574 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 595 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 616 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 637 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 658 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 679 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 700 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 721 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 742 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 763 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 784 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 805 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 826 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 861 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 882 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 903 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 924 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 945 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 966 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 987 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1008 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1029 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1050 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1071 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1092 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 1113 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 21 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 42 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 63 For 2 Set T11 Up TR2_Counter_Tree_CAT2_Clk_OS + TR2_OS + 84 For 2 ! Now program the 2nd Copy of Subsystem Strobe which is Time Line 12 ! -----------------------------================----------------------- ! This is a second copy of the SubSystem Strobe signal. The first ! copy of this signal is on Time Line 9. ! This is the 132 nsec clock that is used to send the L1 Cal Trig ! And-Or Terms to the Trigger Framework Term Receiver Module. Set T12 Up Subsys_Stb_OS + 0 For 3 Set T12 Up Subsys_Stb_OS + 7 For 3 Set T12 Up Subsys_Stb_OS + 14 For 3 Set T12 Up Subsys_Stb_OS + 21 For 3 Set T12 Up Subsys_Stb_OS + 28 For 3 Set T12 Up Subsys_Stb_OS + 35 For 3 Set T12 Up Subsys_Stb_OS + 42 For 3 Set T12 Up Subsys_Stb_OS + 49 For 3 Set T12 Up Subsys_Stb_OS + 56 For 3 Set T12 Up Subsys_Stb_OS + 63 For 3 Set T12 Up Subsys_Stb_OS + 70 For 3 Set T12 Up Subsys_Stb_OS + 77 For 3 Set T12 Up Subsys_Stb_OS + 84 For 3 Set T12 Up Subsys_Stb_OS + 91 For 3 Set T12 Up Subsys_Stb_OS + 98 For 3 Set T12 Up Subsys_Stb_OS + 105 For 3 Set T12 Up Subsys_Stb_OS + 112 For 3 Set T12 Up Subsys_Stb_OS + 119 For 3 Set T12 Up Subsys_Stb_OS + 126 For 3 Set T12 Up Subsys_Stb_OS + 133 For 3 Set T12 Up Subsys_Stb_OS + 140 For 3 Set T12 Up Subsys_Stb_OS + 147 For 3 Set T12 Up Subsys_Stb_OS + 154 For 3 Set T12 Up Subsys_Stb_OS + 161 For 3 Set T12 Up Subsys_Stb_OS + 168 For 3 Set T12 Up Subsys_Stb_OS + 175 For 3 Set T12 Up Subsys_Stb_OS + 182 For 3 Set T12 Up Subsys_Stb_OS + 189 For 3 Set T12 Up Subsys_Stb_OS + 196 For 3 Set T12 Up Subsys_Stb_OS + 203 For 3 Set T12 Up Subsys_Stb_OS + 210 For 3 Set T12 Up Subsys_Stb_OS + 217 For 3 Set T12 Up Subsys_Stb_OS + 224 For 3 Set T12 Up Subsys_Stb_OS + 231 For 3 Set T12 Up Subsys_Stb_OS + 238 For 3 Set T12 Up Subsys_Stb_OS + 245 For 3 Set T12 Up Subsys_Stb_OS + 252 For 3 Set T12 Up Subsys_Stb_OS + 259 For 3 Set T12 Up Subsys_Stb_OS + 266 For 3 Set T12 Up Subsys_Stb_OS + 273 For 3 Set T12 Up Subsys_Stb_OS + 280 For 3 Set T12 Up Subsys_Stb_OS + 287 For 3 Set T12 Up Subsys_Stb_OS + 294 For 3 Set T12 Up Subsys_Stb_OS + 301 For 3 Set T12 Up Subsys_Stb_OS + 308 For 3 Set T12 Up Subsys_Stb_OS + 315 For 3 Set T12 Up Subsys_Stb_OS + 322 For 3 Set T12 Up Subsys_Stb_OS + 329 For 3 Set T12 Up Subsys_Stb_OS + 336 For 3 Set T12 Up Subsys_Stb_OS + 343 For 3 Set T12 Up Subsys_Stb_OS + 350 For 3 Set T12 Up Subsys_Stb_OS + 357 For 3 Set T12 Up Subsys_Stb_OS + 364 For 3 Set T12 Up Subsys_Stb_OS + 371 For 3 Set T12 Up Subsys_Stb_OS + 378 For 3 Set T12 Up Subsys_Stb_OS + 385 For 3 Set T12 Up Subsys_Stb_OS + 392 For 3 Set T12 Up Subsys_Stb_OS + 399 For 3 Set T12 Up Subsys_Stb_OS + 406 For 3 Set T12 Up Subsys_Stb_OS + 413 For 3 Set T12 Up Subsys_Stb_OS + 420 For 3 Set T12 Up Subsys_Stb_OS + 427 For 3 Set T12 Up Subsys_Stb_OS + 434 For 3 Set T12 Up Subsys_Stb_OS + 441 For 3 Set T12 Up Subsys_Stb_OS + 448 For 3 Set T12 Up Subsys_Stb_OS + 455 For 3 Set T12 Up Subsys_Stb_OS + 462 For 3 Set T12 Up Subsys_Stb_OS + 469 For 3 Set T12 Up Subsys_Stb_OS + 476 For 3 Set T12 Up Subsys_Stb_OS + 483 For 3 Set T12 Up Subsys_Stb_OS + 490 For 3 Set T12 Up Subsys_Stb_OS + 497 For 3 Set T12 Up Subsys_Stb_OS + 504 For 3 Set T12 Up Subsys_Stb_OS + 511 For 3 Set T12 Up Subsys_Stb_OS + 518 For 3 Set T12 Up Subsys_Stb_OS + 525 For 3 Set T12 Up Subsys_Stb_OS + 532 For 3 Set T12 Up Subsys_Stb_OS + 539 For 3 Set T12 Up Subsys_Stb_OS + 546 For 3 Set T12 Up Subsys_Stb_OS + 553 For 3 Set T12 Up Subsys_Stb_OS + 560 For 3 Set T12 Up Subsys_Stb_OS + 567 For 3 Set T12 Up Subsys_Stb_OS + 574 For 3 Set T12 Up Subsys_Stb_OS + 581 For 3 Set T12 Up Subsys_Stb_OS + 588 For 3 Set T12 Up Subsys_Stb_OS + 595 For 3 Set T12 Up Subsys_Stb_OS + 602 For 3 Set T12 Up Subsys_Stb_OS + 609 For 3 Set T12 Up Subsys_Stb_OS + 616 For 3 Set T12 Up Subsys_Stb_OS + 623 For 3 Set T12 Up Subsys_Stb_OS + 630 For 3 Set T12 Up Subsys_Stb_OS + 637 For 3 Set T12 Up Subsys_Stb_OS + 644 For 3 Set T12 Up Subsys_Stb_OS + 651 For 3 Set T12 Up Subsys_Stb_OS + 658 For 3 Set T12 Up Subsys_Stb_OS + 665 For 3 Set T12 Up Subsys_Stb_OS + 672 For 3 Set T12 Up Subsys_Stb_OS + 679 For 3 Set T12 Up Subsys_Stb_OS + 686 For 3 Set T12 Up Subsys_Stb_OS + 693 For 3 Set T12 Up Subsys_Stb_OS + 700 For 3 Set T12 Up Subsys_Stb_OS + 707 For 3 Set T12 Up Subsys_Stb_OS + 714 For 3 Set T12 Up Subsys_Stb_OS + 721 For 3 Set T12 Up Subsys_Stb_OS + 728 For 3 Set T12 Up Subsys_Stb_OS + 735 For 3 Set T12 Up Subsys_Stb_OS + 742 For 3 Set T12 Up Subsys_Stb_OS + 749 For 3 Set T12 Up Subsys_Stb_OS + 756 For 3 Set T12 Up Subsys_Stb_OS + 763 For 3 Set T12 Up Subsys_Stb_OS + 770 For 3 Set T12 Up Subsys_Stb_OS + 777 For 3 Set T12 Up Subsys_Stb_OS + 784 For 3 Set T12 Up Subsys_Stb_OS + 791 For 3 Set T12 Up Subsys_Stb_OS + 798 For 3 Set T12 Up Subsys_Stb_OS + 805 For 3 Set T12 Up Subsys_Stb_OS + 812 For 3 Set T12 Up Subsys_Stb_OS + 819 For 3 Set T12 Up Subsys_Stb_OS + 826 For 3 Set T12 Up Subsys_Stb_OS + 833 For 3 Set T12 Up Subsys_Stb_OS + 840 For 3 Set T12 Up Subsys_Stb_OS + 847 For 3 Set T12 Up Subsys_Stb_OS + 854 For 3 Set T12 Up Subsys_Stb_OS + 861 For 3 Set T12 Up Subsys_Stb_OS + 868 For 3 Set T12 Up Subsys_Stb_OS + 875 For 3 Set T12 Up Subsys_Stb_OS + 882 For 3 Set T12 Up Subsys_Stb_OS + 889 For 3 Set T12 Up Subsys_Stb_OS + 896 For 3 Set T12 Up Subsys_Stb_OS + 903 For 3 Set T12 Up Subsys_Stb_OS + 910 For 3 Set T12 Up Subsys_Stb_OS + 917 For 3 Set T12 Up Subsys_Stb_OS + 924 For 3 Set T12 Up Subsys_Stb_OS + 931 For 3 Set T12 Up Subsys_Stb_OS + 938 For 3 Set T12 Up Subsys_Stb_OS + 945 For 3 Set T12 Up Subsys_Stb_OS + 952 For 3 Set T12 Up Subsys_Stb_OS + 959 For 3 Set T12 Up Subsys_Stb_OS + 966 For 3 Set T12 Up Subsys_Stb_OS + 973 For 3 Set T12 Up Subsys_Stb_OS + 980 For 3 Set T12 Up Subsys_Stb_OS + 987 For 3 Set T12 Up Subsys_Stb_OS + 994 For 3 Set T12 Up Subsys_Stb_OS + 1001 For 3 Set T12 Up Subsys_Stb_OS + 1008 For 3 Set T12 Up Subsys_Stb_OS + 1015 For 3 Set T12 Up Subsys_Stb_OS + 1022 For 3 Set T12 Up Subsys_Stb_OS + 1029 For 3 Set T12 Up Subsys_Stb_OS + 1036 For 3 Set T12 Up Subsys_Stb_OS + 1043 For 3 Set T12 Up Subsys_Stb_OS + 1050 For 3 Set T12 Up Subsys_Stb_OS + 1057 For 3 Set T12 Up Subsys_Stb_OS + 1064 For 3 Set T12 Up Subsys_Stb_OS + 1071 For 3 Set T12 Up Subsys_Stb_OS + 1078 For 3 Set T12 Up Subsys_Stb_OS + 1085 For 3 Set T12 Up Subsys_Stb_OS + 1092 For 3 Set T12 Up Subsys_Stb_OS + 1099 For 3 Set T12 Up Subsys_Stb_OS + 1106 For 3 ! Now program the 2nd copy of Subsystem GAP Marker which is Time Line 13 ! -----------------------------====================----------------------- ! This is the second copy of the SybSystem GAP signal. The first ! copy of this signal is on Time Line 10. ! This is the once per turn Gap signal that is used to send the ! L1 Cal Trig And-Or Terms to the Trigger Framework Term Receiver Module. Set T13 Up Subsys_GAP_OS For 119 ! Program the Time Lines that Control Tier 3 ! --------------------------------------====== Assign TR3_OS = +2 ! The offset for all Tier 3 Time Lines ! Program the Tier 3 Counter Tree CAT2 Clock which is Time Line 14 ! ------------==============================---------------------- ! This TL is also the Tier 4 Momentum Tree FMLN Clock. Assign TR3_Counter_Tree_CAT2_Clk_OS = 48 ! Tier 3 Counter Tree ! CAT2 Clock Offset Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 119 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 140 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 161 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 182 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 203 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 224 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 245 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 266 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 287 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 308 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 329 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 350 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 371 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 392 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 413 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 434 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 455 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 490 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 511 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 532 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 553 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 574 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 595 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 616 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 637 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 658 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 679 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 700 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 721 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 742 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 763 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 784 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 805 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 826 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 861 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 882 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 903 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 924 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 945 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 966 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 987 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1008 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1029 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1050 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1071 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1092 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 1113 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 21 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 42 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 63 For 2 Set T14 Up TR3_Counter_Tree_CAT2_Clk_OS + TR3_OS + 84 For 2 ! Program the Tier 2 Momentum Tree CAT2 Clock which is Time Line 15 ! ------------===============================---------------------- Assign TR2_Momentum_Tree_CAT2_Clk_OS = 19 ! Tier 2 Momentum Tree ! CAT2 Clock Offset Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 119 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 140 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 161 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 182 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 203 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 224 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 245 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 266 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 287 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 308 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 329 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 350 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 371 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 392 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 413 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 434 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 455 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 490 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 511 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 532 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 553 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 574 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 595 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 616 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 637 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 658 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 679 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 700 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 721 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 742 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 763 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 784 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 805 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 826 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 861 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 882 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 903 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 924 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 945 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 966 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 987 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1008 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1029 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1050 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1071 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1092 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 1113 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 21 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 42 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 63 For 2 Set T15 Up TR2_Momentum_Tree_CAT2_Clk_OS + TR2_OS + 84 For 2 ! Setup Time Lines 16 and 17 for generation of Quad Terms ! ------------------------------------------------------- ! Program the Quad Term CT_FOM Input Clock which is Time Line 16 ! ------------============================----------------------- Assign CT_FOM_Input_Clk_OS = 34 ! Quad Term CT_FOM ! Input_Clock Offset Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 119 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 140 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 161 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 182 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 203 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 224 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 245 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 266 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 287 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 308 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 329 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 350 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 371 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 392 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 413 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 434 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 455 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 490 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 511 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 532 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 553 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 574 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 595 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 616 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 637 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 658 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 679 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 700 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 721 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 742 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 763 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 784 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 805 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 826 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 861 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 882 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 903 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 924 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 945 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 966 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 987 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1008 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1029 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1050 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1071 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1092 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 1113 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 21 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 42 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 63 For 2 Set T16 Up CT_FOM_Input_Clk_OS + CTFE_OS + TR1_OS + 84 For 2 ! Program the Quad Term CT_FOM Output Clock which is Time Line 17 ! ------------=============================----------------------- Assign CT_FOM_Output_Clk_OS = 48 ! Quad Term CT_FOM ! Output_Clock Offset Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 119 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 140 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 161 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 182 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 203 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 224 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 245 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 266 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 287 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 308 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 329 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 350 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 371 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 392 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 413 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 434 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 455 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 490 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 511 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 532 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 553 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 574 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 595 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 616 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 637 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 658 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 679 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 700 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 721 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 742 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 763 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 784 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 805 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 826 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 861 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 882 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 903 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 924 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 945 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 966 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 987 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1008 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1029 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1050 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1071 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1092 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 1113 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 21 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 42 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 63 For 2 Set T17 Up CT_FOM_Output_Clk_OS + TR3_OS + 84 For 2 ! Setup the currently not used Time Lines 18 and 19 ! ------------------------------------------------- Set T18 Up 1 For 1113 Set T19 Up 1 For 1113 ! Program the ERPB Input Clock signal on Time Line #20 ! ------------=================------------------------- Assign FP_ERPB_In_OS = 24 ! FIRST Pulse ERPB Input Clock Assign SP_ERPB_In_OS = 34 ! SECOND Pulse ERPB Input Clock ! First all of the FIRST Pulses of the ERPB Input Clock Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 119 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 140 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 161 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 182 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 203 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 224 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 245 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 266 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 287 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 308 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 329 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 350 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 371 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 392 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 413 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 434 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 455 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 490 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 511 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 532 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 553 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 574 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 595 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 616 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 637 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 658 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 679 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 700 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 721 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 742 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 763 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 784 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 805 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 826 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 861 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 882 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 903 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 924 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 945 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 966 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 987 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1008 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1029 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1050 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1071 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1092 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 1113 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 21 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 42 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 63 For 4 Set T20 Up FP_ERPB_In_OS + CTFE_OS + TR1_OS + 84 For 4 ! Now all of the SECOND Pulses of the ERPB Input Clock Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 119 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 140 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 161 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 182 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 203 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 224 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 245 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 266 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 287 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 308 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 329 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 350 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 371 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 392 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 413 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 434 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 455 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 490 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 511 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 532 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 553 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 574 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 595 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 616 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 637 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 658 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 679 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 700 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 721 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 742 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 763 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 784 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 805 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 826 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 861 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 882 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 903 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 924 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 945 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 966 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 987 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1008 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1029 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1050 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1071 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1092 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 1113 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 21 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 42 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 63 For 4 Set T20 Up SP_ERPB_In_OS + CTFE_OS + TR1_OS + 84 For 4 ! Program the ERPB EM/Tot Select signal on Time Line #21 ! ------------===================------------------------- Assign EM_Tot_OS = +20 ! Setup the EM/Tot Select offset Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 119 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 140 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 161 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 182 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 203 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 224 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 245 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 266 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 287 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 308 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 329 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 350 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 371 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 392 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 413 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 434 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 455 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 490 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 511 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 532 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 553 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 574 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 595 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 616 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 637 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 658 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 679 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 700 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 721 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 742 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 763 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 784 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 805 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 826 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 861 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 882 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 903 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 924 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 945 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 966 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 987 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1008 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1029 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1050 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1071 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1092 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 1113 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 21 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 42 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 63 For 11 Set T21 Up EM_Tot_OS + CTFE_OS + TR1_OS + 84 For 11 ! Program the Marker that identifies the falling edge of the Latch-Shift ! that begins the processing of the Trigger Pickoff signal from the first ! real BX of a turn, i.e. the BX that is labeled Current Tick #7. This ! identification marker is on Time Line 22. This signal is just a ! copy of that pulse of Latch-Shift. Set T22 Up Ltch_Shft_Clk_OS + CTFE_OS + TR1_OS + 140 For 10 ! Setup the BC_TRIG signal that is a Sequencer reference marker output. ! ----------------------------------------------------------------------- ! Setup the BC_Trig signal. This signal is available only on a front ! panel Lemo and can be setup to match when the BX's happen in the ! center of the D-Zero detector. ! ! We need the peak of the trigger pick off signal to occure typically ! 7 RF Buckets before the falling edge of Latch-Shift. This is the ! center of the range that that the ADC Clk falling edge can be set to. ! ! The real BX in the center of D-Zero happens typically 658 nsec ! before we see the peak of the signal in the L1 Cal Trig. This is ! 36 RF Buckets. So, set this Real BX marker a total of 43 RF Buckets ! before the falling edge of Latch-Shift. Assign BC_Trig_OS = -42 ! Initial alignment of the real BX in the ! center of D-Zero. This is in the ! correct position wrt CTFE signals. Set BCTRIG Up BC_Trig_OS + 140 For 1 Set BCTRIG Up BC_Trig_OS + 161 For 1 Set BCTRIG Up BC_Trig_OS + 182 For 1 Set BCTRIG Up BC_Trig_OS + 203 For 1 Set BCTRIG Up BC_Trig_OS + 224 For 1 Set BCTRIG Up BC_Trig_OS + 245 For 1 Set BCTRIG Up BC_Trig_OS + 266 For 1 Set BCTRIG Up BC_Trig_OS + 287 For 1 Set BCTRIG Up BC_Trig_OS + 308 For 1 Set BCTRIG Up BC_Trig_OS + 329 For 1 Set BCTRIG Up BC_Trig_OS + 350 For 1 Set BCTRIG Up BC_Trig_OS + 371 For 1 Set BCTRIG Up BC_Trig_OS + 511 For 1 Set BCTRIG Up BC_Trig_OS + 532 For 1 Set BCTRIG Up BC_Trig_OS + 553 For 1 Set BCTRIG Up BC_Trig_OS + 574 For 1 Set BCTRIG Up BC_Trig_OS + 595 For 1 Set BCTRIG Up BC_Trig_OS + 616 For 1 Set BCTRIG Up BC_Trig_OS + 637 For 1 Set BCTRIG Up BC_Trig_OS + 658 For 1 Set BCTRIG Up BC_Trig_OS + 679 For 1 Set BCTRIG Up BC_Trig_OS + 700 For 1 Set BCTRIG Up BC_Trig_OS + 721 For 1 Set BCTRIG Up BC_Trig_OS + 742 For 1 Set BCTRIG Up BC_Trig_OS + 882 For 1 Set BCTRIG Up BC_Trig_OS + 903 For 1 Set BCTRIG Up BC_Trig_OS + 924 For 1 Set BCTRIG Up BC_Trig_OS + 945 For 1 Set BCTRIG Up BC_Trig_OS + 966 For 1 Set BCTRIG Up BC_Trig_OS + 987 For 1 Set BCTRIG Up BC_Trig_OS + 1008 For 1 Set BCTRIG Up BC_Trig_OS + 1029 For 1 Set BCTRIG Up BC_Trig_OS + 1050 For 1 Set BCTRIG Up BC_Trig_OS + 1071 For 1 Set BCTRIG Up BC_Trig_OS + 1092 For 1 Set BCTRIG Up BC_Trig_OS + 1113 For 1 ! <><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><> ! ! Below here is some background reference information about how the ! Master Clock is setup for the 36x36 running. Everything below ! here is comment lines. ! Before starting the actual description of the Master Clock Time Lines ! the first part of this file is a description of the expected Run II ! running configuration. ! ! For the initial setup of Run II we will assume that we are running ! with 396 nsec crossings in 3 Super Bunches of 12 crossings each. ! Also let's number the RF Buckets as 1 through 1113. ! ! Now if we want to divide the 1113 RF Buckets into 3 even pieces we could ! arrange these as: ! ! RF Buckets 1 through 371 called the first 3rd ! RF Buckets 372 through 742 called the second 3rd ! RF Buckets 743 through 1113 called the third 3rd ! ! ! For 396 nsec crossings every 21 RF Buckets has particles in it. We could ! pick RF Bucket #1 as the beginning of a gap and then built everything ! symmetrically in three even pieces and it would result in the following ! ! ! RF Bucket Number of the Crossing ! Crossing ------------------------------------------- ! in the 1st 2nd 3rd ! Super Bunch Super Bunch Super Bunch Super Bunch ! ----------- ----------- ----------- ----------- ! 1st 140 511 882 ! 2nd 161 532 903 ! 3rd 182 553 924 ! 4th 203 574 945 ! ! 5th 224 595 966 ! 6th 245 616 987 ! 7th 266 637 1008 ! 8th 287 658 1029 ! ! 9th 308 679 1050 ! 10th 329 700 1071 ! 11th 350 721 1092 ! 12th 371 742 1113 ! ! ! For the set of RF Bucket numbers for the 36 crossings shown in the ! table above, the 3 gaps between the Super Bunches would take place ! between the following RF Bucket numbers. Note that the gap is not ! an integral number times 7 RF Buckets long. ! ! Gap Between This Gap Begins This Gap Ends Gap Lenght ! Super Bunches with RF Bucket with RF Bucket RF Buckets, nsec ! ------------- ---------------- -------------- ---------------- ! SB 1 to SB 2 372 510 139 2617.5 ! SB 2 to SB 3 743 881 139 2617.5 ! SB 3 to SB 1 1 139 139 2617.5 ! ! This table shows the Gap beginning at the RF Bucket immediately ! following the last beam crossing of the Super Bunch before the ! gap (see notes below concerning when the Gap Markers are asserted), ! and the gap ending at the RF Bucket immediately before the ! first beam crossing of the Super Bunch following the gap. ! ! We will place the Beginning of Turn and the Sync Gap in the Gap ! before Super Bunch #1. The Gap between SB #1 and SB #2 and the ! Gap between SB #2 and SB #3 will be called the Cosmic Gaps. ! ! !