Clock Notes ----------- Initial Version: 27-Oct-2000 Current Version: 1-Nov-2000 ========= PCC ========= Receives from the Tevatron Tevatron Sync - a once per turn signal, derived from the Tevatron Beam Sync Clock (TVBS) Tevatron RF - provides the reference frequency for the PCC to match its clock output frequency with that of the Tevatron Outputs PCLK - primary clock frequency MCLK - twice the PCLK frequency SYNC Out - once per turn, dreived from a 1113 countdown of PCLK Modes ----- The PCC has 4 modes, but only two (Freerun and Normal) are expected to be used regularly. In Freerun mode, both Tev RF and Tev SYNC are disabled and the PCC runs asynchronously to the Tevatron. The MCLK and PCLK signals will be fixed and stable (106.2084 and 53.110421 respectively), corresponding to a Tevatron energy of 210 GeV. The SYNC OUT signals is a 1113 countdown of PCLK and has a period of 20.95879 usec. The error monitors are disabled in this mode. In Normal mode, both Tev SYNC and Tev RF are enabled and the PCLK fequency during the time between the Tev SYNC pulses tries to track the Tev RF. In Sync Lock mode, only Tev SYNC is enabled and the frequency of PCLK during the time between the Tev SYNC pulses is fixed at the free running frequency of 53.104210 MHz. In Freq Lock mode, Tev SYNC is disabled and Tev RF is enabled. PCLK is phae locked to the Tev RF and runs without any phase adjustments on each revolution because PCLK tracks the Tev FR at all Tevatron energies. Error Monitors -------------- All errors are latched. The errors can be cleared via VME or a front panel push button switch. SYNC Missing asserted if Tev SYNC has a period of greater than 30 usec or is missing RF Missing asserted if the RF pulses are spaced by more than 60 ns or are missing altogether RF Lock when Tev RF is enabled, this error indicates that the output of the phase locked loop is not locked to the REF FREQ signal (derived from Tev RF) SYNC Timing asserted if the position of the SYNC OUT pulse relative to the Tev SYNC goes beyond some predetermined limits this error is not fatal and the PCC will automatically try to recover ========= Sequencer ========= Receives from the Tevatron BC_INP - beam crossing input from beam pickups Receives from the PCC SYNC_INP - a once per turn signal, based on Tev Sync PCLK - 53 MHz, based on Tev RF MCLK - 106 MHz, based on Tev RF Produces Internally SYNC_REF - a once per turn signal, compared with SYNC_INP BC_REF - programmed in buckets corresponding to expected bunch crossings, compared with BC_INP Outputs MCLK PCLK 12 Static Timing Lines 11 Dynamic Timing Lines various signals available on front panel for monitoring Modes ----- The sequencer has two modes: sync and freerun. In sync mode, the internally generated SYNC_REF is compared with the Tevatron SYNC pulse (SYNC_INP). If they are not in coincidence, the sequencer enters the hold state until the next SYNC_INP occurs. In the hold state the sequencer remains at the bucket in which SYNC_REF is programmed. When the next SYNC_INP occurs, the hold is removed, and the sequencer automatically tries to regain synchronization. The position of SYNC_REF can be programmed relative to the timing lines and hence can be used to establish the absolute timing of the outputs relative to SYNC_INP. In freerun mode, the sequencer continually cycles independent of the coincidence of SYNC_INP and SYNC_REF. Beam Crossing Reference ----------------------- The internally generated BC_REF is compared with the beam crossing input from beam pickups (BC_INP) to determine if the sequencer is properly synchronized to the Tevatron. Phase differences beween BC_INP and BC_REF exceeding a specified limit (user selectable from 2.5 to 10 ns) are detected and generate a BC_Phase error. A BC_Phase error will alert the operator but does not affect the operation of the sequencer. Organization of the Sequencer Memory ------------------------------------ There are 4 memory blocks. One memory block is used to supply the next address, one is used for the static timeline information, and two memory blocks are used for the dynamic timeline information. The address lines for these memory blocks may be either set via VME for programming or controlled by the output of the next address memory block. In the case of the static timelines and the next address memory, turning the clock on and off determines the source of the address (on = next address memory, off = VME). The two dynamic timeline memory blocks can be individually turned on and off; clock on/off does not affect these blocks. For both the dynamic timelines and the static timelines, the output must be enabled in order for the information from the memory blocks to be driven out on the timing lines. Dynamic Timeline Details ------------------------ The outputs of the two dynamic memory blocks are multiplexed; selecting group A/group B determines which memory block is currently supplying the timeline information to the sequencer outputs. Note that the appropriate memory block must be "on" in order for the data to appear at the sequencer output. Error Monitors -------------- The error status is displayed on front panel LEDs and is also available via VME. All errors are latched except for the Seq_Halted condition. The latched errors can be cleared by software or by pressing the front panel Clear Errors pushbutton. Seq_Halted the Sequencer is stopped, generated if SYNC_REF is missing for greater than 30 usec Sync_Missing SYNC_INP has been missing for greater than 30 usec in SYNC mode, this causes the Sequencer to halt in Freerun Mode, this error is disabled PCLK_Missing no PCLK pulse has occured for 30 ns or more MCLK_Missing no MCLK pulse has occured for 30 ns or more Clock_Parity compares the parity programmed in data memory to the hardware generaged parity signal Seq_Hold the Sequencer has lost its synchronization SYNC_INP did not arrive at the expected time (determined by SYNCH HOLD) relative to SYNC_REF BC_Phase detects phase differences between BC_REF and BC_INP the error must be present in two consecutive turns Reset/Power Up -------------- Upon a software reset and at power up: clock off group A off group B off group B selected by the mux errors cleared outputs disabled sync mode