!
!                     Master Clock Signals for the
!         Level 1 Trigger Framework and the Calorimeter Trigger
!
!                       Original Rev. 29-MAR-1999
!                        Current Rev. 23-AUG-2000
!
!
!
!  Before starting the actual description of the Master Clock Time Lines
!  the first part of this file is a description of the expected Run II
!  running configuration.
!
!  For the initial setup of Run II we will assume that we are running
!  with 396 nsec crossings in 3 Super Bunches of 12 crossings each.
!  Also let's number the RF Buckets as 1 through 1113.
!
!  Now if we want to divide the 1113 RF Buckets into 3 even pieces we could
!  arrange these as:
!
!      RF Buckets    1  through   371   called the first 3rd
!      RF Buckets  372  through   742   called the second 3rd
!      RF Buckets  743  through  1113   called the third 3rd
!
!
!  For 396 nsec crossings every 21 RF Buckets has particles in it.  We could
!  pick RF Bucket #1 as the beginning of a gap and then built everything
!  symmetrically in three even pieces and it would result in the following
!
!
!                            RF Bucket Number of the Crossing
!       Crossing        -------------------------------------------
!        in the             1st             2nd             3rd
!     Super Bunch       Super Bunch     Super Bunch     Super Bunch
!     -----------       -----------     -----------     -----------
!          1st              140             511             882
!          2nd              161             532             903
!          3rd              182             553             924
!          4th              203             574             945
!
!          5th              224             595             966
!          6th              245             616             987
!          7th              266             637            1008
!          8th              287             658            1029
!
!          9th              308             679            1050
!         10th              329             700            1071
!         11th              350             721            1092
!         12th              371             742            1113
!
!
!  For the set of RF Bucket numbers for the 36 crossings shown in the
!  table above, the 3 gaps between the Super Bunches would take place
!  between the following RF Bucket numbers.  Note that the gap is not
!  an integral number times 7 RF Buckets long.
!
!      Gap Between      This Gap Begins     This Gap Ends        Gap Lenght
!     Super Bunches      with RF Bucket     with RF Bucket    RF Buckets, nsec
!     -------------     ----------------    --------------    ----------------
!      SB 1 to SB 2          372                 510           139     2617.5
!      SB 2 to SB 3          743                 881           139     2617.5
!      SB 3 to SB 1            1                 139           139     2617.5
!
!  This table shows the Gap beginning at the RF Bucket immediately
!  following the last beam crossing of the Super Bunch before the
!  gap (see notes below concerning when the Gap Markers are asserted),
!  and the gap ending at the RF Bucket immediately before the
!  first beam crossing of the Super Bunch following the gap.
!
!  We will place the Beginning of Turn and the Sync Gap in the Gap
!  before Super Bunch #1.   The Gap between SB #1 and SB #2   and the
!  Gap between SB #2 and SB #3  will be called the Cosmic Gaps.
!
!
!
!
!
!  This file will be used to setup the following Master Clock Time Lines
!
!      Time Line         Function                      Used By
!      ---------     ------------------------     -----------------------
!         TL0        FW Tick Clock                Framework
!         TL1        TRM Clock                    Framework
!         TL2        Beginning of Turn Marker     FW & AO Net Input & SCL
!         TL3        Interaction Marker                AO Net Input & SCL
!         TL4        Cosmic Gap Marker                 AO Net Input & SCL
!         TL5        Sync Gap Marker              FW & AO Net Input & SCL
!         TL6        Spare Marker                      AO Net Input & SCL
!         TL7        FW Helper Function Clock     Framework
!
!         TL8        SCL Tick Clock               SCL
!         TL9        Calo Xing Clock              Calorimeter
!        TL10        Calo Base Sample             Calorimeter
!        TL11        Calo Peak Sample             Calorimeter
!        TL12        Calo Transfer                Calorimeter
!        TL13          ----
!        TL14        Subsystem Strobe		  Framework
!        TL15        Subsystem Gap		  Framework


!
!   Use of OFFSETs in the Definition of the Time Lines
!   -------=======------------------------------------

!  In general three different offsets will be used in the definition
!  of a Time Line.

!    The Global Offset is included in the definition of ALL Time Lines.  It
!    allows us to rotate the entire pattern with respect to the Accelerator.

!    Next each system (e.g. FW SCL CAL) has a system offset that is included
!    in just the Time Lines of that system.  This allows us to easily move
!    one system with respect to the rest.  If a signal is used by more than
!    one system then it is assigned the system offset of its principal
!    consumer.

!    Finally each signal in a given system will typically include an offset
!    for just that signal.  This signal specific offset typically will not
!    include the fixed known understandable timing offset of that signal
!    with respect to the other signals in its system.  The fixed known part
!    is typically included as an integer appearing in the definition of the
!    Time Line and described in the accompanying text.


!  So first let's assign the Global Offset value for ALL Master Clock Signals.

Assign  Glb_OS =  +1   !  Global Offset to be used by all signals



!  Now Program the Trigger Framework Time Lines
!  ----------------=================-----------

!  Note that many of these lines are used by both the FW and the SCL.

!  Recall that all Framework Timing Signals are delayed by 2 periods of
!  the 53 MHz clock in the BSF FPGA.  To get from the Master Clock to the
!  Trigger Framework the timing signals travel through about 30 feet, i.e.
!  18 sections of twist and flat cable.  This is about 50 nsec.  Therefore
!  the Carmen Master Clock signals to the Framework must run about 88 nsec
!  AHEAD of the actual time that they cause action in the Framework.

!  Assign the offset to be used by all Trigger Framework signals.
!  Start FW signals 5 Ticks (about 88 nsec) ahead of time.

Assign  FW_OS  =  -5


!  Program the Tick Clock which is Time Line 0
!  -----------======--------------------------

!  Assign the Tick Clock offset.

Assign  FW_Tick_OS  =  0   ! Tick Clock marks the start of a FW Tick.
                           ! This signal is used only by the Framework.

!  The Tick Clock is up at 0, 7, 14..... and should be up for 1 bucket only.

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +0     For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +7     For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +14    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +21    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +28    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +35    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +42    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +49    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +56    For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +63    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +70    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +77    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +84    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +91    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +98    For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +105   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +112   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +119   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +126   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +133   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +140   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +147   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +154   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +161   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +168   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +175   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +182   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +189   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +196   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +203   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +210   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +217   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +224   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +231   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +238   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +245   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +252   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +259   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +266   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +273   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +280   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +287   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +294   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +301   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +308   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +315   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +322   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +329   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +336   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +343   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +350   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +357   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +364   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +371   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +378   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +385   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +392   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +399   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +406   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +413   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +420   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +427   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +434   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +441   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +448   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +455   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +462   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +469   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +476   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +483   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +490   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +497   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +504   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +511   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +518   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +525   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +532   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +539   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +546   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +553   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +560   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +567   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +574   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +581   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +588   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +595   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +602   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +609   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +616   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +623   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +630   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +637   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +644   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +651   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +658   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +665   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +672   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +679   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +686   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +693   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +700   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +707   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +714   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +721   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +728   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +735   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +742   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +749   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +756   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +763   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +770   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +777   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +784   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +791   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +798   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +805   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +812   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +819   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +826   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +833   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +840   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +847   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +854   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +861   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +868   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +875   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +882   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +889   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +896   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +903   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +910   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +917   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +924   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +931   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +938   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +945   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +952   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +959   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +966   For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +973   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +980   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +987   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +994   For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1001  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1008  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1015  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1022  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1029  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1036  For  1

Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1043  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1050  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1057  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1064  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1071  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1078  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1085  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1092  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1009  For  1
Set  T0  Up  Glb_OS+FW_OS+FW_Tick_OS  +1106  For  1





!  Now program the Trigger Framework TRM Clock which is Time Line 1
!  ---------------------------------=====--------------------------

!  It should be 1 bucket later than the Tick Clock and otherwise identical.
!  So the TRM Clock is up at 1, 8, 15..... and should be up for 1 bucket only.

!  Assign the TRM Clock offset.

Assign  FW_TRM_OS  =  +1   ! TRM Clock starts 18.8 nsec into the FW tick.
                           ! This signal is used only by the Framework.

Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +0     For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +7     For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +14    For  1
.
.
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1092  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1009  For  1
Set  T1  Up  Glb_OS+FW_OS+FW_TRM_OS  +1106  For  1





!  Now program the Beginning of Turn marker which is Time Line 2
!  ----------------=================----------------------------

!  This is the once per accelerator turn marker.  It should be up for
!  7 buckets and should rise 3 buckets before the FW Tick Clock.
!  The Beginning of Turn Marker is used both by the FW and the SCL.
!  The SCL must send out this signal early enough so that it reaches
!  front-end by the actual beginning of turn.  Note also that the
!  FW needs it 1 tick earlier (for its Tick and Turn Scalers) then
!  when the SCL should receive it.

!  Assign the Beginning of Turn Marker delay.

Assign  Beg_Trn_Dl  = -31       ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

!  Assign the Beginning of Turn Marker offset.

Assign Beg_Trn_OS  = +98	! The offset indicates the RF Bucket
				! that we are aiming for out in the 
				! Geo Section.  This is chosen so that
				! the first live crossing in Super Bunch #1
				! corresponds to Current Crossing #7.

Set  T2  Up  Glb_OS+FW_OS+Beg_Trn_Dl+Beg_Trn_OS  For  7





!  Program the  Interaction Marker  Signal which is Time Line 3
!  ------------====================----------------------------

!  The Interaction Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  one tick long and occurs for each of the 36 crossings in an
!  accelerator turn

!  Assign the Interaction Marker delay.

Assign  Interaction_Dl = -31    ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+140    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+161    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+182    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+203    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+224    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+245    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+266    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+287    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+308    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+329    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+350    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+371    For  7

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+511    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+532    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+553    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+574    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+595    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+616    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+637    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+658    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+679    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+700    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+721    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+742    For  7

Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+882    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+903    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+924    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+945    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+966    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+987    For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1008   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1029   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1050   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1071   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1092   For  7
Set  T3  Up  Glb_OS+FW_OS+Interaction_Dl+1113   For  7





!  Program the  COSMIC GAP Marker  Signal which is Time Line 4
!  ------------===================----------------------------

!  The COSMIC GAP Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  asserted during the gap between Super Bunch 1 and Super Bunch 2
!  and during the gap between Super Bunch 2 and Super Bunch 3.

!  Note that as defined near the top of this file the gap between
!  SB #1 and SB #2  begins with RF Bucket 372.  However, the Cosmic
!  Gap marker will not be asserted until the RF Bucket which would 
!  contain a live crossing if this were not a gap, i.e. RF Bucket 392.
!  The same is true for the Cosmic Gap between SB #2 and SB #3, it does 
!  not start until RF Bucket 763.

!  Assign the COSMIC GAP Marker delay.

Assign  COSMIC_Gap_Dl  =  -31   ! The delay is  an integral 
                                ! multiple of 7 RF Buckets.  It
                                ! It reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set T4  Up Glb_OS+FW_OS+COSMIC_Gap_Dl+392  To  Glb_OS+FW_OS+COSMIC_Gap_Dl+510
Set T4  Up Glb_OS+FW_OS+COSMIC_Gap_Dl+763  To  Glb_OS+FW_OS+COSMIC_Gap_Dl+881





!  Now program the  Sync GAP Marker  which is Time Line 5
!  ----------------=================---------------------

!  This is the once per accelerator turn marker.  It is
!  asserted during the gap between Super Bunch 3 and Super Bunch 1
!  and is exactly the same as Cosmic Gap markers.  That is, it is
!  asserted when the next live crossing would happen if this were not a gap
!  and remains active until just before the next live crossing.
!  The Sync Gap Marker is used both by the FW and the SCL and is also
!  an And-Or Network input.
!  The SCL must send out this signal early enough so that it reaches
!  front-ends by the time that we need Sync Gap to occur.   This signal
!  will be delayed in the FW for its use in the TRM's and as an And-Or
!  Network input.

!  Assign the Sync Gap Marker delay.

Assign  Sync_GAP_Dl = -31       ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! It reflects how far early, in ticks,
                                ! we need to generate the Interaction Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3


Set  T5  Up  Glb_OS+FW_OS+Sync_GAP_Dl+21  To  Glb_OS+FW_OS+COSMIC_Gap_Dl+139





!  Now program the  Spare Marker  signal which is Time Line 6
!  ----------------==============----------------------------

!  The Spare Marker signal is distributed to the Front-Ends
!  via the SCL and is used as an And-Or Network Input Term.  It is
!  very similar to the Interaction Marker in that it is
!  one tick long and occurs for each of the 36 crossings in an
!  accelerator turn.  The only difference is that the Spare Marker 
!  continues through the gaps.  At some point during the gap (currently
!  in the middle) the Spare Marker "stutters", i.e. is asserted
!  after only 14 RF Buckets instead of the usual 21.  This allows the
!  Spare Marker to be correctly aligned with the Interaction Marker
!  after the gap.

!  Assign the Spare Marker delay.

Assign  Spare_Dl = -31          ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  It
                                ! reflects how far early, in ticks,
                                ! we need to generate the Spare Marker
                                ! in order for it to make it through the
                                ! SCL Helper Function and then via the SCL
                                ! out to the Geographic Sections at the
                                ! proper time.  A copy of this signal,
                                ! delayed by the SCL Helper Function, is
                                ! used as an And-Or Network Input Term.
                                ! In addition this signal should be
                                ! generated 3 RF Buckets before the FW Tick
                                ! Clock. So its value should be -Nx7 -3

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+140    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+161    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+182    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+203    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+224    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+245    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+266    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+287    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+308    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+329    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+350    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+371    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+392    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+413    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+434    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+448    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+469    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+490    For  7

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+511    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+532    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+553    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+574    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+595    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+616    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+637    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+658    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+679    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+700    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+721    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+742    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+763    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+784    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+805    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+819    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+840    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+861    For  7

Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+882    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+903    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+924    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+945    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+966    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+987    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1008   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1029   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1050   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1071   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1092   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+1113   For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+21    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+42    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+63    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+77    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+98    For  7
Set  T6  Up  Glb_OS+FW_OS+Spare_Dl+119    For  7






!  Now program the Framework HELPER Function Clock which is Time Line 7
!  --------------------------=====================---------------------

!  It should be 2 bucket later than the Tick Clock and otherwise identical.
!  So the HELPER Clock is up at 2, 9, 16... and should be up for 1 bucket only.

!  Assign the HELPER Clock offset.

Assign  FW_HELP_OS  =  +2   ! HELPER Clock starts 37.7 nsec after the FW tick.

Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +0     For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +7     For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +14    For  1
.
.
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1092  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1009  For  1
Set  T7  Up  Glb_OS+FW_OS+FW_HELP_OS  +1106  For  1



!  Now program the Subsystem Strobe which is Time Line 14
!  ----------------================----------------------

!  It should be 5 buckets later than the Tick Clock and up for 3 RF buckets.
!  So the Subsystem Strobe is up at 5, 12, 19.......

!  Assign the Subsystem Strobe offset.

Assign  Subsys_Stb_OS  =  +5	! Subsys Strobe starts 5 RF
				! buckets into the Tick Clock

Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +0     For  3
Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +7     For  3
Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +14    For  3
.
.
Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +1092  For  3
Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +1009  For  3
Set  T14  Up  Glb_OS+FW_OS+Subsys_Stb_OS  +1106  For  3


!  Now program the  Subsystem GAP Marker  which is Time Line 15
!  -----------------====================-----------------------

!  This is a once per accelerator turn marker.  It should rise 4 buckets 
!  before the Subsystem Strobe and be asserted for 118 RF Buckets.
!  The Subsys Gap Marker is used by the FW and can also be an 
!  And-Or Network input.
!  The Subsys Gap Marker mimics the gap signal coming from a front end.
!  It should be delayed relative to the Sync Gap Marker to account for 
!  the delay between the front end and the framework, taken to be about 
!  300 ns.

!  Assign the Subsys Gap Marker delay.

Assign  Subsys_GAP_Dl = -32     ! The delay is  an integral
                                ! multiple of 7 RF Buckets.  
				! In this case, the delay is derived from
				! the corresonding delay for the Sync Gap.
                                ! In addition this signal should be
                                ! generated 4 RF Buckets before the Subsys
                                ! Strobe. So its value should be -Nx7 -4

!  Assign the Subsys Gap Marker offset.

Assign Subsys_GAP_OS = +26	! The offset indicates the RF Bucket
				! that we are aiming for.  This is 
				! 3 Ticks (21 RF buckets) after the
				! Sync Gap.  Additionally, it should be
				! 5 RF buckets later to account for the
				! phase of the Subsys Strobe relative
				! to the Tick Clock.

!  Assign the Subsys Gap Adjust offset.

Assign Subsys_Adj_OS = 7	! This allows the position of the
				! Subsystem Gap to be tweaked for
				! specific tests without
				! altering the two more fundamental
				! values.

Set  T15  Up  Glb_OS+FW_OS+Subsys_GAP_Dl+Subsys_Adj_OS+Subsys_GAP_OS  To 
					Glb_OS+FW_OS+Subsys_GAP_Dl+Subsys_Adj_OS+Subsys_GAP_OS+118




!  Now Program the SCL Hub-End Time Lines
!  ----------------===========-----------

!  The signals generated for use only by the SCL Hub-End are the following:

!         TL8        SCL Clock, Frame Clk, 132 nsec Clk

!  First assign the offset to be used by all the SCL Hub-End signals.
!  For now start with SCL signals with zero offset.

Assign  SCL_OS  =  +0


!  Program the SCL FRAME Clock  which is Time Line 8
!  ---------------=============----------------------------------

!  The SCL Frame Clock is the once every 132 nsec clock that defines
!  "ticks" i.e. frames for the SCL.  It is distributed to the Front-Ends.
!  It is one RF Bucket long and and occurs once every 7 RF Buckets (132 nsec).

!  Assign the SCL Frame Clock offset.

Assign  SCL_TICK_OS  =  +3     ! SCL Frame Clock offset   It is set 57 nsec
                               ! after the FW Tick Clk to allow transport
                               ! and setup of the FW data in the SCL.

Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +0     For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +7     For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +14    For  3
.
.
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1092  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1009  For  3
Set  T8  Up  Glb_OS+SCL_OS+SCL_Tick_OS  +1106  For  3





!  Now Program the  CALORIMETER Precision Readout  Time Lines
!  ----------------===============================-----------


!   Recall that Calorimeter Precision Readout needs the following
!   timing signals:

!         TL9        Calo Xing Clock              Calorimeter
!        TL10        Calo Base Sample             Calorimeter
!        TL11        Calo Peak Sample             Calorimeter
!        TL12        Calo Transfer                Calorimeter

!  For the first tests Calorimeter Precision Readout will operated
!  in a 6x6 mode.

!  So first let's define the 6 crossing points in the 185,186 pattern
!  and set its absolute position with a 6x6 Beam Crossing pattern offset.

Assign  6x6BX_OS = 0

Assign  6x6BX_1 = 182 + 6x6BX_OS
Assign  6x6BX_2 = 6x6BX_1 + 189
Assign  6x6BX_3 = 6x6BX_2 + 182
Assign  6x6BX_4 = 6x6BX_3 + 189
Assign  6x6BX_5 = 6x6BX_4 + 182
Assign  6x6BX_6 = 6x6BX_5 + 189


!  Now assign the offsets and widths that will be used to
!  generate the 4 Calorimeter Time Lines.

Assign     BASE_X = -36

Assign    XING_OS = BASE_X +24
Assign    XING_WD = 3

Assign    BASE_OS = BASE_X - 12
Assign  BASE_HOLD = 29

Assign    PEAK_OS = BASE_OS
Assign  PEAK_HOLD = BASE_HOLD + 122

Assign   TRANS_OS = BASE_OS - 3
Assign   TRANS_WD = BASE_HOLD


! ****************** SETUP T9  (CAL_XING)

SET  T9  UP 6x6BX_1 + XING_OS  FOR  XING_WD
SET  T9  UP 6x6BX_2 + XING_OS  FOR  XING_WD
SET  T9  UP 6x6BX_3 + XING_OS  FOR  XING_WD
SET  T9  UP 6x6BX_4 + XING_OS  FOR  XING_WD
SET  T9  UP 6x6BX_5 + XING_OS  FOR  XING_WD
SET  T9  UP 6x6BX_6 + XING_OS  FOR  XING_WD


! ****************** SETUP T10 (CAL_BASE)

SET  T10  DOWN  6x6BX_1 + BASE_OS  FOR  BASE_HOLD
SET  T10  DOWN  6x6BX_2 + BASE_OS  FOR  BASE_HOLD
SET  T10  DOWN  6x6BX_3 + BASE_OS  FOR  BASE_HOLD
SET  T10  DOWN  6x6BX_4 + BASE_OS  FOR  BASE_HOLD
SET  T10  DOWN  6x6BX_5 + BASE_OS  FOR  BASE_HOLD
SET  T10  DOWN  6x6BX_6 + BASE_OS  FOR  BASE_HOLD


! ****************** SETUP T11 (CAL_PEAK)

SET  T11  DOWN  6x6BX_1 + PEAK_OS  FOR  PEAK_HOLD
SET  T11  DOWN  6x6BX_2 + PEAK_OS  FOR  PEAK_HOLD
SET  T11  DOWN  6x6BX_3 + PEAK_OS  FOR  PEAK_HOLD
SET  T11  DOWN  6x6BX_4 + PEAK_OS  FOR  PEAK_HOLD
SET  T11  DOWN  6x6BX_5 + PEAK_OS  FOR  PEAK_HOLD
SET  T11  DOWN  6x6BX_6 + PEAK_OS  FOR  PEAK_HOLD


! ****************** SETUP T12 (CAL_TRANS)

SET  T12  DOWN  6x6BX_1 + TRANS_OS  FOR  TRANS_WD
SET  T12  DOWN  6x6BX_2 + TRANS_OS  FOR  TRANS_WD
SET  T12  DOWN  6x6BX_3 + TRANS_OS  FOR  TRANS_WD
SET  T12  DOWN  6x6BX_4 + TRANS_OS  FOR  TRANS_WD
SET  T12  DOWN  6x6BX_5 + TRANS_OS  FOR  TRANS_WD
SET  T12  DOWN  6x6BX_6 + TRANS_OS  FOR  TRANS_WD


!  Now program the CFT LED Pulser Trigger which is Time Line 13
!  ----------------======================----------------------

!  It should be up 22 Ticks after BoT and up for 1 RF bucket.

!  First assign the offset to be used by all the CFT signals.
!  For now start with zero offset.

Assign  CFT_OS  =  +0

!  Assign the CFT LED Pulser Trigger offset.

Assign CFT_Pulser_OS = +221	! The offset indicates the RF Bucket
				! that we are aiming for.  This is 
				! 22 Ticks (154 RF buckets) after the
				! Beginning of Turn.  

Set  T13  Up  Glb_OS+CFT_OS+CFT_Pulser_OS For 1