Signal Path through the Level 1 Trigger Framework ------------------------- Original: 3-MAY-1995 Latest: 31-JUL-1995 Introduction ------------ This file tries to describe the critical triggering signal path through the Run II Level 1 Trigger Framework. The critical triggering signal path is defined as: And-Or Input Terms to Start Digitize signals (sent to SLIM). The critical signal path is made up of the following components: (1) Term Receiver Module (TRM): input: unsynchronized And-Or Input Terms output: isochronous And-Or Input Terms (2) And-Or Network Module (AONM): input: isochronous And-Or Input Terms output: Partial And-Or Fired Signals (3) Trigger Decision Module (TDM): input: Partial And-Or Fired Signals output: Specific Trigger Fired Signals (4) Framework Output Module (FOM): input: Specific Trigger Fired Signals output: Start Digitize Signals (to SLIM) Note that some of these cards have inputs which are not listed on this critical path flow. These inputs contribute to the functioning of the cards but do not directly affect the critical path flow. For example, the TDM has several flavors of "disable" inputs, both per-Specific Trigger (e.g. Front-End Busy) and also Global, which are not listed here. Critical Signal Path Examined in Detail --------------------------------------- Let's look at the critical path in more detail, looking carefully at the delays collected at each stage of the processing, including factors like: - input/output translators - # of FPGA's which a signal must travel through - delays (IOB, routing, CLB) within each FPGA - cabling (assumed to be short, <10 ft in most cases Assume that TTL-to-ECL translators are National F100324, and ECL-to-TTL translators are National F100325. Numbers come from 1992 F100K 300 Series data book. The sum of the maximum propagation delay and maximum transition time are used, assuming T=25 degC and SOIC packaging. Assume that the FPGA's are Xilinx XC4025-4. Numbers come from Xilinx 1994 data book (2nd edition) but are not always for the 4025. Data book says to rely on timing calculator in place/route tools for details. Numbers which are likely to be larger in reality (i.e. routing) are indicated with a > symbol. Some timing information does not come from data book but is just guesstimated. These numbers are indicated with a ~ symbol. (1) Term Receiver Module Recall that the TRM simultaneously receives And-Or Input Terms (AOIT's) from multiple L1 Trigger Subsystems (Cal, Muon, etc). These input AOIT's may correspond to different Beam Crossings for each subsystem (depending on the latencies of the various subsystems). Here we are only concerned about the delay from the slowest input AOIT's to the output isochronous AOIT's. Assume that only one trip through a single FPGA is required. Also assume that the TRM FPGA is like a tapped shift register with latched inputs. The "tap" is a function of the latency of the associated L1 Trigger Subsystem but is "built into" the FPGA configuration (i.e. no multiplexers). The slowest AOIT need not pass through any CLB's, let's be optimistic and say that it doesn't. For the faster AOIT's (i.e. the ones that come from the shift register rather than the input), note that clocked CLB delay is lower than clocked IOB delay. Let's give the same clock to the input and the shift register. In reality this may be different clocks or different phases of the same clock. CLOCK ---> GB --. | .---+---+--------+-------------. | | | | V V V V AOITin --> IOB +-> CLB +--> CLB .... +--> CLB -. 1 2,3 | | | | |4 V V V | `----------------------------------> IOB --> AOITout 5 6 The elements which make up the delay are: 1: input ECL/TTL translation 4.4 ns 2-5: single pass through one FPGA, including 2: IOB (setup: pad before CLK, fast) 4.0 ns 3: IOB (prop: CLK to Ix) 6.0 ns 4: IOB -> CLB routing (longline) >7.5 ns 5: IOB (prop, Ox to pad, fast) 5.5 ns 6: output TTL/ECL translation 4.3 ns .---------. TOTAL: | 31.7 ns | `---------' (1.6 ticks) (2) And-Or Network Module: The AONM receives isochronous And-Or Input Terms from TRM's. The delay of interest here is the AOIT input to the output Partial And-Or Fired Signals. Assume that only one trip through a single FPGA is required. Also assume that the AONM FPGA uses 3 stages of logic: first RAM's, then 2 stages of purely combinational logic (8-input AND gates). Assume that the inputs are latched. Note that this arrangement does NOT include a multiplexer to allow 2 different RAM address sources. Adding this multiplexer would add a stage of CLB delay and also the associated routing delay. CLOCK ---> GB --. | .---' | V AOITin --> IOB --> CLB ---> CLB ---> CLB ---> IOB --> PAOFout 1 2,3 4 5 6 7 8 9 10 11 12 1: input ECL/TTL translation 4.4 ns 2-11: single pass through one FPGA, including 40.0 ns (timings 2-11 are estimates, but the above 40.0 ns timing has been verified by NeoCAD trcesh) 2: IOB (setup: pad before CLK, fast) 4.0 ns 3: IOB (prop: CLK to Ix) 6.0 ns 4: IOB -> CLB routing (longline) >7.5 ns 5: CLB (RAM: address to data, 16x2) 4.0 ns 6: CLB -> CLB routing (longline) >7.5 ns 7: CLB (prop: F/G via H' to X/Y) 6.0 ns 8: CLB -> CLB routing (single/double length line) ~5.0 ns 9: CLB (prop: F/G to X/Y) 4.0 ns 10: CLB -> IOB routing (single/double length line) ~5.0 ns 11: IOB (prop: Ox to pad, fast) 5.5 ns 12: output TTL/ECL translation 4.3 ns .---------. TOTAL: | 48.7 ns | `---------' (2.6 ticks) (3) Trigger Decision Module The TDM receives Partial And-Or Fired Signals from AONM's. It also receives various flavors of disable signals. The delay of interest is the Partial And-Or Fired Signals to Specific Trigger Fired Signals. Assume that only one trip through a single FPGA is required. Also assume that the FPGA is implemented as shown in the Run II Level 1 Framework description document. A minimum of 2 CLB delays are necessary to implement the logic as shown in that document. Let's also give the input and output separate clocks so we don't need to be quantized to Beam Crossings: CLOCK ---> GB --. | .---' | V PAOFin --> IOB --> CLB ---> CLB ---> IOB --> STFout 1 2,3 4 5 6 7 8 9 10 1: input ECL/TTL translation 4.4 ns 2-9: single pass through one FPGA, including 30.0 ns (timings 2-9 are estimates, but above 30.0 ns timing has been verified by NeoCAD trcesh) 2: IOB (setup: pad before CLK, fast) 4.0 ns 3: IOB (prop: CLK to Ix) 6.0 ns 4: IOB -> CLB routing (longline) >7.5 ns 5: CLB (prop: F/G to X/Y) 4.0 ns 6: CLB -> CLB routing (single/double length line ~5.0 ns 7: CLB (prop: F/G via H' to X/Y) 6.0 ns 8: CLB -> IOB routing (single/double length line) ~5.0 ns 9: IOB (prop: Ox to pad, fast) 5.5 ns 10: output TTL/ECL translation (for AOITout) 4.3 ns .---------. TOTAL: | 38.7 ns | `---------' (2.1 ticks) (4) Framework Output Module The FOM receives Specific Trigger Fired Signals from TDM's. The delay of interest is the Specific Trigger Fired Signal input to the Start Digitize output. Recall that the Start Digitize output goes to the SLIM. Assume that only one trip through a single FPGA is required. Also assume that the FOM FPGA is closely based on the AONM FPGA. That is, 3 stages of logic: first RAM's, then 2 stages of purely combinational logic (in this case, 8-input OR gates). Assume that the inputs and outputs are latched. Note that this arrangement does NOT count a multiplexer to allow 2 different RAM address sources. Adding this multiplexer would add a stage of CLB delay and also the associated routing delay. inCLK ---> GB --. | .---' | V STFin ---> IOB --> CLB ---> CLB ---> CLB ---> IOB --> SDout 1 2,3 4 5 6 7 8 9 10 11 12 1: input ECL/TTL translation 4.4 ns 2-11: single pass through one FPGA, including 40.0 ns (timings 2-11 are estimates, but the above 40.0 ns timing comes from NeoCAD trcesh simulation of AONM FPGA) 2: IOB (setup: pad before CLK, fast) 4.0 ns 3: IOB (prop: CLK to Ix) 6.0 ns 4: IOB -> CLB routing (longline) >7.5 ns 5: CLB (RAM: address to data, 16x2) 4.0 ns 6: CLB -> CLB routing (longline) >7.5 ns 7: CLB (prop: F/G via H' to X/Y) 6.0 ns 8: CLB -> CLB routing (single/double length line) ~5.0 ns 9: CLB (prop: F/G to X/Y) 4.0 ns 10: CLB -> IOB routing (single/double length line) ~5.0 ns 11: IOB (prop: Ox to pad, fast) 5.5 ns 12: output TTL/ECL translation 4.3 ns .---------. TOTAL: | 48.7 ns | `---------' (2.6 ticks) The total delay of the 4 cards in the critical path is therefore 167.8 ns. This does NOT include settling times or cable delays. What will the cable delays be? There will be 4 cards spread out over 2 crates, plus the trip to the SLIM. Let's call that 4 inter-card connections, with an average length of 5'. Total cable delay from TRM input to SLIM input would then be about 30 ns, with the total minimum delay from TRM input to SLIM output about 197.8 ns. What about settling times? Let's say we can't clock a signal unless it has been around for 20 ns. There are 4 places where this is important (not counting the TRM input settling time, but including the SLIM input settling time). This adds another 80 ns, or 277.8 ns.