Run II Timing Signal Generation and Distribution --------------------------------------------- Original Rev. 15-APR-1997 Most Recent Rev. 22-JUN-2000 This file describes the Timing Signal Generation and Distribution used in the Run II setup. Timing Signals are distributed to the Frameworks, the Serial Command Link Hub End, and to the Level 1 Calorimeter Trigger. Carmen Rotolo's "Master Clock" modules will be used to generate these Run II Timing Signals. Because there is not a spare set of these modules that we can bring back to a Test Rack at MSU we have made a version of the Master Clock (called the Big Ben) to operate at MSU. Note that some signals that are distributed on the Framework P1 Backplanes as Timing Signals are NOT generated by Carmen's Master Clock. These are driven by the Helper Function card. We have divided the P1 Backplane Timing signals in half: P1_TS(7:0) are driven by Carmen P1_TS(15:8) are driven by the Helper Function card Each crate in the Frameworks will receive its timing signals on the P3 connector of its TOM card. There is a special TOM Paddle Board to receive these signals. The TOM Paddle has 4 connectors for receiving timing signals. These connectors are split between the Carmen Master Clock and the Helper Function card as described above. Also note that the Helper Function card itself will require a private (non-P1 Backplane) feed of one or more Carmen Timing Signals. Carmen Rotolo's "Master Clock" Modules: --------------------------------------- Phase Coherent Clock Receives: "Tevatron Sync" and "Tevatron RF". Sends out: 53 MHz, 106 MHz, and SYNC. Sequencer Receives from the Phase Coherent Clock: 53 MHz, 106 MHz, and SYNC. Receives the processed Beam Pickup signals. Detects timing errors between SYNC and Beam Pickup signals. Sends out: 53 MHz, 106 MHz and 23 programmable "Timing Lines". Recall that Time Lines 0 through 11 are the Static Time Lines and Time Lines 12 through 23 are the Dynamic Time Lines. Selector Fanout Module Receives from the Sequencer: 53 MHz, 106 MHz and 23 programmable "Timing Lines". Selects 4 Timing Lines from the 23 available Timing Lines. Sends out 3 copies of each selected Timing Line plus 3 copies of either 53 MHz or 106 MHz. The Master Clock Crate can hold up to 13 Selector Fanout Modules. Generation and Distribution of Signals for L1 Framework ------------------------------------------------------- The following signals have been assigned for use by the L1 Framework: From Carmen: PCLK 53 MHz P1_TS(0) TL0 Tick Clock P1_TS(1) TL1 TRM Clock P1_TS(2) TL2 Beginning of Turn (Framework Time Zone) P1_TS(3) TL3 -------- P1_TS(4) TL4 -------- P1_TS(5) TL5 Framework Gap (Framework Time Zone) P1_TS(6) TL6 -------- P1_TS(7) TL7 BX Clock for the Helper MSA Input 51 From Helper Functions: Transport High-Speed Data P1_TS(8) Capture High-Speed Data P1_TS(9) Capture Monitor Data P1_TS(10) Maginot Line P1_TS(11) Increment L3 Transfer Number P1_TS(12) Transfer Mask to L2 P1_TS(13) Send L2 Decision/Gap Marker at MSU P1_TS(14) Scaler Reset P1_TS(15) For now, it appears that all FW backplanes could receive the same ensemble of P1 Timing Signals (see the Helper notes below, however). That is the baseline model we will use, keeping in mind that we could feed different timing signals to one or more backplanes later if necessary (at the cost of additional Selector Fan Out cards, see below). For the Carmen-generated P1 Timing Signals, therefore, a single Phase-Coherent Clock and Sequencer are required. Five Selector Fan Out's are required: 1 for M122 P1_TS(4:0) aka PCLK, TL0, TL1, TL2, TL3 1 for M122 P1_TS(7:5) aka TL4, TL5, TL6 1 for M123 P1_TS(4:0) aka PCLK, TL0, TL1, TL2, TL3 1 for M123 P1_TS(7:5) aka TL4, TL5, TL6 1 for Helper Function Timing Inputs (at least TL1) The first 4 of these SFO's are fully subscribed, while the last one is only lightly used. This leaves little room for expansion (either driving the same signals to more backplanes or driving different signals to some of our existing backplanes). We should probably reserve space for two or more additional SFO's to preserve some future flexibility. We should also reserve some Sequencer Timing Lines for future expansion as well. The SFO's can directly feed the TOM P1_TS inputs via the Carmen Paddleboard and the Tom Paddleboard. Note that all of the SFO to TOM cables must be the same length. As installed in April 1999 these cables are 30 ft long, 18 flat sections long. On the Carmen Paddleboard the J2, J3, and J4 connectors have the 50 MHz clock on pins 3 and 4 (dir and cmp respectively), selected timing line 3 on pins 7 and 8, selected timing line 2 on pins 11 and 12, selected timing line 1 on pins 15 and 16, and selected timing line 0 on pins 19 and 20. The TOM Paddleboard J2 connector receives the 50 MHz (TS0) on pins 3 and 4 (dir and cmp respectively), TS1 on pins 7 and 8, TS2 on pins 11 and 12, TS3 on pins 15 and 16, and TS4 on pins 19 and 20. The TOM Paddleboard J3 connector receives TS5 on pins 7 and 8, TS6 on pins 11 and 12, and TS7 on pins 15 and 16. P1 Selector Carmen PB Tom PB Tom PB Backplane Sequencer Fan-Out J2, J3, J4 J2 J3 Timing Time Line Channel No. Pin No. Pin No. Pin No. Signal No. --------- ----------- ---------- ------- ------- ---------- 53 MHz PCLK 3, 4 3, 4 0 0 3 7, 8 7, 8 1 1 2 11,12 11,12 2 2 1 15,16 15,16 3 3 0 19,20 19,20 4 4 3 7, 8 7, 8 5 5 2 11,12 11,12 6 6 1 15,16 15,16 7 We will use the Selector Fan-Out Modules starting with the "last" one. The last one is just the 12th one because the 13th Selector Fan-Out slot is being reserved for a second Sequencer. We want to start using the Selector Fan-Outs starting with the 12th one (i.e. last one) because then our cables to the FW will not bury other peoples cables and access to their Selector Fan-Outs. Therefore the following will be the setup: Selector SFO SFO TOM Sequencer -> Fan-Out No. Connector Connector Rack Crate Timing Line Channel # --- --------- --------- ---- ------ ------------------------ 12 J4 J2 M122 Top \ / TL0 -> SFO Ch # 3 12 J3 J2 M122 Middle -- TL1 -> SFO Ch # 2 12 J2 J2 M122 Bottom / \ TL2 -> SFO Ch # 1 \ TL3 -> SFO Ch # 0 11 J4 J3 M122 Top \ / TL4 -> SFO Ch # 3 11 J3 J3 M122 Middle -- TL5 -> SFO Ch # 2 11 J2 J3 M122 Bottom / \ TL6 -> SFO Ch # 1 10 J4 J2 M123 Top \ / TL0 -> SFO Ch # 3 10 J3 J2 M123 Middle -- TL1 -> SFO Ch # 2 10 J2 J2 M123 Bottom / \ TL2 -> SFO Ch # 1 \ TL3 -> SFO Ch # 0 9 J4 J3 M123 Top \ / TL4 -> SFO Ch # 3 9 J3 J3 M123 Middle -- TL5 -> SFO Ch # 2 9 J2 J3 M123 Bottom / \ TL6 -> SFO Ch # 1 8 J4 MSA Input 51 TL7 -> SFO Ch # 3 pins 7,8 of Helper FM Card pins 7,8 on J5 of Rear PB Notes on the Selector Fanout Module (from D0 Note 926 - SFO Hardware Desc.) ----------------------------------- There are nine 8 pin switches on the SFO. In all cases, an open switch corresponds to a 1 and a closed switch corresponds to a 0. Switch number 1 controls the clock output: Programming Switch Bit Number Key No Controlled Function ----------- ------ --------------------------------------------------- Bit 0 1 Retiming Enable Bit 1 2 Clock Select (PCLK or MCLK - probably high for PCLK) Bit 2 3 Clock Out Inhibit Bit 3 4 not used Bits 7:4 8:5 Retiming Delay Switches 2 and 7 are used to control the router and should be left open. Switches 4, 3, 9, and 8 control SFO channels 0 through 3 respectively: Programming Switch Bit Number Key No Controlled Function ----------- ------ -------------------------------------------- Bits 4:0 5:1 Timing Line Select Bit 5 6 Channel Output Inhibit Bits 7:6 8,7 not used Switches 5 and 6 are used to control the decoding of the VME address bits A23:A16 and A15:A8 respectively. For our assignment of timing lines to channels the following is the setup in use in June 1999. Note that the 8th SFO is currently setup to use Sequencer TL00 or TL01 as the source of the Helper Function Clk. Module Delay Ch#0 Ch#1 Ch#2 Ch#3 Clock Function ------ ----- ----- ----- ----- ----- ----- ----------------- 12th 9 TL03* TL02 TL01 TL00 PCLK --\ 11th 9 TL07* TL06* TL05 TL04* PCLK* --/ M122 10th 9 TL03* TL02 TL01 TL00 PCLK --\ 9th 9 TL07* TL06* TL05 TL04* PCLK* --/ M123 8th 9 TL06 TL04 TL00 TL01 PCLK* --- Helper Clock * --> The output is not enabled Trigger Framework - Cables to Carry Timing Signals from Sequencer P3 Paddle Boards (aka Carmen_PB) to the TOM Paddle Board (aka TOM_PB) ----------------------------------------------------------------------- All of these cables are 26 conductor twist and flat with 26 pin connectors tied up in the standard manner. All of these cables should be the same length. It is not clear where the best place is to store the extra cable. The 25MAR99 guess at the cable length is 31 ft to make it to the bottom M122 crate. As installed in April 1999 they are 18 flat sections long. Map of Which Master Clock Generated Signals are in Which Crates ------------------------------------------------------------------- M122 M123 P1_TS ------------------------------- ------------------------------- Signal Top Middle Bottom Top Middle Bottom ------ --------- --------- --------- --------- --------- --------- 0 53 MHz \ 1 TL_0 FW Tick Clock | 2 TL_1 TRM Clock | 3 TL_2 Beginning of Turn | All Crates | have the same 4 N.C. | P1_TS (7:0) 5 N.C. | 6 TL_5 Sync Gap Marker | 7 N.C. / What must be done to feed the Helper Function? ---------------------------------------------- Note that the Helper Function P1 Timing Signals will run "behind" the Carmen P1 Timing Signals. This is planned in the design, such that the Helper Function P1_TS are only "gates" or "enables", and the "clocks" always come from Carmen. Delaying these gates cuts into the (very generous) enable-to-clock setup time in the various FPGA's, and adds to the enable-after-clock hold time: _______________ Helper Function Enable __________/ \______ ___ ___ Carmen Clock ______| |_____________| |________ Note also that all P1 Timing Signals are delayed by 2 periods of the 53 MHz clock in the BSF. We must compensate for this in the programming of the Carmen Master Clock, running the P1 Backplanes essentially 37.6 ns AHEAD of the "actual" time. Note also that we can control the phase of the 53 MHz (PCLK) with respect to the TL outputs on the SFO's. This is crucial to tune the BSF's ability to cleanly latch P1_TS(15:1) with P1_TS(0). For the Helper-generated P1 Timing signals, we have a small problem. The Helper Function card does not have an associated Fan Out card. So when multiple copies of a signal are needed then the Helper itself generates these multiple copies. Map of Which Helper Function Gererated Signals are in Which Crates ---------------------------------------------------------------------- M122 M123 P1_TS ------------------------------- ------------------------------- Signal Top Middle Bottom Top Middle Bottom ------ --------- --------- --------- --------- --------- --------- 8 N.C. N.C. ------------ Transport HSRO Data ----------- * 9 N.C. N.C. Wait_L2_BAD ----- Capture HSRO Data ----- * 10 - Capture L1 MD - Capt L2 MD -- Capture L1 Monitor Data -- * 11 N.C. N.C. L2 Maginot L1 Maginot L2 Maginot L1 Maginot * 12 N.C. N.C. L3_C_D_L_E N.C. L3DS_IL3TN L3_C_D_L_E 13 N.C. N.C. L2 TRM Read N.C. L2 TRM Read N.C. 14 N.C. N.C. N.C. N.C. - Send L2 Decision - 15 ------------------------- Reset Scalers ------------------------ * --> These P1_TS's carry different signals in different crates. L3_C_D_L_E == L3 Control Data Latch Enable L3DS_IL3TN == L3 Data Strobe and Increment L3 Transfer Number Recall that there were a couple of locations where we need some of the signals listed above but there were no P1_TS lines available to route them: L2_FW_Capture_Monitor_Data The two TRM's in M123 Middle which FIFO the L1 Spec Trig Fired Mask will receive this signal via their P5 connector pins 1,2 The FM-Latch in M123 Bottom which buffers control path data to L3 will receive this signal via its P5 connector pins 1,2 A patch panel has been made to perform the mapping of Helper Function card outputs to TOM P1_TS inputs. It is described below in this file. Helper Function Patch Panel --------------------------- Front View of Patch Panel M123 M122 Crate -------------------- --------------------- ----- TS 13:9 TS 8,14,15 TS 13:9 TS 8,14,15 -------- -------- ------------ -------- -------- | #1 | | #2 | |L1 HLP 15:0 | | #9 | | #10 | Top -------- -------- ------------ -------- -------- -------- -------- ------------ -------- -------- | #3 | | #4 | |L1 HLP 31:16| | #11 | | #12 | Middle -------- -------- ------------ -------- -------- -------- -------- ------------ -------- -------- | #5 | | #6 | |L2 HLP 15:0 | | #13 | | #14 | Bottom -------- -------- ------------ -------- -------- -------- -------- ------------ -------- -------- | #7 | | #8 | | Spare | | #15 | | #16 | Spare -------- -------- ------------ -------- -------- Wiring in this Patch Panel -------------------------- Source L1 Helper -=------- Wired Through MSA_Out Output Connector To Destination 15:0 ---------------- ----------------------------------------- pins Number Pins Rack Crate P1_TS Signal Name --------- ------ ------- ---------- ----- ------------------- 1 2 14 7 8 M122 Bot 8 Transport HSRO Data 3 4 15 23 24 not used spare Capture HSRO Data 5 6 15 1 2 not used spare Capture L1 Monitor Data 7 8 5 11 12 M123 Bot 11 L1 Maginot Line 9 10 15 3 4 not used L1-Helper MSA_Out_4 11 12 15 5 6 not used L1-Helper MSA_Out_5 13 14 15 7 8 not used L1-Helper MSA_Out_6 15 16 14 15 16 M122 Bot 15 Scaler Reset 17 18 6 7 8 M123 Bot 8 Transport HSRO Data 19 20 4 7 8 M123 Mid 8 Transport HSRO Data 21 22 2 7 8 M123 Top 8 Transport HSRO Data 23 24 5 3 4 M123 Bot 9 Capture HSRO Data 25 26 3 3 4 M123 Mid 9 Capture HSRO Data 27 28 1 3 4 M123 Top 9 Capture HSRO Data 29 30 11 7 8 M122 Mid 10 L1 Capture Mon Data 31 32 9 7 8 M122 Top 10 L1 Capture Mon Data 33 34 unused Source L1 Helper -=------- Wired Through MSA_Out Output Connector To Destination 31:16 ---------------- ----------------------------------------- pins Number Pins Rack Crate P1_TS Signal Name ---------- ------ ------- ---------- ----- ------------------- 1 2 5 7 8 M123 Bot 10 L1 Capture Mon Data 3 4 3 7 8 M123 Mid 10 L1 Capture Mon Data 5 6 1 7 8 M123 Top 10 L1 Capture Mon Data 7 8 1 11 12 M123 Top 11 L1 Maginot Line 9 10 15 9 10 TCC Pause/Resume to Glb Disable TRM 11 12 15 11 12 not used TCC_Controllable_Signal_0 13 14 15 13 14 not used TCC_Controllable_Signal_1 15 16 12 15 16 M122 Mid 15 Scaler Reset 17 18 10 15 16 M122 Top 15 Scaler Reset 19 20 6 15 16 M123 Bot 15 Scaler Reset 21 22 4 15 16 M123 Mid 15 Scaler Reset 23 24 2 15 16 M123 Top 15 Scaler Reset 25 26 15 15 16 not used CMD_Armed_Signal_0 27 28 15 17 18 not used CMD_Armed_Signal_1 29 30 15 19 20 not used L1-Helper MSA_Out_30 31 32 15 21 22 not used L1-Helper MSA_Out_31 33 34 unused Source L2 Helper -=------- Wired Through MSA_Out Output Connector To Destination 15:0 ---------------- ----------------------------------------- pins Number Pins Rack Crate P1_TS Signal Name --------- ------ ------- ---------- ----- -------------------- 1 2 13 19 20 M122 Bot 13 Input_TRM_Read_Enable 3 4 3 19 20 M123 Mid 13 Input_TRM_Read_Enable 5 6 4 11 12 M123 Mid 14 Send_L2_Decision 7 8 6 11 12 M123 Bot 14 Send_L2_Decision 9 10 13 15 16 M122 Bot 12 L3_Control_Data_Ltch_Enb 11 12 5 15 16 M123 Bot 12 L3_Control_Data_Ltch_Enb 13 14 3 15 16 M123 Mid 12 L3_Data_Strb_Inc_Xfr_Num 15 16 13 11 12 M122 Bot 11 L2_Maginot_Line 17 18 3 11 12 M123 Mid 11 L2_Maginot_Line 19 20 13 7 8 M122 Bot 10 L2_Capture_Monitor_Data 21 22 13 3 4 M122 Bot 9 Waiting_for_L2_BAD 23 24 8 3 4 not used spare Send_L2_Decision 25 26 8 5 6 not used spare L3_Control_Data_Latch_Enable 27 28 8 7 8 not used spare L3_Data_Strobe_Inc_Xfr_Number 29 30 8 9 10 not used spare L2_Capture_Monitor_Data 31 32 8 11 12 not used spare L2_Answer_TRM_Write_Clock 33 34 not used Generation and Distribution of Signals for SCL Hub End ------------------------------------------------------ For the SCL Hub End, the following signals have been assigned: Sequencer Time Line SCL Hub-End Function --------- ------------------------------------- PCLK 53 MHz RF clock TL8 Front End Gap Marker TL9 Interaction Marker TL10 Beginning of Turn (Front End Time Zone) TL11 SCL Clock TL12 Spare Marker for SCL TL13 Cosmic Gap Marker The SCL Hub End can share the Framework's PCC and Sequencer. It will require two (?) Selector Fan Out modules. The SCL Hub End will receive Carmen PCLK and TL11 (SCL Clock) on twinax cables (fed through a standard Carmen-built paddleboard). The remaining Master Clock signals will be on normal twist-and-flat cabling (sourced through one of our Carmen paddleboards), which will either pass through a patch panel or specialized cabling to be mapped into the appropriate arrangement for the SCL Hub End. Generation and Distribution of Signals for the Cal Trig ------------------------------------------------------- We should know more about this after the Paris workshop in March 1999. However, it already seems certain that the L1 Cal Trig can NOT share the Sequencer with the Framework and SCL HE. The limiting factors are the 23 Timing Lines (~13 of which are already allocated) and the 13 SFO's (~9 of which are already allocated). ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ The following is background reference information about the Carmen Selector-Fanout, the Carmen_PB, and the TOM_PB. Additional information about both of the PB cards can be found in their hardware directories. Selector Fanout Module J3 Backplane Output Pinout The outputs for the 3 copies of each of the 4 selected Timing Lines and the 53 MHz or 106 MHz clock are all on P3 slots 8 through 20. Copy #1 Copy #2 Copy #3 -------- -------- -------- Non Inv Non Inv Non Inv --- --- --- --- --- --- Selected TL #0 B9 C9 B17 C17 B23 C23 Selected TL #1 B10 C10 B19 C19 B24 C24 Selected TL #2 B11 C11 B20 C20 B25 C25 Selected TL #3 B12 C12 B21 C21 B26 C26 Selected Clock B13 C13 B22 C22 B27 C27 The grounds on these J3 connectors are on pins: B3, A5, A9, A13, A17, C18, A21, A25, A29, B29, Selector Fanout Module P3 Paddle Board (aka Carmen Card) --------------------------------------------------------- This is the version made at MSU, not the Carmen-built version. +---------------------------------------------------------+ | A1 B1 C1 +---+ | +---------+ +-----+ | * | | | * | | J2 + + | | | | | | + + | C | | | J1 | | 26 + + | A | | | | | pin + + +-----+ | B | | | | |* + + | J4 + + | L | | | 96 | +-----+ | + + | E | | | pin | | 26 + + | | | | DIN | +-----+ | pin + + | C | | | | | J4 + + |* + + | L | | | 90 deg | | + + +-----+ | A | | | solder | | 26 + + | M | | | tail | | pin + + | P | | | | |* + + | | | +---------+ +-----+ | * | | | A,B,C 32 +---+ | +---------------------------------------------------------+ The Carmen Card is shown with the 26 pin headers facing the "wrong" way. Installing the headers in this way (and routing the flat cables) up and over the headers allows us to have the Selector FanOut "53 MHz Clock" signal at the pin #1 end of the 26 pin headers. Installing these 26 pin headers in the funny way allows all other aspects of the master clock wiring to use standard practices (brown/tan pair at pin #1 end of all cable connectors, all components on the standard Eurocard side of the board) and still get the Selector Fanout "53 Mhz Clock" signal to TOM's Timing Signal #0. Carmen_PB J1 Connector to the Selector FanOut ----------------------------------------------------------------- Pin Num Row A Row B Row C --- ------------------- ------------------- ------------------- 1 nc nc nc 2 nc nc nc 3 nc GND nc 4 nc nc nc 5 GND nc nc 6 nc nc nc 7 nc nc nc 8 nc nc nc 9 GND SELCTD_0_COPY_1_DIR SELCTD_0_COPY_1_CMP 10 nc SELCTD_1_COPY_1_DIR SELCTD_1_COPY_1_CMP 11 nc SELCTD_2_COPY_1_DIR SELCTD_2_COPY_1_CMP 12 nc SELCTD_3_COPY_1_DIR SELCTD_3_COPY_1_CMP 13 GND SELCTD_CLK_CP_1_DIR SELCTD_CLK_CP_1_CMP 14 nc nc nc 15 nc nc nc 16 nc nc nc 17 GND SELCTD_0_COPY_2_DIR SELCTD_0_COPY_2_CMP 18 nc nc GND 19 nc SELCTD_1_COPY_2_DIR SELCTD_1_COPY_2_CMP 20 nc SELCTD_2_COPY_2_DIR SELCTD_2_COPY_2_CMP 21 GND SELCTD_3_COPY_2_DIR SELCTD_3_COPY_2_CMP 22 nc SELCTD_CLK_CP_2_DIR SELCTD_CLK_CP_2_CMP 23 nc SELCTD_0_COPY_3_DIR SELCTD_0_COPY_3_CMP 24 nc SELCTD_1_COPY_3_DIR SELCTD_1_COPY_3_CMP 25 GND SELCTD_2_COPY_3_DIR SELCTD_2_COPY_3_CMP 26 nc SELCTD_3_COPY_3_DIR SELCTD_3_COPY_3_CMP 27 nc SELCTD_CLK_CP_3_DIR SELCTD_CLK_CP_3_CMP 28 nc nc nc 29 GND GND nc 30 nc nc nc 31 nc nc nc 32 nc nc nc Carmen_PB J4 Typical of J2 and J3 26 Pin Cable Connectors ----------------------------------------------------------------- Pin Pin Num Function Num Function --- ------------------- --- ------------------- 1 GND 2 GND 3 SELCTD_CLK_CP_1_DIR 4 SELCTD_CLK_CP_1_CMP 5 GND 6 GND 7 SELCTD_3_COPY_1_DIR 8 SELCTD_3_COPY_1_CMP 9 GND 10 GND 11 SELCTD_2_COPY_1_DIR 12 SELCTD_2_COPY_1_CMP 13 GND 14 GND 15 SELCTD_1_COPY_1_DIR 16 SELCTD_1_COPY_1_CMP 17 GND 18 GND 19 SELCTD_0_COPY_1_DIR 20 SELCTD_0_COPY_1_CMP 21 GND 22 GND 23 GND 24 GND 25 GND 26 GND TOM Paddle Board ---------------- This card has a standard 160 pin female 90 degree solder tail DIN connector on one side and four 26 pin 4 wall 90 degree solder tail male headers with latches on the opposite side. This card is the same physical layout as the Rear_Paddle_Board. The following is an outline of the TOM Paddle Board as seen looking at its "component" side. ---------------------------+ / TOP | / +----+-- +----+-- | +----- |O | |O | | | | J2 | | J3 | | +-+----+ | | | | | | | | | TS | | TS | | | | | | 0:4| | 5:7| | | | J1 | +----+-- +----+-- | | | | | | | | +--- +-- +----+- | | | | |O | |O | | | | O | | J4 | | J5 | | All connectors +-+----+ | | | | | are mounted on | | TS | |TS 8, | the Component +----- |9:13| |14,15 | side of the TOM \ +----+-- +----+-- | Paddle Board. \ | ---------------------------+ Connections to the Four Flat Cable Connectors ------------------------------------------------------------------ ---------------- ---------------- ---------------- ---------------- J2 J3 J4 J5 Timing_Sig 0:4 Timing_Sig 5:7 Timing_Sig 8:12 Timing_Sig 13:14 ---------------- ---------------- ---------------- ---------------- Pin Pin Pin Pin Pin Pin Pin Pin Num Fun Num Fun Num Fun Num Fun Num Fun Num Fun Num Fun Num Fun ------- ------- ------- ------- ------- ------- ------- ------- 1 g 2 g 1 g 2 g 1 g 2 g 1 g 2 g 3 TS0+ 4 TS0- 3 via 4 via 3 TS9+ 4 TS9- 3 via 4 via 5 g 6 g 5 g 6 g 5 g 6 g 5 g 6 g 7 TS1+ 8 TS1- 7 TS5+ 8 TS5- 7 TS10+ 8 TS10- 7 TS8+ 8 TS8- 9 g 10 g 9 g 10 g 9 g 10 g 9 g 10 g 11 TS2+ 12 TS2- 11 TS6+ 12 TS6- 11 TS11+ 12 TS11- 11 TS14+ 12 TS14- 13 g 14 g 13 g 14 g 13 g 14 g 13 g 14 g 15 TS3+ 16 TS3- 15 TS7+ 16 TS7- 15 TS12+ 16 TS12- 15 TS15+ 16 TS15- 17 g 18 g 17 g 18 g 17 g 18 g 17 g 18 g 19 TS4+ 20 TS4- 19 via 20 via 19 TS13+ 20 TS13- 19 via 20 via 21 g 22 g 21 g 22 g 21 g 22 g 21 g 22 G 23 g 24 g 23 g 24 g 23 g 24 g 23 g 24 G 25 g 26 g 25 g 26 g 25 g 26 g 25 g 26 G Layout of the TOM's J3 Timing Signal Inputs: ---------------------------------------------- TOM's J3 LAYOUT ---------------------------------------------------------------- Pin Row Row Row Row Row Number "A" "B" "C" "D" "E" ------ --------- --------- ------- ------- ------- 1 Gnd Gnd Gnd Gnd N.C. 2 TS_00_INV TS_00_NON +3V Gnd N.C. 3 Gnd Gnd Gnd Gnd N.C. 4 TS_01_INV TS_01_NON +3V Gnd N.C. 5 Gnd Gnd -4.5V Gnd N.C. 6 TS_02_INV TS_02_NON Gnd Gnd N.C. 7 Gnd Gnd +3V Gnd N.C. 8 TS_03_INV TS_03_NON Gnd Gnd N.C. 9 Gnd Gnd +5V Gnd N.C. 10 TS_04_INV TS_04_NON Gnd Gnd N.C. 11 Gnd Gnd +3V Gnd N.C. 12 TS_05_INV TS_05_NON Gnd Gnd N.C. 13 Gnd Gnd +3V Gnd N.C. 14 TS_06_INV TS_06_NON Gnd Gnd N.C. 15 Gnd Gnd -4.5V Gnd N.C. 16 TS_07_INV TS_07_NON Gnd Gnd N.C. 17 Gnd Gnd +3V Gnd N.C. 18 TS_08_INV TS_08_NON Gnd Gnd N.C. 19 Gnd Gnd +5V Gnd N.C. 20 TS_09_INV TS_09_NON +3V Gnd N.C. 21 Gnd Gnd Gnd Gnd N.C. 22 TS_10_INV TS_10_NON +3V Gnd N.C. 23 Gnd Gnd Gnd Gnd N.C. 24 TS_11_INV TS_11_NON -4.5V Gnd N.C. 25 Gnd Gnd Gnd Gnd N.C. 26 TS_12_INV TS_12_NON +3V Gnd N.C. 27 Gnd Gnd Gnd Gnd N.C. 28 TS_13_INV TS_13_NON +5V Gnd N.C. 29 Gnd Gnd +3V Gnd N.C. 30 TS_14_INV TS_14_NON Gnd Gnd N.C. 31 Gnd Gnd +3V Gnd N.C. 32 TS_15_INV TS_15_NON Gnd Gnd N.C. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ The following is an old version of some parts of this file. M123 M122 Helper Function Generated ------------------- ------------------- P1 Timing Signals P1_TS# Top Middle Bottom Top Middle Bottom ------------------------- --- ------ ------ --- ------ ------ 8 Transport HSRO Data X X X X 9 Capture HSRO Data X X X X 10 Capture Monitor Data X X X X X X 11 Maginot Line X X 12 Increment Level 3 X Transfer Number 13 Transfer Mask to L2 X 14 Send L2 Decision/ X Gap Marker at MSU 15 Scaler Reset X X X X X X Counting up X's, we come up with 25 Timing Signals. Each crate will get the necessary subset of the 8 Helper P1 Timing Signals. This is still not too complicated to think about. Front View of Patch Panel M123 M122 TS 13:9 TS 8,14,15 TS 13:9 TS 8,14,15 -------- -------- ------------ -------- -------- | #1 | | #2 | |Helper 31:16| | #9 | | #10 | Top -------- -------- ------------ -------- -------- -------- -------- ------------ -------- -------- | #3 | | #4 | |Helper 15:0 | | #11 | | #12 | Middle -------- -------- ------------ -------- -------- -------- -------- ----------- -------- -------- | #5 | | #6 | | Spare | | #13 | | #14 | Bottom -------- -------- ----------- -------- -------- -------- -------- ----------- -------- -------- | #7 | | #8 | | Spare | | #15 | | #16 | Spare -------- -------- ----------- -------- -------- Source Destination Helper 15:0 pins TS Rack Crate pins Connector ---------------- -- ------------------ --------- 1 2 8 M122 B 7 8 14 3 4 9 M122 B 3 4 13 5 6 10 M122 B 7 8 13 7 8 11 M123 B 11 12 5 9 10 12 M123 M 15 16 3 11 12 13 M123 M 19 20 3 13 14 14 M123 M 11 12 4 15 16 15 M122 B 15 16 14 17 18 8 M123 B 7 8 6 19 20 8 M123 M 7 8 4 21 22 8 M123 T 7 8 2 23 24 9 M123 B 3 4 5 25 26 9 M123 M 3 4 3 27 28 9 M123 T 3 4 1 29 30 10 M122 M 7 8 11 31 32 10 M122 T 7 8 9 33 34 unused Helper 31:16 pins TS Rack Crate pins Connector ----------------- -- ------------------ --------- 1 2 10 M123 B 7 8 5 3 4 10 M123 M 7 8 3 5 6 10 M123 T 7 8 1 7 8 11 M123 T 11 12 9 10 12 unused 11 12 13 unused 13 14 14 unused 15 16 15 M122 M 15 16 12 17 18 15 M122 T 15 16 10 19 20 15 M123 B 15 16 6 21 22 15 M123 M 15 16 4 23 24 15 M123 T 15 16 2 25 26 unused 27 28 unused 29 30 unused 31 32 unused 33 34 unused Every Helper P1 Timing Signal therefore must come directly from the Helper card, which has only 32 outputs (not the 48 which would be required to drive 8 signals to each of 6 backplanes). So let's look at which Helper Function P1 Timing Signals are actually USED in each crate: