Timing Signal Skew
                    ----------------------

                                                 Original Ver.  22-SEP-1998
                                                   Latest Ver.  22-SEP-1998


The first section of this file describes the timing signal skew up to
the point of the P1 Timing Signals arriving at the  THE-Card  Board
Support Functions FPGA.  The accumulated skew along the path to the BSF
FPGA includes:

  1. skew in generation of the Timing Lines in the Master Clock
  2. skew in transport of these signals to the TOM board
  3. skew going through the TOM board
  4. skew in transport across the P1 backplane (to a given slot,
          i.e. not the slot to slot skew)
  5. skew during reception and delivery to the BSF FPGA on THE-Card


A maximum value for item #1 will be estimated below.

Item #2 is assumed to be zero.  The justification for this is that we do
not use the outer pairs on the twist and flat cable and that we use only
every other pair in the center section of the cable.  Also these lines
are relatively short and have only a single properly terminated load.

A maximum value for item #3 will be estimated below.

Item #4 is assumed to be zero.  This is because of the high degree of
symmetry in the layout of the timing signals in the top section of the
P1 backplane.  Note that the delay of P1_TS#0 and P1_TS#8 going across
this backplane may be slightly different than that of the other 14
P1 Timing Signals.

A maximum value for item #5 will be estimated below.

The estimate of the maximum skew in the P1 Timing Signals reaching the
THE-Card BSF FPGA will be the sum of the maximum estimate for items:
#1, #3, and #5.  Note again that this does not include P1_TS#0  i.e.
the 53 MHz clock, which is both generated in the Master Clock with a
phase that is independent of the Master Clock Time Lines, and is
transported across the top of the P1 backplane with possibly a
different delay than the 14 "bulk" P1 Timing Signals.  All times listed
below are in the normal unit of nano-seconds.


Time Line Generation in the Master Clock   Item #1

   10H186  U99  "D" FF  clock to output      0.7 min   2.7 max    2.0 skew
   10H158  U93  mux input to output          1.0 min   1.8 max    0.8 skew
   10H101  output oscillator xxx driver      0.7 min   1.5 max    0.8 skew
                                                                  ------
                                                                  3.6 max skew

Transport through the TOM circuit board   Item #3

   100314  diff receiver input to output     0.8 min   1.6 max    0.8 skew
   100316  diff driver   input to output     0.6 min   2.1 max    1.5 skew
                                                                  ------
                                                                  2.3 max skew
Reception on THE-Card   Item #5

   100325  diff receiver ECL in to TTL out   0.9 min   3.5 max    2.6 skew
             different values up vs down     1.7 min   4.3 max    2.6 skew
                                                                  ------
                                                                  3.4 max skew

                   TOTAL of the maximum skew from each section:   9.3 max skew