ADF System ---------- In the D-Zero Run IIB Level 1 Calorimeter Trigger the ADF System (Analog Digital Filter) is responsible for sending to the 8 TAB cards the best estimate of the Et energy in the EM and Hadronic sections of the 1280 Trigger Towers for each Tevatron beam crossing. The calculation of these Et values by the 80 ADF cards is based upon the 2560 analog trigger signals that the ADF cards receive from the Calorimeter front-end electronics and upon the timing and control signals that are distributed through out the D-Zero DAQ system by the Serial Command Links. The ADF system is setup and monitored by a Trigger Control Computer (TCC) that is described elsewhere in this article. Generation of Trigger Signals by the Calorimeter Front-End Electronics ---------------------------------------------------------------------- The D-Zero Calorimeter front-end electronics consists of preamplifiers, which are mounted up on the Calorimeter next to its signal feed through ports, and Base Line Subtracter cards (BLS cards) which are mounted down in the platform area under the Calorimeter (Reference for the Calorimeter Front-End Electronics here). On the BLS cards the preamplifier output signals are split into two analog paths. One path leads through switch capacitor analog storage arrays to the precision readout system for the Calorimeter and the other path leads to the generation of the projective Trigger Tower based trigger signals which are used by the L1 Calorimeter Trigger. Each Trigger Tower consists of an EM section and a Hadronic section. One Trigger Tower covers a 0.2 x 0.2 eta,phi section of the Calorimeter. Typically the signals from 28 EM Calorimeter cells and 12 Hadronic Calorimeter cells belong to the eta,phi area covered by one Trigger Tower. Each BLS card forms the EM and Hadronic trigger signals for one Trigger Tower. In response to an energy deposit, the preamplifier output signal for a given Calorimeter cell has a smooth step function like waveform with the amplitude of the step being proportional to the energy E deposited in that cell. Formation of a trigger signal begins by differentiation, with a 55 nsec time constant, of all the preamplifier output signals that contribute to a given trigger signal. All of these differentiated preamplifier output signals are then individually scaled, by passing through a resistor, before being summed to make the trigger signal. This scaling of the preamplifier signals that contribute to a given trigger signal is necessary, before they can be summed, for two basic reasons: - Different sections and depths of the Calorimeter have different sampling fractions and thus different preamplifier output step amplitudes for a given value of energy deposited in the Calorimeter. - The different Calorimeter cells that contribute to a given trigger signal have different cell capacitances and thus they have different preamplifier output signal rise-times. Because of the different rise-times the differentiated preamplifier output signals have different amplitudes for a given value of energy deposited in the Calorimeter. The trigger signal scaling on the BLS cards is also used to accomplish part of the Calorimeter energy E to Et conversion. The Level 1 Calorimeter Trigger calculations are based on the Et energy in each Trigger Tower whereas the un-scaled signals on the BLS cards and the precision readout of the Calorimeter are in terms of energy E. For the highest eta Trigger Towers the value of Et is only about 1/30 th of the value of E. For accurate processing of these signals, with analog circuits having a limited dynamic range, part of the scaling to Et must be done early in the summing circuits on the BLS cards. This is accomplished by assigning three ranges in eta with each range having its own calibration target for BLS card trigger signal output Volts per GeV deposited in the Calorimeter. Within each of these eta ranges the remainder of the scaling to Et is carried out on the ADF cards as described below. Because there are over 1000 BLS cards in the Calorimeter DAQ system, one of the guide lines for the design of the Run IIB Level 1 Calorimeter Trigger was to require no modification to the existing trigger signals generated by these cards. The system of long cables that bring the BLS card trigger signals from the detector platform on the Tevatron side of the shield wall out to the L1 Calorimeter trigger was modified only by the inclusion of a Cable Transition System which is described elsewhere in this article. ADF Card Processing of the Analog Trigger Signals into Digital Et Values ------------------------------------------------------------------------ Each ADF card receives 32 analog trigger signals (Reference here for ADF Card Block Diagram and picture). On a given ADF card these trigger signals represent the EM and Hadronic components of a 4x4 array of Trigger Towers. Each differential AC coupled analog trigger signal is received by a passive circuit that terminates and compensates for some of the characteristics of the long cable that brought the signal out of the collision hall. Following this passive circuit the active part of the analog receiver circuit rejects common mode noise on the differential trigger signal, provides filtering to select the frequency range of the signal caused by a real Tevatron energy deposit in the Calorimeter, and provides additional scaling and a level shift to match the subsequent ADC circuit. The analog level shift in the trigger signal receiver circuit is controlled, separately for each of the 32 channels on an ADF card, by a 12 bit pedestal control DAC. This DAC is used both to set the pedestal of the signal coming out of the ADC that follows the receiver circuit and this DAC is used as a "stand alone" way to test the full signal path on the ADF card (except for a few passive components in the trigger signal input circuit). With no input signal, which is the typical condition because the inputs are AC coupled, the pedestal control DAC can swing the output of the ADC from slightly below zero to mid scale. This is an adequate range to provide a reasonable test of the ADF card's signal path and still provides fine enough control to accurately set the pedestal at the ADC output to within a fraction of a count. During Physics operation we set the pedestal at the ADC output to 50 counts which is a little less than 5% of its full scale range. We can not set the BLS card trigger signal level that represents zero energy deposited in the Calorimeter to be zero ADC counts for two reasons. If we set the ADC output pedestal to zero then during Physics running we could not actually see the pedestal of the BLS card trigger signal and verify that it had not drifted negative. By using this unsigned offset binary system we can both avoid the unnecessary complexity of doing signed arithmetic and still correctly account for both positive and negative noise fluctuations throughout the trigger logic. The 10 bit sampling ADCs that follows the receiver circuit include a track-and-hold function and they complete a conversion in 5 pipeline steps. As controlled by a clock signal, which will be described later, ADC conversions are made every 33 nsec. This is 4 times faster than the potential Tevatron live beam crossing period of 132 nsec. Note that with the current Run IIB Tevatron beam structure, during the periods of beam crossings in each turn which are called "super bunches", there is a live crossing every 396 nsec. There are 159 potential beam crossings locations in a turn of the Tevatron of which 36 have live crossings in the current beam structure. The fundamental clock related to the Tevatron RF has 159 periods of 132 nsec each per turn of the Tevatron. The seemingly higher than necessary ADC conversion rate is used both the reduce the latency going through the pipeline ADCs and to provide the raw data necessary to associate the rather slow rise-time trigger signals (200 nsec typical rise-time) with the correct Tevatron beam crossing. Associating energy deposits in the Calorimeter with the correct beam crossing is not currently an issue with the live beam crossings spaced 396 nsec apart. Associating Calorimeter energy deposits with the beam crossing that caused them would be a major function of the ADF system if the Tevatron were to run with a 132 nsec live crossing beam structure. On each ADF card the 10 bit outputs from the 32 ADCs flow into a pair of FPGAs, called the data path FPGAs, where the bulk of the signal processing takes place (Reference the ADF Data Path FPGA block drawing here). This signal processing task is split over two FPGAs with each FPGA handling all of the steps in the signal processing for 16 channels. Two FPGAs were used because it simplified the circuit board layout and provided an economical way to obtain the required number of I/O pins. The first step in the signal processing is to align in time all of the 2560 trigger signals. The peak of the trigger signals from a given beam crossing arrive at the L1 Calorimeter Trigger at different times because of the different length cable runs from the Calorimeter front-end electronics and because the high capacitance sections of the Calorimeter respond more slowly. This initial signal processing step makes the digitized signals from all Trigger Towers isochronous and that simplifies the operation of the rest of the L1 Calorimeter Trigger. The Trigger Tower signals are lined up in time by delaying the early signals in shift registers. The 10 bit wide data for each channel passes through a variable length shift register that steps the data every 33 nsec. The length of the shift register for a given channel is controlled by the value that is written into a control-status register for that channel by the Trigger Control Computer. Once the trigger signals have been made isochronous they are sent to both the raw ADC data circular buffers where monitoring data is recorded and to the input of the digital filter stage. The raw ADC data circular buffers are typically setup to record all of the ADC samples (636 samples) in a full turn of the accelerator. Once the writing of monitor data into these circular buffers has been started by the Trigger Control Computer it can be stopped in one of three ways. The Trigger Control Computer can synchronously stop the writing of data into these circular buffers for all 2560 channels in the system or TCC can setup the system so that the writing of data into these circular buffers will synchronously stop for all channels the next time that an L1 Accept is issued that includes a flag indicating that monitoring data should be collected. During normal Physics operation L1 Accepts with the collect monitor data flag are issued about once every 5 seconds. Using the collect monitor data flagged L1 Accept to stop the writing of data into the raw ADC data circular buffers is the normal mode of operation. The advantage of this mode is that it helps to collect a turn's worth of raw ADC monitor data that includes some signals from real Tevatron energy deposits in the Calorimeter. The third mode for stopping the writing of data into these circular buffers is to allow each channel to operate and stop independently when its trigger signal has risen above some programmable minimum threshold. This third mode is used to collect data to study the timing and shape of the trigger signals from the BLS cards. The raw ADC monitor data from these circular buffers is readout by the Trigger Control Computer and sent to a monitoring system which is described elsewhere in this article. The address of the data in these circular buffers has a known alignment with the accelerator beam crossings. The raw ADC data circular buffers can also be loaded by the TCC with simulation data. For testing this raw ADC simulation data can then be played through the rest of the down stream signal processing stages. The digital filter in the signal processing path can be used to remove high frequency noise from the trigger signals and to remove low frequency shifts in the baseline. During the initial Physics operation of this new L1 Calorimeter Trigger the filter stage has been setup to select the ADC sample from the point in time where the peak of the trigger signal is located and then to passes that data through to the next stage. This mode of operation allowed the most direct comparison of the trigger signals in this new Calorimeter Trigger with the old system. The 10 bit output from the filter stage has the same scale and offset as the output from the ADCs. The filter output is used as the 10 bit address to a lookup memory. The 8 bit data words in this lookup memory are the Et values that are sent out from the ADF system to the TAB cards. Currently the lookup memories are programmed with "straight line" data. The slope of the straight line data in a given lookup memory is used to implement the final step in the conversion from energy E to Et for that channel. TCC programs the straight line data in all channels so that the point with address 50 contains Et data value 8. The Et data sent to the TAB cards is defined to have a uniform scale of 1 count equals 0.25 GeV of Et with a pedestal of 8 counts. Without this pedestal only positive noise fluctuation would be sent to the TAB cards. That would result in "rectifier effect", i.e. the summation of positive noise fluctuations when arrays of Trigger Towers are summed together in the various steps of the trigger algorithms. In each channel the Et data from the lookup memory is one of the 4 inputs to that channel's output multiplexer. The output multiplexer, on a clock cycle by clock cycle basis, selects which of its 4 inputs is sent out to the TAB cards. The 4 inputs to the output multiplexer are: the Et data from the lookup memory, a fixed value from a programmable register, simulation data from the output data circular buffer, and data from a pseudo random noise generator. The output multiplexer for each channel is separately controllable. This control comes from a combination of timing signals and control data that TCC writes into a control-status register for that channel's output multiplexer. The signal selected by the output multiplexer is sent out to the TAB cards and it goes to the input of that channel's output data circular buffer. The output data circular buffers are used to record monitoring data or to playback simulation data in a way that is very similar to the raw ADC data circular buffers which were described above. The monitoring data recorded by the output data circular buffers is a copy of the actual data that is sent to the TAB cards. The output data circular buffers are normally set to be 159 locations long and thus hold a full accelerator turn's worth of data. For normal Physics operation TCC sets up the output multiplexers so that they select their channel's lookup memory Et data for clock periods that have a real beam crossing and they select the contents of their channel's fixed data register for the other clock periods during a turn of the accelerator. The fixed data registers are loaded by TCC with the value 8. Thus the data that is sent out from the ADF system for the non live crossings in each turn is the value which represents zero energy deposited in the calorimeter. Note that the ADF system sends data to the TAB cards for all 159 clock periods during a turn of the accelerator. Occasionally during Physics operation the trigger signal from a BLS card may become too noisy to use in generating the Level 1 triggers. In that case the output multiplexer for that channel is set so that it selects the fixed data register for all 159 clock periods in a turn of the accelerator and thus excludes that channel from participating in the level 1 decision. During testing the output multiplexer, under TCC control, can select either simulation data, fixed data, or pseudo random noise data to send to the TAB cards. Simulation data can be used to send realistic patterns of energy deposits in the Calorimeter to the TAB cards for testing the trigger algorithms. Fixed data, with the fixed data register for each channel programmed by TCC with a unique known value, is used to verify the cabling of the ADF system outputs to the TAB inputs. Pseudo random noise data is used to test the bit error rate on the ADF to TAB links. Data is sent from the ADF system to the TAB cards using a National Semiconductor Channel Link chip set with LVDS signal levels between the transmitter and receiver (Reference here for National Semiconductor Channel Link). Each Channel Link output from an ADF card carries the Et data for all 32 channels (4x4 Trigger Towers) serviced by that card. A new frame of Et data is sent every 132 nsec. All 80 ADF cards begin sending their frame of Et data for a given Tevatron beam crossing at the same point in time. Each frame of Et data also includes: the ID number of the beam crossing in a turn of the Tevatron that produced the Et values reported in this frame, synchronizing information that the TAB cards use to identify which of the 8 Channel Link transfers that make up a full frame of Et data is the first transfer in the frame, and check sum information that the TAB cards use to verify that they have received data free of transport errors. Each ADF card sends out 3 identical copies of its data. This data replication is used to implement "crack-less" trigger algorithms in the TAB cards. Timing and Control Signals from the Serial Command Link ------------------------------------------------------- As mentioned above the ADF system receives its timing and control signals over one of the Serial Command Links (Reference for the SCL here). The Serial Command Link (SCL) system delivers timing and control information to all parts of the D-Zero DAQ system. The ADF system makes use of a number of signals from the SCL. The SCL signals used by the ADF system are: the fundamental 132 nsec clock which is locked to the Tevatron RF system, a marker signal which indicates the first crossing of each turn of the accelerator, a marker signal which flags the clock periods that contain a real beam crossing at D-Zero, and marker signals that indicate when a Level 1 Trigger Accept has been issued and indicate which Level 1 Accepts should be used to initiate the collection of monitoring information. Distribution of these signals from the SCL to the 80 ADF cards is facilitated by a card designed and built by the Saclay Laboratory called the SCL Distributor or SCLD card (Reference the SCLD card here). The SCLD card receives a copy of the SCL information using a standard SCL Receiver mezzanine card. This SCL Receiver mezzanine card is standard to all parts of the D-Zero DAQ system. The SCLD card fans out the signals mentioned above to the 4 VME-64x crates that hold the 80 ADF cards. These signals are transported from the SCLD card to the 4 ADF crates using LVDS level signals. In addition each ADF crate sends back to the SCLD card two LVDS level signals. The 80 ADF cards are held in slots 2 through 21 of 4 VME-64x crates (Reference for Wiener VME Crates here). The ADF card in slot 11 of each crate receives the signals from the SCLD card and directly places them onto spare reserved bused VME-64x backplane lines at TTL open collector signal levels. These backplane lines have normal VME type terminators at each end. All 20 of the ADF cards in a crate pickup their timing and control signals from these backplane lines. The only signal that receives special treatment is the fundamental 132 nsec clock signal. Direct and complement copies of this clock signal are sent across the backplane so that it may be received differentially on each ADF card. Once it is received on an ADF card this clock signal is used only as the reference for an on-board 8x PLL. To provide a high quality clock signal on the ADF card this PLL is built from a discrete voltage controlled crystal oscillator and feedback loop components. With a tracking range of 200 ppm and a loop response of 100 Hz this PLL is well matched to the Tevatron RF, which changes by only 20 ppm during an approximately 1 minute ramp from 150 GeV to 980 GeV, and it provides a much cleaner output signal than a wide bandwidth integrated PLL. The principal need for the high quality clock signal on the ADF card is to provide a clean reference clock for the Channel Link transmitters. It also provides jitter free timing of the ADC samples and thus helps ensure a large spurious free dynamic range from the ADCs. The ADF card in slot 11 of each of the 4 crates also sends back to the SCLD card 2 signals. Currently the ADF system makes use of these 2 signals from only one of the crates. These signals are used to allow the TCC to synchronously cause activity in all 80 ADF cards. One of these signals, when asserted by TCC, causes the writing of monitor data into the circular buffers to immediately and synchronously stop on all 80 ADF cards. The other signal, when asserted by TCC, enables the next L1 Accept, that has been mark to initiate the collection of monitor data, to cause writing to the circular buffers to synchronously stop on all 80 ADF cards. Programming of the ADF System ----------------------------- The ADF cards are controlled over a VME bus. Each ADF card uses a large PAL to implement a "slave only" VME interface. This PAL configures its logic into itself at power up. Once the VME interface is running then the TCC configures the logic into the 2 data path FPGAs on each card. Both data path FPGAs on a given ADF card can be configured at the same time. Although the logic in the two data path FPGAs is not exactly the same (e.g. the output check sum generation logic must differ) a standard technique is used that implements, in each FPGA, the super set of the required logic and provides a single ID pin via which a given FPGA can lean which one it is and thus function appropriately. In this way the same module of data path FPGA logic runs in both FPGA locations on an ADF card. All 80 ADF cards currently use the same data path FPGA logic. The data path FPGAs only need to be configured with their logic once after the power has been turned on. After TCC has configured the logic into the data path FPGAs on all 80 ADF cards then all of the control-status registers and memory blocks exist that TCC must program to operate the ADF system. Information that is held on the ADF cards that is critical to their Physics triggering operation is protected by making those programmable features "read only" during normal operation. TCC must explicitly unlock the write access to these features to change their control values. In this way no single failed or miss-addressed VME cycle can overwrite this critical data. Absolutely all data that TCC can write to the ADF cards can be, and routinely is, read back by TCC to verify the correct setup of ADF system. References: ----------- Calorimeter front-end electronics http://www-d0.fnal.gov/hardware/cal/calorimeter_electronics.htm ADF card block diagram http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_card_block_diagram.pdf or .ps ADF card picture http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/pictures/ adf2_front.jpg ADF Data Path FPGA block drawing http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ data_path_fpga_signal_processing.pdf or .ps for National Semiconductor Channel Link http://www.national.com/appinfo/lvds/files/channellink_design_guide.pdf Serial Command Link http://www.pa.msu.edu/hep/d0/l1/scl.html SCLD card http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/scld/ Wiener Series 6000 VME-64x Crate http://www.wiener-us.com/ Drawings and Pictures which could be included in this NIM paper: ---------------------------------------------------------------- ADF card picture ADF card block drawing ADF card Data Path FPGA block drawing