Minutes of Video Conference Tuesday, September 16, 1997, 3pm. MSU: Jim Linnemann, Dan Edmunds, Philippe Laurens UofM: Myron Campbell, Jerry Huang Jerry's presents recent test results on Magic Bus to Main Memory transfer based on logic analyzer traces: 1st transfer of 128 bits takes 8 PCI cycles (= 67 MB/s) 2 mixed writes to 2 different TB addresses takes 29 PCI cycles (37MB/s) 3 burst writes to same TB destination takes 12 PCI cycles (133MB/s) 4 burst writes to same TB destination takes 33 PCI cycles, including 3 retries on 4th write because the 21171 is not ready (64MB/s) [Jim's note: PCI cycles are 30 ns (ie 33 MHz), giving a nominal capacity of 8B/.03 usec = 267 MB/s = 267B/usec, not 320 MB/s as Jim had said in the past] Myron suggests that the next step is to watch the command bus between the 21171 and the alpha CPU. Another ides would be to repeat the test on the 21172. The 21172 is the chipset that will be used for all prototypes and what is used on the PC164. Another possibility was to try faster memory. Jim mentions that, at some point, we might want to call Tim Reddin who works in the High Performance Computing Group at Digital and offered to help answer questions and/or put us in contact with other experts. Jim will not be able to see either Tim Reddin or CERN's Alberto Guglielmi during his coming trip to Beaune. Myron suggests MSU could bring its PC164 (i.e. a stripped down Durango Workstation) to UofM to repeat the timing tests. Philippe will contact Jerry to arrange a one day visit and bring the board. Myron describes the status of the first prototype alpha board as being at the end of the layout stage so that routing can start. The schedule is still set for October but has slipped by at least two weeks lost on PCI connector problems. The design of the Magic Bus Programmed IO Port has not started, but is still planned with a windowing of Magic Bus address space onto PCI address space and thus onto alpha memory space. There is no new board documentation available at the moment. Jim points out that the magic bus documentation that was given to MSU is now outdated and does not match the schematics. There were some specific questions about some new lines. The MBLOAD was left over from Run I and goes away. Jim had noticed that the DSTROBE backplane pin doesn't seem to be connected to anything on the schematic and this is probably a bug that UofM will look into. Myron describes that the board will have 8 memory sockets and will accept 64 MB, 128MB... No further work has been done on interrupts with respect to FIFO_EMPTY and EVENT_DONE. Jim informs UofM of MSU's preference of having the user option to tie the interrupt to either an individual processor card or the set of all cards. Myron describes CDF method for restarting and downloading the processor crates. CDF has a VME SYSRESET fanout to all crates which causes a global reset. There will also be a front panel reset button on the alpha processor card. Jim asks about UofM experience of knowledge regarding debugging of a running processor. Myron mentions that after a hard crash with memory dump and processor halted, one can always read memory over the VME bus. An idea for attaching the debugger to a running system "on the fly" would be with a VME interrupt and an interrupt service routine on the alpha system to enable remote debugging. In general UofM is busy with hardware issues and MSU's help would be appreciated for such software and systems issues. Myron reports on the status of the 2 prototype Magic Bus backplanes. The boards are done, have been sent to Fermi to be stuffed, and are probably ready by now. Jim asks how CDF handles the purchase of the CDF VMEforPhysics crates. Myron answers they just call Preps. UofM does not have specifications to offer for power supplies: probably 300A of +5V and 50A of +3.3, the real limit being what the backplane can deliver. CDF hasn't reached a standard setup for cooling yet. In general there isn't a standard crate+PS+cooling package at CDF because every system has different needs. MSU/D0 should thus build their crates to their own specifications for the D0 Level 2. Myron describes the meaning of CDF_RESET as resetting of the front end buffers, but that it isn't clear what it translates to for the CDF L2 system. On the question of debugging and repair of alpha boards, Myron encourages MSU/D0 to try and solve their problems, and send the boards they can't fix to UofM. A cost figure for alpha boards is not currently available, but will be after the first prototypes are built. Jim asks about UofM understanding of PCI arbitration and any possible delay when the CPU decides it wants to, for example, write to the FRED lines while a Magic Bus transfer tries to update main memory. Jerry says that the PCI arbitration is round-robin, and that PCI specifies a maximum number of cycles where a source can hold the bus. The Magic Bus port has been designed to re-arbitrate before each new transfer. The 21172 (CPU-PCI Bridge) can always accept or reject a particular PCI transfer and force a retry. This might be a mechanism where the 21172 dictates that it needs the PCI bus. Answering this question goes beyond the current level of understanding.