17 Nov 1997 3-way video conference FNAL: Dan Owen UofM: Jerry Huang, Myron Campbell MSU: Dan Edmunds, Jim Linnemann, Philippe Laurens Jerry shows expected performance of the VME interface as predicted by the Universe Data Book: - There are two modes you can run the Universe chip; coupled mode vs decoupled mode. - VME Master coupled mode makes CPU wait for IO completion, slower, 5 MB/s decoupled mode (sometimes called posted write), faster, 22 or 32 MB/s depending on transfer size. - VME Slave coupled, 9.5MB/s decoupled, 76MB/s or 97 MB/s depending on burst size [Myron, later: only VME-32 actually implemented, not full VME64 For CDF readout mode, Tundra is not limiting performance Jim is inquiring whether CDF and D0 readout goes in the same mode] Jerry describes characteristics of the Programmed IO MB-PCI interface: - implemented in FPGA - bidirectional MB <-> PCI - two PCI windows mapped to MB - one MB window maps to PCI - MB->PCI is persistant (I think it means that it keeps trying until done) - PCI-> MB implements retry signal when MB is still busy after timeout. This is a PCI signal asserted by the MB-PCI interface and the 21172 will automatically retry without software intervention. - There was some discussion of bits 31:16 that I didn't completly get. I think the idea is that the address comparaison to determine if an address hits a particular window is typically done on the upper 16 bits, and that the low 16 bits are passed through as the offset within the window. PCI->MB Window A (some information missing here) - PCI address bits 31:16 selects the windows - trigger a MB transfer on the last PCI data transaction - read/write to 32 bit address if 32 bit PCI transfer, 64 bit if 64 bit PCI transfer - read/write to even/odd 32 bit address (i.e. bit #2) to reach both parts of the 64 bit data PCI->MB Window B - trigger on the last 32 bit part of the 128 MB - each 128 bit MB data is aligned at 128 bit PCI address - using four 32 bit words word0/1/2/3, triggers transfer on word 3 - trigger on word 2 if 64 bit transfer - set PCI RETRY signal within 16 PCI cycles after TRIG_MB if cannot acquire MB mastership. When such a PCI slave gives retry signal, 21172 will retry. No software retry necessary. software can still verify transfer happened. MB->PCI Window - currently only comparison on bits 31:16 is implemented - described by: MB lower bound, MB higher bound, PCI offset Question from Jim: What bandwidth on MB-PCI? Jerry: 5 MB/s (at least like coupled universe) Myron: probably pessimistic as MB faster than VME. Question from Jim: how to isolate the node from VME and MB access? Myron: probably doable to shut off MB interfaces and VME interfaces. There might be an enable state in some register, or one can de-program the windows. Jim: who owns the 21172? Intel or DEC? Myron: DEC still the one supporting 21172 Jim: documentation? Myron: we need to clean up Jim: cost, power? Myron: we are working on this now Jim: prototype 1 status? Myron: couple tries at routing, then start over, still trying. (later on we hear that this is done by undergraduates) Jim: MB backplane tests? Myron: no tests yet. have one backplane with a few of the connectors. Jim: memory space layout? Myron: part of documentation, not yet. Jim: word count associated with block transfer? Jerry,Myron: DMA engines increments address. CPU can read back the translation addresses buffers and deduce a word count by difference. Jim: interrupt generation? Myron: no new work Myron: prototype #1 will have tundra/Universe VME interface block transfer from MB 2*64 pci slots floppy port serial port Myron: what is the board count for DZero? Jim: cft + 2*muon + forward preshower + cal + global = 6 crates with typically 2 CPUs per crate Myron: routing done by undergrad now hired a full time secretary now have a full time technician/engineer jerry is also taking classes conclusion: still not back to full capacity of a year ago myron almost done with other commitments and ready to go back to the design (after lehman review). Myron: power supply needs +5V, +3.3V onboard converter generates +2 for CPU Myron: Can MSU help bringing first board to life when it shows up? This involves the Serial ROM and the Flash RAM firmware.