Minutes from phone conversation with Myron Campbell, Jan 27, 1998

Propose meeting on Feb 18 at FNAL or 19/20 video

Alpha Prototype:

postdoc working full time on layout.  Decided to make
first prototype include the MBus programmed I/O interface.
	won't include fast I/O port, just parallel port
Expect board at U of M March, MSU April.
Jerry Huang doing web documentation of programmed I/O
all U of M work so far is really 64bit PCI (IEEE standard) indep of alpha
may well go to 12 broadcast address bits from 8
	ASK at next meeting

MBus address range set at startup: PCI configuration space registers

MBus
	3 backplanes, 2 partially stuffed
	undergrad doing termination cards, avail before Alpha
	can monitor busy% by looking at BOSS
		BOSS must be idle before begin arbitration

Planning to use optical Cypress 320 Mb/s + fiber
	observed error rates less than g-link
		glink discouraged by HP; losing synch (all 0's)
		ECL/TTL converters needed

Programmed I/O 
	speed estimate: ask at meeting
	I/O arbitrates at each cycle
	64 and 128 bit modes

VME I/O
	
CDF, like D0, reads out by having an external master
take control of VME and read through Tundra as a slave.