FIC OPTIONS =========== Schedule/ construction/purchasing --------------------------------- January: board layout slot requested; 1-2 month cycle if delayed May/June 99 --test at FNAL? FIC questions: does master have to verify synch before startup? what does receiver emit during startup? need guaranteed spacing between events of 3 clock (byte) cycles for G-link Stateless vs IDLE/EVENT/ERROR states (same issue for SLIC, MBT) FINALIZE BY FNAL WORKSHOP (orders in mid-november) 64K FIFO? is this surely overkill for CPS, FPS? Is money worth difference? number of cards (10) fibers FIC cards @4/card count: 6 CFT = 2 4 CPS 1 6 FPS+CPS 2 stereo ---- 5 actual, 5 spare/test EXPECTS Fnal/Maryland to purchase transformers (is the datatronics good enough?) purchase crystals provide Cypress output design (balancing) choose connector, cable (say class 5 STP and RJ45 phone jack style connector) note: atlas' cable was quite special: running hi freq clock by sensitive analog front end electronics, strong EM interference specs made it hard G-link construction method -------------------------- * NOT interested in g-link layout * wants VTM or Finnisar boardlets VTM board option need to verify no dependence on any J3 backplane, just connector e.g. for synch (VRB output bus) in tracking crate VME very difficult for running operation (e.g. SCL_INIT) in L2 crate need shortened MBus verify it passes 21 characters, so we can use in any mode Finnisar (or FNAL substitute) single channel daughter board more expensive FIC: VME vs no VME ------------------ probably will have VME functionality, just for loadup/testing VME option fancier monitoring spec should really be in L2 crate so TCC/Admin can reach it scalers for errors now possible SCL Init request/ack via VME interrupt/register readback BIST via VME note: BIST CAN't be turned off by anything in-band, must be wire or VME or front panel NO VME ECL scalers LED for error BIST on front panel request SCL INIT by special character or trailer no handshake to verify if reframe successful FIC communication requirements ------------------------------ MUST be able to provoke stream of G-link pads (up to 12msec) to resynch - generate busy (before next event, else SCL_INIT) - or SCL_INIT (directly, or indirectly) eg: insert end event chars on loss of lock, may generate sync error - maybe also reframe_ok signal? G-link has error output and has (much rarer?) illegal character error means need to reframe Reframing: special character: nasty, since no guarantee talking to a Master MBT same issues with SLIC! could equip all MBT's with SCL Mezanine and then enable/disable the other pieces busy request (for reframing) most sense for FIC, since some chance to slide in between events, tho no chance to resynch before next event: ONLY makes sense if can succeed without a SCL_INITIALIZE 1) send end event so receiver sees a bad, but not mismatched, event 2) send busy_request 3) start reframing 4) tickle counter/ light LED 5) when resynch complete, send free_request 6) may have to add free_request to end of event, and/or complicate the state machine However, SCL_INITIALIZE will go to SLIC by VME Communication paths: synch OK probably only by first 2 choices, since synch not ok might make transmission fail wire VME (interrupt, read, download) trailer special character internal: just a timeout question: how long must L2 subsystem wait after SCL_INTIALIZE until can guarantee no more input? transport trailer: if don't recover bad bytes, there is basically no hope for alpha to analyze the event--far too hard to reset byte boundaries BUt could recognize that shouldn't pull scl_init because known problem if try to recover, have hazardous data, so should have a trailer to warn, or other mechanism (such as MBus open collector line) hard for FIC, easier for SLIC, not so easy for MBT L2 Special characters (which don't go into FIFO) --------------------- end event null (must recognize as special case for cypress to ignore) start event: only if decide on statefulness other candidates busy/free probably only for FIC (stimulating resynch between evts) only the fic has a "realtime" data source without buffered outputs, so busy may well help init_ok ? probably, VME is better!? multiple types of end_event to signal error conditions an alternative to transport trailer or, transport trailer has defined fields for each board on path 16 B, not 16B at each hop Cypress ======= pad characters during message allowed, must be ignored Muon protocol: Only begin/end event defined BIST request is done via VME currently, receiver just does for a fixed length of time resynch only on scl_init, and power-up back path?? request scl_init on any single error (!) but only during data--separate states for event/gap, separate counters their claim is 4 cycles to resynch the cypress (claim, or spec??) CLAIM CYPRESS HAS ONLY 75 ohm layout examples, no STP??? this is curious, as there are app notes specifically on copper and long cables... no balanced 120 ohm STP? Cypress kinks: last pad character in a string has READY, thus pad must be actively avoided. G-link ====== pad characters during message allowed, must be ignored multiple null characters (have to pick right one for re-synch) F1? 2 consecutive errors puts in reframe request (can indeed make it want reframe) will take order 10 ms to reframe then much larger than interevent gap--scl_init, or busy 4 bit encoding field control characters have 2 bits fewer than Data characters D7/8 or 9/10 are defined 2-frame mode: (not in FLAGSEL) flag toggled by transmitter allows detection of all single-bit errors in C field The 4-bit C field conveys: inverted or not 1b generated internal to Xmit data, fill0, fill1, control 2b DAV, CAV, FF flag (or toggle) 1b FLGSEL settings to interpret the bitstream: 16/20 (M20SEL) flag vs toggle (MDFSEL) frequency range (DIV0,DIV1: 2 bits) errors detected: if 16 or 20, all single-bit errors in C field, but NO errors in D field except for control characters, which have defined values of 2 D bits 20 b frames ----------- 4 bit coding field 16b data 2-frame mode (extra error checking by strict alt of bits) 17b data using this as extra flag bit 24 b frames 20 or 21b data control: 4 characters fewer? no std definitions of control characters ctl chars not used by CDF JFR: claims only a FEW characters invalid (weaker error detection?) so cannot see parity errors very often thus no reason for a physical transport trailer also, does not want to make the extra logic to create one front panel: error light, clearable?