L2 Framework Initialization --------------------------- Orig: 24-FEB-2000 Rev: 16-JUN-2000 This document describes how to set up the L2 Framework @ Initialization Time, for normal physics running (not testing). Elements which must be set up: - TTS - FOM++ - FM D_Latches (3 cards) - L1 ST Fired TRM's (2 cards) - L2 Answer TRM's (2 cards) - L2 Auxi TRM - L2 Spec Trig Accept AONM's (2 cards) - L2 Spec Trig Reject AONM's (2 cards) - L2 Geo Sect Accept FOM's (2 cards) - L2 Geo Sect Reject AONM's (2 cards) - L2 Busy Answer Detect (2 cards) - L2 Helper FPGA How to program these things: (1) TTS Program BSF as described in BSF setup document Only Chips 15 and 16 are used on this card Chip 15 provides Current Tick/Turn # Chip 16 provides L1 Accept Tick/Turn # Reg Data Comment --- ---- ------- 0 0x0000 No interrupts from this chip 2 0x0000 No Scalers enabled for TS Reset (this is different from %RIO%\tts_setup.rii, because we currently (?) use the L1 Helper FPGA to reset these scalers, rather than the SCL Initialize) 3 0x0000 No Scalers held in reset 8 0x0000 (15) No FIFO Error Checking (for Current TTN) ****** (16) Write 0x0003, then 0x0203, then 0x0003 again to set up FIFO Error Checking for L1 Accept TTN and clear any latched errors 12 0x0000 (15) Tick/Turn Number sent to output 0x0001 (16) TTN muxed with FIFOed TTN sent to output 16 0x0000 (15) output is Current TTN (i.e. no delay on Turn Marker) 0x0001 (16) output is L1 Accept TTN (i.e. delay Turn Marker) 25 0x8004 HSRO enabled, generate 4 16 bit data words 32 0x0004 Program BXHSR delay (2) FOM++ BSF programmed according to BSF setup document see note of 26 Jan 2000 for MSA FPGA's (3) FM D_Latches BSF's programmed according to BSF setup document (recall that the M123 BSF's are programmed differently from the M122 BSF's) MSA's programmed as follows: Reg Data Comment --- ---- ------- 0 0x0000 No interrupts from this chip 2 0x0000 No scaler channels enabled for Timing Signal Reset 3 0x0000 No scaler channels held in reset (4) All TRM's BSF's programmed according to BSF setup document. MSA's programmed according to TRM Initialize mail message of 16 Feb (also on web). The VME FPGA for all L2 TRM's must be programmed differently from the default values. The differences are as follows: Reg Data Comment --- ---- ------- 8 0xfffe Enable Chip Status from FPGA's 15:1 to generate interrupt 9 0x0001 Enable Chip Status from FPGA 16 to generate interrupt Note that the default programming of these VME FPGA's does not allow the VME Interrupt to propagate on the P1 Backplane. This is the behavior desired for these FPGA's, the interrupt request only goes to the BSF FPGA to indicate FIFO Not Empty. (5) AONM's and FOM's The BSF for these cards is programmed like L1 AONM/FOM BSF's. At initialize time, the MSA's should be programmed mostly like L1 FW AONM's. The only difference is that the "benign" lookup array programming is different. It is not 100% clear what "benign" lookup array programming is, but it may be something like "require all inputs HIGH." All of the ancillary programming (BXHSR depth, interrupts, etc) should look exactly like L1 AONM/FOM's. For each Specific Trigger allocated by COOR: Corresponding L2 Accept AONM channel must be programmed to require corresponding L1 ST Fired (entering on lower 64 MSA's) and corresponding L2 Global Answer (entering on upper 64 MSA's) i.e. MSA_Out(x) = MSA_In(x) AND MSA_In(64 + x) Corresponding L2 Reject AONM channel must be programmed to require corresponding L1 ST Fired (entering on lower 64 MSA's) and veto on corresponding L2 Global Answer (entering on upper 64 MSA's) i.e. MSA_Out(x) = MSA_In(x) AND NOT MSA_In(64 + x) For each Geographic Section allocated by COOR The Accept/Reject FOM's are programmed EXACTLY like L1 FOM's But note that Geo Sect 127 should be programmed with the OR of all allocated Specific Triggers. It is not clear to me whether COOR sends an explicit message to request this or if that action is implicit in TCC (6) L2 Busy Answer Detect The BSF is, as usual, programmed according to the BSF setup doc At initialize time, the 16 MSA FPGA's on each L2_BAD card are programmed as follows: Reg Data Comment --- ---- ------- 0 0x0000 No interrupts from this chip 8 0x0000 L2 Busy(15:0) Control LSW 9 0x0000 L2 Busy(31:16) Control MSW 12 0x0000 . 13 0x0000 . 16 0x0000 . 17 0x0000 . 20 0x0000 . 21 0x0000 L2 Busy(63:48) Control MSW 26 0x0000 Do Not force output to any state 152 0x0000 MSA FPGA #1 (scalers service ST 3:0 / 67:64) 0x0001 MSA FPGA #2 (scalers service ST 7:4 / 71:68) . . . . . . 0x000f MSA FPGA #16 (scalers service ST 63:60 / 127:124) For each Geographic Section allocated by COOR, the corresponding Front-End Busy signal must be enabled to cause the L2 Busy Answer Delay. See the L2 BAD FPGA documentation (under the AONM directory) on the web for details. (7) L2 Helper FPGA This card has no BSF. The L2 Helper is in MSA FPGA #4: Reg Data Comment --- ---- ------- 0 0x0000 No interrupts from this chip 16 0x0000 State engine in "normal" mode 0x0001 Program this value when there is no L2 Global --> also pulse bit 15 of this register HIGH then LOW at end of initialization, to force L2 FW Helper to reset to quiescent state 18 0x0000 L2 Answer Strobe sourced by L2 Global