Blackboard notes from 13-JUN-1997 --------------------------------- Dan and Jim expressed support for the current idea of a commissioning plan where phase #1 has only one event in the L2 system at one time (no overlap of event transfer/analysis/readout). To avoid backing up the Level 1 buffers, this involve controlling the Level 1 rate: 1 l1 rate smooth and below ------------------ l2 processing time Admin ----- - Assign Buffer - Wait for Acknowldege - Kick Magic Bus Source Card - Wait for Answer from Worker - Tell L2 HW FW the Answer - Answer is yes: manage the VBD readout and wait for completion Answer is no: no readout action necessary - Read SCL (wait to receive the SCL message about L2 Decision about this event) - Check - Worker had corect Event Number - all Preproc match and match SCL L1 Number - SCL L2 Decision match L2 Global Decision Worker ------ - Receive Buffer assignement - Clean/Prepare this buffer - Tell admin buffer is ready to go - Wait for buffer to fill (Check flag set by Interrupt Service Routine) - Check all pieces fit together - Analysis loop - Event Passed: prepare Readout Event Failed: nothing - Send answer to admin - Wait for buffer assignment "Pre-allocating buffers" Up until now, we had been saying the word "pre-allocating", because we all had a clear sense of this concept being a desirable feature for supporting maximum performance and overlap of event analysis and event transfer over the Magic Bus. However (until now) all proposed schemes were (in my mind) only "working hard to stay ahead" but not automatic/inherent pre-allocation. "Allocating a Buffer" actually means: --------------------- Programming the DMA Mapper Slot #n [n=0..15] to point to Main Memory Buffer #k. Where "n" is the known sequential Magic Bus Event ID that will accompany the event on the Magic Bus. There are actually several (up to 15) event source IDs that need to be programmed for each and every event, including this event #n. Each event source ID will point to a sub-portion of the Main Memory Buffer #k. The management of Main Memory Buffer Slots is done by the Administrator because: - The Admin collects the answer(s) from the Worker(s) and communicates with the L1/L2 FW to decide whether the event should pass/fail. The Admin thus knows whether a particular Buffer should be saved for readout or may be recycled immediately. - The Admin controls the VBD and Event readout. The Admin thus knows when a readout buffer is no longer in use. - The Admin needs to know exactly which event buffer was used by the worker so that it can build the correct list in Short IO VME space of segment start and length for the VBD to readout. - The Admin may want to directly access some information in the event buffer over VME before or after event readout (for building Monitoring information or for cross-checking). In order to fully/automatically pre-allocate buffer slots, the idea is that the Admin needs to talk to the Worker(s) not about the destination of the next event (or near future) that is about to be transferred, but tell the Worker(s) which Main Memory Buffer Slot to switch to as soon as the next (or near future) event has been transferred. The Interrupt Service Routine that is called at the end of an event transfer can then automatically switch a buffer slot (1) to point away from the precious event data just transferred and (2) to already point to an already free memory slot. The important point is that the knowledge of which slot should now be pointed to no longer depends on any additional past or future communication between the Admin and the Worker. The next buffer was pre-allocated in advance, and this is an important point because an interrupt service routine cannot be used to wait for some event to happen (like the Admin writing a message over the Magic Bus to some communication area in the Worker's Main Memory). This scheme will have the side effect of increasing the necessary total number of event/processing slots in the buffer pool. I was NOT seeing the full picture last week, and this is still similar to the "working hard to stay ahead" method because we still have to communicate information about future slot(s) "at some point in time". The next observation is that WE KNOW that there are only 16 event slots in the Front-Ends for "Event awaiting L2 decision". This means that the Level 2 system can while it is working on one event have at most 15 other events waiting to be processed. Even if the input queue was empty before starting the analysis of a particular event, and if the analysis of this event takes a long time, the system will only receive a maximum of only 15 more events while it is working on this one event. This means that the DMA Mapper slot that received the event that is being worked on now CANNOT POSSIBLY be active again until this event is analysed and the answer sent back to the L2 FW. So there is a natural and safe place in the event loop where the Admin can communicate to the Worker and pre-allocate buffer slots. By nature, while a particular event is being worked on: - The Magic Bus Event ID and corresponding DMA Buffer Slots that were used to transport this event are inactive. - This same DMA Buffer Slot is already pointing to the Main Memory Buffer Slot that will be used for the next event with the same Magic Bus Event ID. This was accomplished by the ISR and pre-allocation. - The Admin can NOW tell the Worker(s) what Main Memory Buffer Slot to switch to, once the NEXT event with this same Magic Bus Event ID has been transferred. Parenthesis: Dan has pointed out before that the number of buffer in use might be greater than 16 because we might have a number of events awaiting transfer to Level 3. It now looks to me that this observation about the maximum number of input buffer in use can by itself prove that we don't need to pre-allocate at all and still AUTOMATICALLY stay ahead by 0..15 slots if we reset the DMA Mapper Slot before analysing the event that came on that slot. It may still be an interesting idea for the second advantage listed earlier; i.e. immediately point away from the slot where an event was just transferred.