Blackboard Notes from 18-JUN-1997 meeting 
present: Jim, Dan E., Philippe + Dan O. on Video Link

Buffer Slot Data types (quick tour)
----------------------

- Event Input Data
    from all L2 PP sources

- Analysis Workspace
    - L2 Trigger Mask(s)
    - Tool space
    - Frame space
    - Readout space
        data
        length for Admin/VBD Short IO space 

- Monitoring
    - event processing state flags
    - starting time for different phases/tasks

- Messages
    - Tool messages: error/warning/info
    - Frame messages

Main Memory Buffer Slot Control Structure
-----------------------------------------

- Indexed by Main Memory Buffer Number (we need order of 40 such buffer 
slots)

- Structure Content
    - Base Addresses
        - MBus Data Sources
        - pointer All other pieces part of this buffer

    - Event State Flags
        - Filled (but not processaed)
        - Finished processing
        - Assigned to be re-filled (i.e. allocated)
            (buffer already to or about to be pointed to)
        - Event held for readout
        - Event holds a MFP
        - MMA (whatever that meant???)
        - Event passed/failed

    - Buffer Linkage 
        - Main memory slot number to switch to after the event 
            in this slot is received (index or pointer)
        (this might be useful, but the *main* home and the source for 
this
        information is in the structure below.)

Mapper Slot Control Structure
-----------------------------

- Writable over MBus by Admin. 

- Used by Interrupt Service Routine (=ISR)
    (this is a separate structure for direct/easy access  by ISR)

- Indexed by Mapper Slot Number (0:15) i.e. MBus Event ID Number

- Structure Content
    - Main Memory Buffer Slot Destination
        - Main Mem Slot to receive next event for this Mapper Slot
        - Main Mem Slot to switch to after this event is received
        (Proposal: Admin is the only one in charge of updating this 
area?)
    - Cyclic (0:15) Counter of next/current MBus event ID to be 
transferred
        over the Magic Bus
        (updated by ISR)



Buffer Control state diagram
-----------------------------

Data structures associated with input buffer management     18 June 1997

Mapper data structure:

NinUse  <=16
NextEventInMapperSlot 0-15      
{CurrentBuffer(0:15),NextBuffer(0:15)}  table


Buffer management structure:
----------------------------
NBuffers   about 40 = 16mapped + 16preassigned or filled + 8 L3readout
NextBuffer    <=NBuffers    next buffer to examine for Filled event

{BaseAddress{port,buffer},state{buffer},Passed{buffer},MarkPass{buffer},other?}

    where port is 0:15, buffer is 0:NBuffers

    BaseAddress may be just computed instead of looked up?

Counters?
Nallocated,Nfilled,Nprocessed :Worker and Administrator, or just Admin?
    NL3Readout,Nexamining,Nfree :Administrator only 

Buffer state numbers:
    Worker      Admin
0               Free
1   Allocated   Allocated
2   Filled      Filled
3   Processing  Processing?
4   Processed   Processed
5               L3 Readout
6               Examining