Suggested Milestones for Level 2 [these should be Level 3 milestones, internal to D0, except for the "done commissioning", as the design is not sufficienty finalized to justify a frozen set of milestones at this point. We may still chose to implement in a different order than envisioned in this schedule] 1. Global and Cal TDR complete: June 2, 1997 2. V1.0 of Global frame in non-VME prototype at MSU August 1, 1997 depends on delivery of PC164 processor card from Digital [March] prototype PCI cards from U of M: [August] PCI to VME PCI to Magic bus (less so) goals: demonstrate downloading of .exe demonstrate downloading of binary DATA file if possible else TCC able to write Alpha memory run barest version of tool frame program TCC able to read Alpha memory and send interrupt to Alpha run at MSU self-test of PCI DMA interface 3. V2.0 of Global Frame in VME prototype at MSU March 9, 1998 depends on delivery of VME alpha with integrated PCI cards [December] VME for Physics Crate with Magic Bus [December] Hotlink/MBus receiver card (MSU) [September] State registers for monitoring [December] goals: repeat of above tests in new card run V1 of Master program for Global run V2 of Frame program for Global run V1 of Master program for Cal run V1 of em and jet program for Cal run V1 Master and V2 Frame for Global on 2 separate nodes Run self-test of Hotlink/MBus receiver through DMA to Alpha memory 4. verify timing estimates in nodes May 1, 1998 run V1 Cal master and V1 em and/or jet in 2 separate nodes run and time realistic Global master/ worker in 2 separate nodes 5. Communication between Cal and Global at MSU August 26, 1998 depends on delivery of 4 VME version cards total [June 98] 2 VME for Physics crates [Dec 97?] Hotlink driver card [May 98] Hotlink/Magic Bus receiver card [September 97] communicate between 2 crates, each with master and worker Cal and Global master/2 workers test not visible milestone Oct 7, 1998 run Cal master + jet and em workers 5. Commissioning of Cal/Global L2 Complete March 29, 1999