1. Does the VBD ever give up the bus between DMA blocks?  It is possible
   that it only gives up the bus in CD mode.  Dean says "very likely not",
   i.e. very likely it does not give up the bus.   1.16 msec makes sence
   i.e.   2843 longwords --> 410 nsec per longwork  minus setting up 14
   blocks.

2. Buffers must go before the slowest part of the chain of steps.  Our
   2.71 msec is our slowest link.   1/2.71 msec is 369 Hz and we are running
   357 Hz.

3. Double the number of COMINT's

      2.71 msec/2 = 1.35 msec             time for two COMINT's in parallel
      1.16 msec + 0.2 msec = 1.36 mesc    VBD DMA time plus minimum VTC time
                                             stop building jet lists in VTC

4. Garbage collection.  The vertical reads now take about 900 usec.
   Can this be fit into the 1.35 msec.  Must have access via VME backplane
   to the master Vertical Interface module at the same time as the VBD is
   using the VME backplane.   Separate VME bus and CPU??  Separate crate
   and backplane and CPU and everything?

   Some Vertical Data is part of the L1 block e.g. the absolute time stamp.
   Some of the vertical data is not part of the L1 block, e.g. pulser data.

5. Modes of VBD operation.  Is muon mode just the Calo mode without the
   Word Count words being stuck into the Data Stream by the VBD?


6.  When does the MVME-133A-20  Time-out a bus cycle ??

    Page 35.   There are 3 sources of bus error exceptions on the MVME-133A.
    They are:  Local Bus Time-out (LTO),  Qualified VMEbus BERR* signal
    QVBERR*,  and RMW-LOCK.

    Local bus time-out ocurs whenever an MPU access does not complete
    within 13 to 15 msec.   If the system is configured properly then this
    sould only happen if:   software tells the MPU to access a non-existant
    location within the onboard range,  or something prevents this module
    from becoming the VMEbus master.

    Qualified VMEbus BERR*,  QVBERR*,  ocurs when the MVME133A is bus master
    and the BERR* signal is active.

    page 42   MVME133A  System Controller  Global Bus Time-Out    If the
    MVME133A is the system controller and if it detects the activation of
    DS0* and or DS1* for longer than the time-out period of 50 usec or
    57 usec then it drives BERR* low to complete the cycle.