*********************** * * * CALORIMETER TRIGGER * * TIMING FLOW * * * *********************** 10-JAN-1992 15-JAN-1992 GENERAL INFORMATION ------------------- This document describes the signal flow through the Calorimeter Trigger, for each logical tree. The minimum propagation delay through each Calorimeter Trigger processing element, including cable delays, is compared to the current (CTROM1B, CTROM2A, CTROM3A, CTROM4A) Calorimeter Trigger MTG PROMs, and the IML Clock generated on the Framework MTG. The purpose of this file is to verify that the MTG PROMs are compatible with the correct operation of the Calorimeter Trigger. Additionally, this file will drive the next generation of Calorimeter Trigger MTG PROMs, which will correct any deficiencies of the current PROMs, as well as improving the safety margins of critical timing paths. ------------------------------------------------------------------------------------------------------------------------ EM Et COUNTER TREE TIMING | JAN 91 MTG PROM | JAN 92 MTG PROM | MIMIMUM PROM | ------------------------------------------------------------------------------------------------------------------------ _ _ | | | | CTFE ADC CLOCK |_ --> CTFE 74F399 CLOCK |_ | 4 ticks | 5 ticks | 5 ticks | | | | | receive TSS-H: 10H125 4 ns | | | | buffer TSS-H: 74ALS541 14 ns | | | | delay TSS-H: BEL DELAY 0-110 ns | | | | A-D conversion: 10319 20 ns | | | | -------- | | | | 38-148 ns | 150 ns | 187.5 ns | 187.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE 74F399 CLOCK |_ --> CTFE LUM REG CLK _| | 2 ticks | 3 ticks | 3 ticks | | | | | receive TSS-B: 10H125 4 ns | | | | buffer TSS-B: 74ALS540 12 ns | | | | mask by CSR bit: 74AS32 6 ns | | | | buffer masked signal: 74ALS540 12 ns | | | | mask by CSR bit: 74AS08 6 ns | | | | latch ADC output: 74F399 9 ns | | | | lookup Add>Clock: CY7C245A-25 25 ns | | | | ----- | | | | 74 ns | 75 ns | 112.5 ns | 112.5 ns | (note: this only works because we can | | | | really subtract 18 ns processing | | | | time on LUM REG CLK, but is flaky) | | | | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE LUM REG CLK _| --> CTFE CMP LTCH CLK _| | 4 ticks | 3 ticks | 3 ticks | | | | | receive TSS-G: 10H125 4 ns | | | | buffer TSS-G: 74ALS541 14 ns | | | | lookup Clock>Data: CY7C245A-25 15 ns | | | | comparator: 74LS684 30 ns | | | | PAL Input>Clock: PALCE22V10-25 10 ns | | | | ----- | | | | 73 ns | 150 ns | 112.5 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE CMP LTCH CLK _| --> CHTCR INPUT HOLD |_ | 7 ticks | 6 ticks | 3 ticks | | | | | receive TSS-F,G: 10H125 4 ns | | | | buffer TSS-F,G: 74ALS541 14 ns | | | | make TSS-F * TSS-G: 74AS08 6 ns | | | | PAL Clock>Output: PALCE22V10-25 10 ns | | | | travel time: Backplane 5 ns | | | | ----- | | | | 39 ns | 262.5 ns | 225 ns | 112.5 ns | (note: the CHTCR input latches go | | | | transparent after 4 ticks, and | | | | hold 3 ticks later. The | | | | comparator outputs reach | | | | the CHTCR before the latches | | | | become transparent) | | | | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CHTCR INPUT HOLD |_ --> T2 COUNTER CAT CLK _| | 3 ticks | 8 ticks | 4 ticks | | | | | receive TSS-D: 10H125 4 ns | | | | buffer TSS-D: 74ALS541 14 ns | | | | latch CHTCR input: 74AS573 12 ns | | | | 1st stage PROMs: AM27S185 35 ns | | | | 2nd stage PROMs: N82HS321 30 ns | | | | output drivers: 10H124 2 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 127 ns | 112.5 ns | 300 ns | 150 ns | (note: this works because the CHTCR | | | | input latches are transparent, | | | | but is flaky) | | | | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T2 COUNTER CAT CLK _| --> T3 COUNTER CAT CLK _| | 3 ticks | 6 ticks | 3 ticks | | | | | CAT2 Clock -> Partial Sum: 34 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 64 ns | 112.5 ns | 225 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (a) T3 COUNTER CAT CLK _| --> IMLRO LATCH _| | 17 ticks | 9 ticks | 11 ticks | | | | | CAT2 Clock -> Final Sum: 45 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 75 ns | 637.5 ns | 337.5 ns | 412.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b) T3 COUNTER CAT CLK _| --> IML LATCH _| | 17 ticks | 9 ticks | ??? 11 ticks | | | | | CAT2 Clock -> Comparators: 42 ns | | | | travel time: Cable 50 ns | | | | ----- | | | | 92 ns | 637.5 ns | 337.5 ns | 412.5 ns ??? | | | | | ------------------------------------------------------------------------------------------------------------------------ Total Et COUNTER TREE TIMING | JAN 91 MTG PROM | JAN 92 MTG PROM | MINIMUM PROM | ------------------------------------------------------------------------------------------------------------------------ _ _ | | | | CTFE ADC CLOCK |_ --> CTFE 74F399 CLOCK |_ | 4 ticks | 5 ticks | 5 ticks | | | | | (SAME AS EM COUNTER) 38-148 ns | 150 ns | 187.5 ns | 187.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE 74F399 CLOCK |_ --> CTFE LUM REG CLK _| | 2 ticks | 3 ticks | 3 ticks | | | | | (SAME AS EM COUNTER) 74 ns | 75 ns | 112.5 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE LUM REG CLK _| --> TOT ADDER LCH CLK _| | 4 ticks | 3 ticks | 3 ticks | | | | | receive TSS-G: 10H125 4 ns | | | | buffer TSS-G: 74ALS541 14 ns | | | | lookup Clock>Data: CY7C245A-25 15 ns | | | | adder: 2 x 74F283 20 ns | | | | ----- | | | | 53 ns | 187.5 ns | 150 ns | 150 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE TOT ADDR LTC CLK _| --> CHTCR IN HOLD |_ | 7 ticks | 6 ticks | 3 ticks | | | | | receive TSS-F,G: 10H125 4 ns | | | | buffer TSS-F,G: 74ALS541 14 ns | | | | make TSS-F * TSS-G: 74AS08 6 ns | | | | Adder latch Clock>Out: 74AS821 11 ns | | | | Comparator: 74LS684 30 ns | | | | PAL Input>Output: PALCE22V10-25 25 ns | | | | travel time: Backplane 5 ns | | | | ----- | | | | 95 ns | 262.5 ns | 225 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CHTCR INPUT HOLD |_ --> T2 COUNTER CAT CLK _| | 3 ticks | 8 ticks | 4 ticks | | | | | (SAME AS EM COUNTER) 127 ns | 112.5 ns | 300 ns | 150 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T2 COUNTER CAT CLK _| --> T3 COUNTER CAT CLK _| | 3 ticks | 6 ticks | 3 ticks | | | | | (SAME AS EM COUNTER) 64 ns | 112.5 ns | 225 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (a) T3 COUNTER CAT CLK _| --> IMLRO LATCH _| | 17 ticks | 9 ticks | 11 ticks | | | | | (SAME AS EM COUNTER) 75 ns | 637.5 ns | 337.5 ns | 412.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b) T3 COUNTER CAT CLK _| --> IML LATCH _| | 17 ticks | 9 ticks | ??? 11 ticks | | | | | (SAME AS EM COUNTER) 92 ns | 637.5 ns | 337.5 ns | 412.5 ns ??? | | | | | ------------------------------------------------------------------------------------------------------------------------ Energy ADDER TREE TIMING: First Lookup | JAN 91 MTG PROM | JAN 92 MTG PROM | MINIMUM PROM | ------------------------------------------------------------------------------------------------------------------------ _ _ | | | | CTFE ADC CLOCK |_ --> CTFE 74F399 CLOCK |_ | 4 ticks | 5 ticks | 5 ticks | | | | | (SAME AS EM COUNTER) 38-148 ns | 150 ns | 187.5 ns | 187.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE 74F399 CLOCK |_ --> CTFE LUM REG CLK _| | 2 ticks | 3 ticks | 3 ticks | | | | | (SAME AS EM COUNTER) 74 ns | 75 ns | 112.5 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE LUM REG CLK _| --> T1 ENERGY CAT CLK _| | 7 ticks | 6 ticks | 4 ticks | | | | | receive TSS-G: 10H125 4 ns | | | | buffer TSS-G: 74ALS541 14 ns | | | | lookup Clock>Data: CY7C245A-25 15 ns | | | | 1st Adder: 2 x 74F283 20 ns | | | | 2nd Adder: 3 x 74F283 29 ns | | | | output driver: 10H124 2 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 114 ns | 262.5 ns | 225 ns | 150 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T1 ENERGY CAT CLK _| --> T2 ENERGY CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | CAT2 Clock > Partial Sum: 34 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T2 ENERGY CAT CLK _| --> T3 ENERGY CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS EM COUNTER) 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (a) T3 ENERGY CAT CLK _| --> IMLRO LATCH CLK _| | 21 ticks | 18 ticks | 14 ticks | | | | | CAT3 Clock > Final Sum: 50 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 80 ns | 787.5 ns | 675 ns | 525 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (c) T3 ENERGY CAT CLK _| --> IML LATCH CLK _| | 21 ticks | 18 ticks | ??? 14 ticks | | | | | CAT3 Clock > Comparators: 50 ns | | | | travel time: Cable 50 ns | | | | ----- | | | | 100 ns | 787.5 ns | 675 ns | 525 ns ??? | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b) T3 ENERGY CAT CLK _| --> T4 TOTAL CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | CAT3 Clock > Final Sum: 50 ns | | | | travel time: Cable 15 ns | | | | ----- | | | | 65 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b') T4 TOTAL CAT CLK _| --> IMLRO LATCH CLK _| | 18 ticks | 14 ticks | 11 ticks | | | | | CAT3 Clock > Partial Sum: 39 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 69 ns | 675 ns | 525 ns | 412.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b'') T4 TOTAL CAT CLK _| --> IML LATCH CLK _| | 18 ticks | 14 ticks | ??? 11 ticks | | | | | CAT3 Clock > Comparator: 50 ns | | | | travel time: Cable 50 ns | | | | ----- | | | | 100 ns | 675 ns | 525 ns | 412.5 ns | | | | | ------------------------------------------------------------------------------------------------------------------------ Energy ADDER TREE TIMING: Second Lookup | JAN 91 MTG PROM | JAN 92 MTG PROM | MINIMUM PROM | ------------------------------------------------------------------------------------------------------------------------ _ _ | | | | CTFE ADC CLOCK |_ --> CTFE 74F399 CLOCK |_ | 4 ticks | 5 ticks | 5 ticks | | | | | (SAME AS EM COUNTER) 38-148 ns | 150 ns | 187.5 ns | 187.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ _ | | | | CTFE 74F399 CLOCK |_ --> CTFE EGR PAGE SEL _X_ | 7 ticks | 6 ticks | 4 ticks | | | | | time to complete 1LU: CTFE 112.5 ns | | | | address hold: CY7C245A 0 ns | | | | ----- | | | | 112.5 ns | 262.5 ns | 225 ns | 150 ns | (note: if 1st LU timing is changed, | | | | this timing must be adjusted) | | | | |--------------------|--------------------|--------------------| _ _ _ | | | | CTFE ENERGY PAGE SEL _X_ --> CTFE LUM REG CLK _| | 3 ticks | 4 ticks | 6 ticks | | | | | receive TSS-(pg sel): 10H125 4 ns | | | | buffer TSS-(pg sel): 74ALS541 14 ns | | | | lookup Clock>Data: CY7C245A-25 15 ns | | | | ----- | | | | 43 ns | 112.5 ns | 150 ns | 225 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE LUM REG CLK _| --> T1 ENERGY CAT CLK _| | 3 ticks | 4 ticks | 4 ticks | | | | | (SAME AS 1st LOOKUP) 114 ns | 112.5 ns | 150 ns | 150 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T1 ENERGY CAT CLK _| --> T2 ENERGY CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS 1st LOOKUP) 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T2 ENERGY CAT CLK _| --> T3 ENERGY CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS 1st LOOKUP) 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (a) T3 ENERGY CAT CLK _| --> IMLRO LATCH CLK _| | 17 ticks | 13 ticks | 7 ticks | | | | | (SAME AS 1st LOOKUP) 80 ns | 637.5 ns | 487.5 ns | 262.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (c) T3 ENERGY CAT CLK _| --> IML LATCH CLK _| | 17 ticks | 13 ticks | 7 ticks | | | | | (SAME AS 1st LOOKUP) 100 ns | 637.5 ns | 487.5 ns | 262.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b) T3 ENERGY CAT CLK _| --> T4 TOTAL CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS 1st LOOKUP) 65 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b') T4 TOTAL CAT CLK _| --> IMLRO LATCH CLK _| | 14 ticks | 9 ticks | 4 ticks | | | | | (SAME AS 1st LOOKUP) 69 ns | 525 ns | 337.5 ns | 150 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b'') T4 TOTAL CAT CLK _| --> IML LATCH CLK _| | 14 ticks | 9 ticks | 4 ticks | | | | | (SAME AS 1st LOOKUP) 100 ns | 525 ns | 337.5 ns | 150 ns | | | | | ------------------------------------------------------------------------------------------------------------------------ Momentum ADDER TREE TIMING | JAN 91 MTG PROM | JAN 92 MTG PROM | MINIMUM PROM | ------------------------------------------------------------------------------------------------------------------------ _ _ | | | | CTFE ADC CLOCK |_ --> CTFE 74F399 CLOCK |_ | 4 ticks | 5 ticks | 5 ticks | | | | | (SAME AS EM COUNTER) 38-148 ns | 150 ns | 187.5 ns | 187.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | CTFE 74F399 CLOCK |_ --> T1 MOM CAT CLK _| | 9 ticks | 9 ticks | 6 ticks | | | | | receive TSS-B: 10H125 4 ns | | | | buffer TSS-B: 74ALS540 12 ns | | | | mask by CSR bit: 74AS32 6 ns | | | | buffer masked signal: 74ALS540 12 ns | | | | mask by CSR bit: 74AS08 6 ns | | | | latch ADC output: 74F399 9 ns | | | | Add EM + HD: 2 x 74F283 20 ns | | | | Lookup Addr>Data: CY7C291A-35 35 ns | | | | 1st Adder: 2 x 74F283 20 ns | | | | 2nd Adder: 3 x 74F283 29 ns | | | | driver: 10H124 4 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 187 ns | 337.5 ns | 337.5 ns | 225 ns | (note: if 2 Momentum lookups are used | | | | the T1 MOM CAT CLK must occur | | | | before the MOMENTUM PAGE SEL | | | | bits change. The current CTMTG | | | | PROMs do not do this) | | | | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T1 MOM CAT CLK _| --> T2 MOM CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS 1st LOOKUP) 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | T2 MOM CAT CLK _| --> T3 MOM CAT CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | (SAME AS 1st LOOKUP) 64 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (a) T3 MOM CAT CLK _| --> IMLRO LATCH CLK _| | 21 ticks | 18 ticks | 15 ticks | | | | | (SAME AS 1st LOOKUP) 80 ns | 787.5 ns | 675 ns | 562.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b) T3 MOM CAT CLK _| --> T4 FMLN LTCH CLK _| | 3 ticks | 4 ticks | 3 ticks | | | | | CAT3 Clock > Final Sum: 50 ns | | | | travel time: Cable 15 ns | | | | ----- | | | | 65 ns | 112.5 ns | 150 ns | 112.5 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b') T4 FMLN LTCH CLK _| --> IMLRO LATCH CLK _| | 18 ticks | 14 ticks | 12 ticks | | | | | receive TSS H: 100114 2 ns | | | | latch Px, Py: 100151 3 ns | | | | mux Input>Output: 100155 2 ns | | | | lookup Addr>Data: 100C500 17 ns | | | | PAL Input>Output: 100E302 4 ns | | | | buffer: 100114 2 ns | | | | drive: 100114 2 ns | | | | travel time: Cable 30 ns | | | | ----- | | | | 62 ns | 675 ns | 525 ns | 450 ns | | | | | |--------------------|--------------------|--------------------| _ _ | | | | (b'') T4 FMLN LTCH CLK _| --> IML LATCH CLK _| | 18 ticks | 14 ticks | ??? 12 ticks | | | | | FMLN Clock > Threshold Compares 32 ns | | | | travel time: Cable 50 ns | | | | ----- | | | | 82 ns | 675 ns | 525 ns | 450 ns ??? | | | | |