---------------------------------------------------------------- ! CAT2 ! ! D0 FIRST LEVEL TRIGGER SYSTEM CALORIMETER ADDER TREE CARD ! ! TYPE 2 ! ---------------------------------------------------------------- Michigan State University - 2-JULY-1991 GENERAL DESCRIPTION In the Calorimeter Trigger two sets of signals are digitized and must then be summed. The electromagnetic energy and the Hadronic energy are the two signals. There are 32 phi signals per theta sector with theta sectors currently extending for either -19 to +19 or -20 to +20. This gives a total of either 1216 or 1280 signals which must be summed. This sum will be produced by an adder tree which takes place in 4 sections. Section 1 is on the CTFE card it sums 4 eight bit signals to produce a 10 bit partial sum. These 10 bit partial sums are summed by an 8 operand CAT2 card. Sections 3 and 4 are identical to section 2. This note describes CAT2 cards. Eight CAT2 cards will be used in each calorimeter trigger front end backplane. The outputs of these CAT2 cards will be sent to another backplane containing more CAT2 cards for section 3 of the calorimeter adder tree. The outputs of the section three CAT2 cards will be sent to one final CAT2 card. This card will output the final corrected sum for an event. The CAT2 operand inputs are differential ECL may be 0 to 12 bits in length. All operand inputs are terminated on card. Unused inputs or unused bits of an input default to logical 0. Each operand input is then latched. These latches are activated by timing signal H. By design these latches may be selected at the time of assembly to be either the 100150 transparent latches or the 100151 edge triggered latches. A board with the 100150 transparent latches may be used asynchronously as a fast ripple adder. When used in that manner a CAT2 card requires that timing signal H be held low. A board with the 100151 edge triggered latches may be used in a synchronous clocked system. In a clocked system the data set up at the 100151 inputs is latched on the rising edge of timing signal H. In either case the input operands may be latched for computer bus readout to be used in system testing. There is one eight bit control input. This input is a differential ECL input on the front panel. Each bit of this input is used to asynchronously reset one 12 bit operand input. Thus under external control individual operands may be eliminated from the sum. These inputs will default to the inactive or non reset state in the event no control input signal is applied. The outputs of the transparent latches are fed to an adder tree which produces the sum of the 8 input operands. The sum produced is 15 bits wide. The 15 bit sum is fed to four 15 bit magnitude comparators. Each magnitude comparator has a computer loadable register for its other input. The sum may thus be compared to 4 predetermined thresholds. The 'less than' outputs of these comparators is converted to differential ECL, inverted to provide a 'greater than or equal to' signal, and driven off card. The 15 bit sum is also converted to differential ECL and driven off card. Following the comparators the 15 bit sum is sent to a final adder where a two's complement number, computer loaded into a register may be added to the sum. Thus the 15 bit sum may be corrected to a 12 bit result for cascading to additional CAT2 cards. All 15 bits of this final adder are output as differential ECL. The accelerator RF system operates at a frequency of 53.104 MHz. This gives the time of an RF period to be 18.831 nanoseconds. At maximum luminosity the closest bunch to bunch spacing will be every 7th RF bucket. This is based on the information that are 1113 RF buckets in the accelerator and that the maximum fill is 144 bunches. This gives the shortest bunch to bunch time spacing of 131.82 nanoseconds. During this period the First Level Calorimeter Trigger System CAT2 Card will need to cycle two times. Thus the period available for a CAT2 Card to cycle is 65.91 nanoseconds. The First Level Calorimeter Trigger will be designed so that all CAT2 Card cycles will be of equal length (i.e. during a period of 7 RF buckets there will NOT be a short cycle followed by a long cycle). The following table summarizes the timing delays, and the necessary set up and hold times for the CAT2 card at 25 degrees. Operand Input Setup Time minimum typical maximum input line receiver stage 100114 .55 ns 2.4 ns latch 100151 .80 ns 2.4 ns ---------------------------------------------------------- total 4.8 ns Adder Tree Delay Time first adder stage delay 100180 1.1 ns 4.6 ns + 100180 2.5 ns 7.7 ns + 100114 .55 ns 2.4 ns total 3.1 ns 10.1 ns subsequent adder stages (3) 100180 1.1 ns 4.6 ns + 100179 2.5 ns 6.7 ns + 100180 3.6 ns 10.6 ns total (1) 3.6 ns 10.6 ns total (3) 10.8 ns 31.8 ns output buffer stage 100114 .55 ns 2.4 ns -------------------------------------------------------- total 15.6 ns 44.3 ns Comparator Delay Time delay through adder stages 11.5 ns 31.3 ns delay through comparator 100166 1.4 ns 3.7 ns +100166 2.8 ns 7.4 ns output buffer stage 100114 .55 ns 2.4 ns -------------------------------------------------------- total 14.9 ns 41.1 ns Note there is a non corrected sum output available one adder stage delay earlier than the corrected sum output ie at 33.7 ns. There are eight connectors on the CAT2 card. Connectors J1, J2, J3, and J4 bring system ground, the +5.0 Volt supply, the -4.5 Volt supply, the -2.0 Volt supply, the 12 operand inputs, and the computer bus onto the card. The 8 operand inputs are close packed on the 96 available differential inputs on connectors J1, J2, J3, and J4. A plug in paddle board is used on the back of the backplane to adapt 8 34 conductor cables to the close packed inputs J1 and J2. Note the card is constructed of 100K series ECL logic and uses a supply of -4.5 Volts as well as a supply of -2.0 Volts for the signal line terminator resistors. Connector J5 carries the 15 bit final (corrected) sum off card. Connector J6 carries the 15 bit partial (non-corrected) sum off card. Connector J7 carries the 4 comparator greater than signals off card. Connector J8 brings the 8 bit control input onto the card. The CAT2 card requires -4.5 Volts at approximately 21 Amps. See the note at the end of this paper for a list of the IC's used along with typical and maximum currents as specified in the IC data sheets. Note a statistical analysis of the power supply requirements for the -4.5 Volt supply shows that the cards will require 21.5 Amps or less per card at the 99.8% confidence level (See "Calculating the Current Requirements of Power Supplies", Electronic Products, January 1, 1985). Signal lines are terminated with 68 Ohm resistors to a -2.0 Volt supply. A supply of about 9 amps at 2.0 Volts will be required. Also for the receiver default condition bias networks a +5.0 volt supply at approximately 200 milliAmps will be required. As eight boards are used per Calorimeter Trigger Front End Backplane and there are four backplanes per rack the CAT2 cards will require supplies of about 660 to 690 amps @ -4.5 Volts per rack and about 260 to 290 amps @ -2.0 Volts per rack. This is in addition to the standard supplies required for the rest of the Calorimeter Trigger Front End logic. PROGRAMMING The CAT2 card has 16 read only registers used to read the value of the 12 bit input operands and 15 read/write registers used to load the magnitude comparison registers and the correction register. The 16 read only registers occupy function address's 0 through 15. Two function addresses are used for each 12 bit operand. The 15 read write registers occupy function addresses 16 through 30. Three function addresses are used for each 15 bit register. Information about the function addresses is summarized in the table below. Function Address Read Function --------------------------------------------------------------- 0 read input operand latch 1 bits 1 - 6 1 read input operand latch 1 bits 7 -12 2 read input operand latch 2 bits 1 - 6 3 read input operand latch 2 bits 7 -12 4 read input operand latch 3 bits 1 - 6 5 read input operand latch 3 bits 7 -12 6 read input operand latch 4 bits 1 - 6 7 read input operand latch 4 bits 7 -12 8 read input operand latch 5 bits 1 - 6 9 read input operand latch 5 bits 7 -12 10 read input operand latch 6 bits 1 - 6 11 read input operand latch 6 bits 7 -12 12 read input operand latch 7 bits 1 - 6 13 read input operand latch 7 bits 7 -12 14 read input operand latch 8 bits 1 - 6 15 read input operand latch 8 bits 7 -12 16 read correction register bits 1 - 6 17 read correction register bits 7 -12 18 read correction register bits 13 -15 19 read comparator register 1 bits 1 - 6 20 read comparator register 1 bits 7 -12 21 read comparator register 1 bits 13 -15 and comparator 1 output bits 22 read comparator register 2 bits 1 - 6 23 read comparator register 2 bits 7 -12 24 read comparator register 2 bits 13 -15 and comparator 2 output bits 25 read comparator register 3 bits 1 - 6 26 read comparator register 3 bits 7 -12 27 read comparator register 3 bits 13 -15 and comparator 3 output bits 28 read comparator register 4 bits 1 - 6 29 read comparator register 4 bits 7 -12 30 read comparator register 4 bits 13 -15 and comparator 4 output bits The CAT2 uses 6-bit registers, NOT 8-bit registers. The upper two bits of each register will always be set to 0. Note that Function Addresses 21, 24, 27, and 30 contain the following information: Bit Contents --- -------- (8) Zero (7) Zero 6 1: Partial sum < Comparator n (0: PS >=C) 5 1: Partial sum > Comparator n (0: PS <= C) 4 1: Partial sum <> Comparator n (0: PS = C) 3 Comparator data bit 15 2 Comparator data bit 14 1 Comparator data bit 13 Function Address Write Function ---------------------------------------------------------------- 16 write correction register bits 1 - 6 17 write correction register bits 7 -12 18 write correction register bits 13 -15 19 write comparator register 1 bits 1 - 6 20 write comparator register 1 bits 7 -12 21 write comparator register 1 bits 13 -15 22 write comparator register 2 bits 1 - 6 23 write comparator register 2 bits 7 -12 24 write comparator register 2 bits 13 -15 25 write comparator register 3 bits 1 - 6 26 write comparator register 3 bits 7 -12 27 write comparator register 3 bits 13 -15 28 write comparator register 4 bits 1 - 6 29 write comparator register 4 bits 7 -12 30 write comparator register 4 bits 13 -15 There are no wire wrap posts or jumpers on the CAT2 card. There is one 8 switch DIP switch used to set the card address. Bits one through six of this switch are used to select the card address as shown in the table below. Bits seven and eight are unused. Note for these switches when closed or in the on position represent a logical 1. Switch Number Function ----------------- -------------- 1 Card Address 1 2 Card Address 2 3 Card Address 3 4 Card Address 4 5 Card Address 5 6 Card Address 6 7 Unused 8 Unused There are 21 LED's on the CAT2 card. Seventeen of these LED's are used to display the final sum output. The other 4 LED's display the state of the comparator outputs. All LED's are active high ie they glow when signal displayed is true. Following is a table of the signals displayed on the LED's. LED Signal Displayed --------------------------------- DS1 F SUM BIT 17 DS2 F SUM BIT 16 DS3 F SUM BIT 15 DS4 F SUM BIT 14 DS5 F SUM BIT 13 DS6 F SUM BIT 12 DS7 F SUM BIT 11 DS8 F SUM BIT 10 DS9 F SUM BIT 9 DS10 F SUM BIT 8 DS11 F SUM BIT 7 DS12 F SUM BIT 6 DS13 F SUM BIT 5 DS14 F SUM BIT 4 DS15 F SUM BIT 3 DS16 F SUM BIT 2 DS17 F SUM BIT 1 DS18 P SUM = COMP 4 DS19 P SUM = COMP 3 DS20 P SUM = COMP 2 DS21 P SUM = COMP 1 TESTING There are many levels on which the CAT2 card can and must be tested. These will be seperated into three catagories. First there is computer bus interface testing. Second there is static (quasi-dynamic) adder testing. Third there is dynamic testing to verify worst case timing. OPTIONS By eliminating certain parts from a completed board options can be obtained which reduce functionality but offer reduced cost per board and reduced power consumption. 1. The ability to read the operand latches may be eliminated by eliminating the 16 100123 buffers that buffer the latch outputs. and the 2 100170 read data selectors. This option would save about 3 amps of VEE per board. 2. Comparator elimination. Any or all of the comparators, comparator data latches, and comparator read buffers may be eliminated in final assembly saving about 5 amps per card. Note however that the partial sum terminator resistors are located in the compartor assembly and must be installed. CONNECTORS J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 1 Bit 1 Inverted IN IIO1.1 34 Input Operand 1 Bit 2 Inverted IN IIO1.2 35 Input Operand 1 Bit 3 Inverted IN IIO1.3 36 Input Operand 1 Bit 4 Inverted IN IIO1.4 37 Input Operand 1 Bit 5 Inverted IN IIO1.5 38 Input Operand 1 Bit 6 Inverted IN IIO1.6 39 Input Operand 1 Bit 7 Inverted IN IIO1.7 40 Input Operand 1 Bit 8 Inverted IN IIO1.8 41 Input Operand 1 Bit 9 Inverted IN IIO1.9 42 Input Operand 1 Bit 10 Inverted IN IIO1.10 43 Input Operand 1 Bit 11 Inverted IN IIO1.11 44 Input Operand 1 Bit 12 Inverted IN IIO1.12 45 Input Operand 2 Bit 1 Inverted IN IIO2.1 46 Input Operand 2 Bit 2 Inverted IN IIO2.2 47 Input Operand 2 Bit 3 Inverted IN IIO2.3 48 Input Operand 2 Bit 4 Inverted IN IIO2.4 49 Input Operand 2 Bit 5 Inverted IN IIO2.5 50 Input Operand 2 Bit 6 Inverted IN IIO2.6 51 Input Operand 2 Bit 7 Inverted IN IIO2.7 52 Input Operand 2 Bit 8 Inverted IN IIO2.8 53 Input Operand 2 Bit 9 Inverted IN IIO2.9 54 Input Operand 2 Bit 10 Inverted IN IIO2.10 55 Input Operand 2 Bit 11 Inverted IN IIO2.11 56 Input Operand 2 Bit 12 Inverted IN IIO2.12 57 Input Operand 3 Bit 1 Inverted IN IIO3.1 58 Input Operand 3 Bit 2 Inverted IN IIO3.2 59 Input Operand 3 Bit 3 Inverted IN IIO3.3 60 Input Operand 3 Bit 4 Inverted IN IIO3.4 61 Input Operand 3 Bit 5 Inverted IN IIO3.5 62 Input Operand 3 Bit 6 Inverted IN IIO3.6 63 Input Operand 3 Bit 7 Inverted IN IIO3.7 64 Input Operand 3 Bit 8 Inverted IN IIO3.8 65 Input Operand 1 Bit 1 Non-inverted IN NIO1.1 66 Input Operand 1 Bit 2 Non-inverted IN NIO1.2 67 Input Operand 1 Bit 3 Non-inverted IN NIO1.3 68 Input Operand 1 Bit 4 Non-inverted IN NIO1.4 69 Input Operand 1 Bit 5 Non-inverted IN NIO1.5 70 Input Operand 1 Bit 6 Non-inverted IN NIO1.6 71 Input Operand 1 Bit 7 Non-inverted IN NIO1.7 72 Input Operand 1 Bit 8 Non-inverted IN NIO1.8 73 Input Operand 1 Bit 9 Non-inverted IN NIO1.9 74 Input Operand 1 Bit 10 Non-inverted IN NIO1.10 75 Input Operand 1 Bit 11 Non-inverted IN NIO1.11 76 Input Operand 1 Bit 12 Non-inverted IN NIO1.12 77 Input Operand 2 Bit 1 Non-inverted IN NIO2.1 78 Input Operand 2 Bit 2 Non-inverted IN NIO2.2 79 Input Operand 2 Bit 3 Non-inverted IN NIO2.3 80 Input Operand 2 Bit 4 Non-inverted IN NIO2.4 81 Input Operand 2 Bit 5 Non-inverted IN NIO2.5 82 Input Operand 2 Bit 6 Non-inverted IN NIO2.6 83 Input Operand 2 Bit 7 Non-inverted IN NIO2.7 84 Input Operand 2 Bit 8 Non-inverted IN NIO2.8 85 Input Operand 2 Bit 9 Non-inverted IN NIO2.9 86 Input Operand 2 Bit 10 Non-inverted IN NIO2.10 87 Input Operand 2 Bit 11 Non-inverted IN NIO2.11 88 Input Operand 2 Bit 12 Non-inverted IN NIO2.12 89 Input Operand 3 Bit 1 Non-inverted IN NIO3.1 90 Input Operand 3 Bit 2 Non-inverted IN NIO3.2 91 Input Operand 3 Bit 3 Non-inverted IN NIO3.3 92 Input Operand 3 Bit 4 Non-inverted IN NIO3.4 93 Input Operand 3 Bit 5 Non-inverted IN NIO3.5 94 Input Operand 3 Bit 6 Non-inverted IN NIO3.6 95 Input Operand 3 Bit 7 Non-inverted IN NIO3.7 96 Input Operand 3 Bit 8 Non-inverted IN NIO3.8 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 3 Bit 9 Inverted IN IIO3.9 34 Input Operand 3 Bit 10 Inverted IN IIO3.10 35 Input Operand 3 Bit 11 Inverted IN IIO3.11 36 Input Operand 3 Bit 12 Inverted IN IIO3.12 37 Input Operand 4 Bit 1 Inverted IN IIO4.1 38 Input Operand 4 Bit 2 Inverted IN IIO4.2 39 Input Operand 4 Bit 3 Inverted IN IIO4.3 40 Input Operand 4 Bit 4 Inverted IN IIO4.4 41 Input Operand 4 Bit 5 Inverted IN IIO4.5 42 Input Operand 4 Bit 6 Inverted IN IIO4.6 43 Input Operand 4 Bit 7 Inverted IN IIO4.7 44 Input Operand 4 Bit 8 Inverted IN IIO4.8 45 Input Operand 4 Bit 9 Inverted IN IIO4.9 46 Input Operand 4 Bit 10 Inverted IN IIO4.10 47 Input Operand 4 Bit 11 Inverted IN IIO4.11 48 Input Operand 4 Bit 12 Inverted IN IIO4.12 49 Input Operand 5 Bit 1 Inverted IN IIO5.1 50 Input Operand 5 Bit 2 Inverted IN IIO5.2 51 Input Operand 5 Bit 3 Inverted IN IIO5.3 52 Input Operand 5 Bit 4 Inverted IN IIO5.4 53 Input Operand 5 Bit 5 Inverted IN IIO5.5 54 Input Operand 5 Bit 6 Inverted IN IIO5.6 55 Input Operand 5 Bit 7 Inverted IN IIO5.7 56 Input Operand 5 Bit 8 Inverted IN IIO5.8 57 Input Operand 5 Bit 9 Inverted IN IIO5.9 58 Input Operand 5 Bit 10 Inverted IN IIO5.10 59 Input Operand 5 Bit 11 Inverted IN IIO5.11 60 Input Operand 5 Bit 12 Inverted IN IIO5.12 61 Input Operand 6 Bit 1 Inverted IN IIO6.1 62 Input Operand 6 Bit 2 Inverted IN IIO6.1 63 Input Operand 6 Bit 3 Inverted IN IIO6.1 64 Input Operand 6 Bit 4 Inverted IN IIO6.1 65 Input Operand 3 Bit 9 Non-inverted IN NIO3.9 66 Input Operand 3 Bit 10 Non-inverted IN NIO3.10 67 Input Operand 3 Bit 11 Non-inverted IN NIO3.11 68 Input Operand 3 Bit 12 Non-inverted IN NIO3.12 69 Input Operand 4 Bit 1 Non-inverted IN NIO4.1 70 Input Operand 4 Bit 2 Non-inverted IN NIO4.2 71 Input Operand 4 Bit 3 Non-inverted IN NIO4.3 72 Input Operand 4 Bit 4 Non-inverted IN NIO4.4 73 Input Operand 4 Bit 5 Non-inverted IN NIO4.5 74 Input Operand 4 Bit 6 Non-inverted IN NIO4.6 75 Input Operand 4 Bit 7 Non-inverted IN NIO4.7 76 Input Operand 4 Bit 8 Non-inverted IN NIO4.8 77 Input Operand 4 Bit 9 Non-inverted IN NIO4.9 78 Input Operand 4 Bit 10 Non-inverted IN NIO4.10 79 Input Operand 4 Bit 11 Non-inverted IN NIO4.11 80 Input Operand 4 Bit 12 Non-inverted IN NIO4.12 81 Input Operand 5 Bit 1 Non-inverted IN NIO5.1 82 Input Operand 5 Bit 2 Non-inverted IN NIO5.2 83 Input Operand 5 Bit 3 Non-inverted IN NIO5.3 84 Input Operand 5 Bit 4 Non-inverted IN NIO5.4 85 Input Operand 5 Bit 5 Non-inverted IN NIO5.5 86 Input Operand 5 Bit 6 Non-inverted IN NIO5.6 87 Input Operand 5 Bit 7 Non-inverted IN NIO5.7 88 Input Operand 5 Bit 8 Non-inverted IN NIO5.8 89 Input Operand 5 Bit 9 Non-inverted IN NIO5.9 90 Input Operand 5 Bit 10 Non-inverted IN NIO5.10 91 Input Operand 5 Bit 11 Non-inverted IN NIO5.11 92 Input Operand 5 Bit 12 Non-inverted IN NIO5.12 93 Input Operand 6 Bit 1 Non-inverted IN NIO695 94 Input Operand 6 Bit 2 Non-inverted IN NIO6.2 95 Input Operand 6 Bit 3 Non-inverted IN NIO6.3 96 Input Operand 6 Bit 4 Non-inverted IN NIO6.4 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 6 Bit 5 Inverted IN IIO6.5 34 Input Operand 6 Bit 6 Inverted IN IIO6.6 35 Input Operand 6 Bit 7 Inverted IN IIO6.7 36 Input Operand 6 Bit 8 Inverted IN IIO6.8 37 Input Operand 6 Bit 9 Inverted IN IIO6.9 38 Input Operand 6 Bit 10 Inverted IN IIO6.10 39 Input Operand 6 Bit 11 Inverted IN IIO6.11 40 Input Operand 6 Bit 12 Inverted IN IIO6.12 41 Input Operand 7 Bit 1 Inverted IN IIO7.1 42 Input Operand 7 Bit 2 Inverted IN IIO7.2 43 Input Operand 7 Bit 3 Inverted IN IIO7.3 44 Input Operand 7 Bit 4 Inverted IN IIO7.4 45 Input Operand 7 Bit 5 Inverted IN IIO7.5 46 Input Operand 7 Bit 6 Inverted IN IIO7.6 47 Input Operand 7 Bit 7 Inverted IN IIO7.7 48 Input Operand 7 Bit 8 Inverted IN IIO7.8 49 Input Operand 7 Bit 9 Inverted IN IIO7.9 50 Input Operand 7 Bit 10 Inverted IN IIO7.10 51 Input Operand 7 Bit 11 Inverted IN IIO7.11 52 Input Operand 7 Bit 12 Inverted IN IIO7.12 53 Input Operand 8 Bit 1 Inverted IN IIO8.1 54 Input Operand 8 Bit 2 Inverted IN IIO8.2 55 Input Operand 8 Bit 3 Inverted IN IIO8.3 56 Input Operand 8 Bit 4 Inverted IN IIO8.4 57 Input Operand 8 Bit 5 Inverted IN IIO8.5 58 Input Operand 8 Bit 6 Inverted IN IIO8.6 59 Input Operand 8 Bit 7 Inverted IN IIO8.7 60 Input Operand 8 Bit 8 Inverted IN IIO8.8 61 Input Operand 8 Bit 9 Inverted IN IIO8.9 62 Input Operand 8 Bit 10 Inverted IN IIO8.10 63 Input Operand 8 Bit 11 Inverted IN IIO8.11 64 Input Operand 8 Bit 12 Inverted IN IIO8.12 65 Input Operand 6 Bit 5 Non-inverted IN NIO6.5 66 Input Operand 6 Bit 6 Non-inverted IN NIO6.6 67 Input Operand 6 Bit 7 Non-inverted IN NIO6.7 68 Input Operand 6 Bit 8 Non-inverted IN NIO6.8 69 Input Operand 6 Bit 9 Non-inverted IN NIO6.9 70 Input Operand 6 Bit 10 Non-inverted IN NIO6.10 71 Input Operand 6 Bit 11 Non-inverted IN NIO6.11 72 Input Operand 6 Bit 12 Non-inverted IN NIO6.12 73 Input Operand 7 Bit 1 Non-inverted IN NIO7.1 74 Input Operand 7 Bit 2 Non-inverted IN NIO7.2 75 Input Operand 7 Bit 3 Non-inverted IN NIO7.3 76 Input Operand 7 Bit 4 Non-inverted IN NIO7.4 77 Input Operand 7 Bit 5 Non-inverted IN NIO7.5 78 Input Operand 7 Bit 6 Non-inverted IN NIO7.6 79 Input Operand 7 Bit 7 Non-inverted IN NIO7.7 80 Input Operand 7 Bit 8 Non-inverted IN NIO7.8 81 Input Operand 7 Bit 9 Non-inverted IN NIO7.9 82 Input Operand 7 Bit 10 Non-inverted IN NIO7.10 83 Input Operand 7 Bit 11 Non-inverted IN NIO7.11 84 Input Operand 7 Bit 12 Non-inverted IN NIO7.12 85 Input Operand 8 Bit 1 Non-inverted IN NIO8.1 86 Input Operand 8 Bit 2 Non-inverted IN NIO8.2 87 Input Operand 8 Bit 3 Non-inverted IN NIO8.3 88 Input Operand 8 Bit 4 Non-inverted IN NIO8.4 89 Input Operand 8 Bit 5 Non-inverted IN NIO8.5 90 Input Operand 8 Bit 6 Non-inverted IN NIO8.6 91 Input Operand 8 Bit 7 Non-inverted IN NIO8.7 92 Input Operand 8 Bit 8 Non-inverted IN NIO8.8 93 Input Operand 8 Bit 9 Non-inverted IN NIO8.9 94 Input Operand 8 Bit 10 Non-inverted IN NIO8.10 95 Input Operand 8 Bit 11 Non-inverted IN NIO8.11 96 Input Operand 8 Bit 12 Non-inverted IN NIO8.12 ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 TSS H Operand Latch Clk Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 TSS H Operand Latch Clk Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 ----------------------------------------------------------------------------- J5 : FIRST LEVEL CALORIMETER TRIGGER CAT2 FINAL SUM CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Final Sum Bit 1 Non-inverted OUT 1 NFS1 2 Final Sum Bit 1 Inverted OUT 2 IFS1 3 Final Sum Bit 2 Non-inverted OUT 1 NFS2 4 Final Sum Bit 2 Inverted OUT 2 IFS2 5 Final Sum Bit 3 Non-inverted OUT 1 NFS3 6 Final Sum Bit 3 Inverted OUT 2 IFS3 7 Final Sum Bit 4 Non-inverted OUT 1 NFS4 8 Final Sum Bit 4 Inverted OUT 2 IFS4 9 Final Sum Bit 5 Non-inverted OUT 1 NFS5 10 Final Sum Bit 5 Inverted OUT 2 IFS5 11 Final Sum Bit 6 Non-inverted OUT 1 NFS6 12 Final Sum Bit 6 Inverted OUT 2 IFS6 13 Final Sum Bit 7 Non-inverted OUT 1 NFS7 14 Final Sum Bit 7 Inverted OUT 2 IFS7 15 Final Sum Bit 8 Non-inverted OUT 1 NFS8 16 Final Sum Bit 8 Inverted OUT 2 IFS8 17 Final Sum Bit 9 Non-inverted OUT 1 NFS9 18 Final Sum Bit 9 Inverted OUT 2 IFS9 19 Final Sum Bit 10 Non-inverted OUT 1 NFS10 20 Final Sum Bit 10 Inverted OUT 2 IFS10 21 Final Sum Bit 11 Non-inverted OUT 1 NFS11 22 Final Sum Bit 11 Inverted OUT 2 IFS11 23 Final Sum Bit 12 Non-inverted OUT 1 NFS12 24 Final Sum Bit 12 Inverted OUT 2 IFS12 25 Final Sum Bit 13 Non-inverted OUT 1 NFS13 26 Final Sum Bit 13 Inverted OUT 2 IFS13 27 Final Sum Bit 14 Non-inverted OUT 1 NFS14 28 Final Sum Bit 14 Inverted OUT 2 IFS14 29 Final Sum Bit 15 Non-inverted OUT 1 NFS15 30 Final Sum Bit 15 Inverted OUT 2 IFS15 31 Final Sum Bit 16 Non-inverted OUT 1 NFS16 32 Final Sum Bit 16 Inverted OUT 2 IFS16 33 Final Sum Bit 17 Non-inverted OUT 1 NFS17 34 Final Sum Bit 17 Inverted OUT 2 IFS17 ----------------------------------------------------------------------------- J6 : FIRST LEVEL CALORIMETER TRIGGER CAT2 PARTIAL SUM CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Partial Sum Bit 1 Non-inverted OUT 1 NPS1 2 Partial Sum Bit 1 Inverted OUT 2 IPS1 3 Partial Sum Bit 2 Non-inverted OUT 1 NPS2 4 Partial Sum Bit 2 Inverted OUT 2 IPS2 5 Partial Sum Bit 3 Non-inverted OUT 1 NPS3 6 Partial Sum Bit 3 Inverted OUT 2 IPS3 7 Partial Sum Bit 4 Non-inverted OUT 1 NPS4 8 Partial Sum Bit 4 Inverted OUT 2 IPS4 9 Partial Sum Bit 5 Non-inverted OUT 1 NPS5 10 Partial Sum Bit 5 Inverted OUT 2 IPS5 11 Partial Sum Bit 6 Non-inverted OUT 1 NPS6 12 Partial Sum Bit 6 Inverted OUT 2 IPS6 13 Partial Sum Bit 7 Non-inverted OUT 1 NPS7 14 Partial Sum Bit 7 Inverted OUT 2 IPS7 15 Partial Sum Bit 8 Non-inverted OUT 1 NPS8 16 Partial Sum Bit 8 Inverted OUT 2 IPS8 17 Partial Sum Bit 9 Non-inverted OUT 1 NPS9 18 Partial Sum Bit 9 Inverted OUT 2 IPS9 19 Partial Sum Bit 10 Non-inverted OUT 1 NPS10 20 Partial Sum Bit 10 Inverted OUT 2 IPS10 21 Partial Sum Bit 11 Non-inverted OUT 1 NPS11 22 Partial Sum Bit 11 Inverted OUT 2 IPS11 23 Partial Sum Bit 12 Non-inverted OUT 1 NPS12 24 Partial Sum Bit 12 Inverted OUT 2 IPS12 25 Partial Sum Bit 13 Non-inverted OUT 1 NPS13 26 Partial Sum Bit 13 Inverted OUT 2 IPS13 27 Partial Sum Bit 14 Non-inverted OUT 1 NPS14 28 Partial Sum Bit 14 Inverted OUT 2 IPS14 29 Partial Sum Bit 15 Non-inverted OUT 1 NPS15 30 Partial Sum Bit 15 Inverted OUT 2 IPS15 31 Unused 32 Unused 33 Unused 34 Unused ----------------------------------------------------------------------------- J7 : FIRST LEVEL CALORIMETER TRIGGER CAT2 COMPARATOR CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Comparator 1 Greater Than Non-inverted OUT 1 NGT1 2 Comparator 1 Greater Than Inverted OUT 2 IGT1 3 Comparator 2 Greater Than Non-inverted OUT 1 NGT2 4 Comparator 2 Greater Than Inverted OUT 2 IGT2 5 Comparator 3 Greater Than Non-inverted OUT 1 NGT3 6 Comparator 3 Greater Than Inverted OUT 2 IGT3 7 Comparator 4 Greater Than Non-inverted OUT 1 NGT4 8 Comparator 4 Greater Than Inverted OUT 2 IGT4 9 Unused 10 Unused 11 Unused 12 Unused 13 Unused 14 Unused 15 Unused 16 Unused 17 Unused 18 Unused 19 Unused 20 Unused 21 Unused 22 Unused 23 Unused 24 Unused 25 Unused 26 Unused 27 Unused 28 Unused 29 Unused 30 Unused 31 Unused 32 Unused 33 Unused 34 Unused ----------------------------------------------------------------------------- J8 : FIRST LEVEL CALORIMETER TRIGGER CAT2 FAST RESET CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Async Latch 1 Reset Non-inverted IN 1 NLR1 2 Async Latch 1 Reset Inverted IN 2 ILR1 3 Async Latch 2 Reset Non-inverted IN 1 NLR2 4 Async Latch 2 Reset Inverted IN 2 ILR2 5 Async Latch 3 Reset Non-inverted IN 1 NLR3 6 Async Latch 3 Reset Inverted IN 2 ILR3 7 Async Latch 4 Reset Non-inverted IN 1 NLR4 8 Async Latch 4 Reset Inverted IN 2 ILR4 9 Async Latch 5 Reset Non-inverted IN 1 NLR5 10 Async Latch 5 Reset Inverted IN 2 ILR5 11 Async Latch 6 Reset Non-inverted IN 1 NLR6 12 Async Latch 6 Reset Inverted IN 2 ILR6 13 Async Latch 7 Reset Non-inverted IN 1 NLR7 14 Async Latch 7 Reset Inverted IN 2 ILR7 15 Async Latch 8 Reset Non-inverted IN 1 NLR8 16 Async Latch 8 Reset Inverted IN 2 ILR8 17 Unused 18 Unused 19 Unused 20 Unused 21 Unused 22 Unused 23 Unused 24 Unused 25 Unused 26 Unused 27 Unused 28 Unused 29 Unused 30 Unused 31 Unused 32 Unused 33 Unused 34 Unused ----------------------------------------------------------------------------- BOARD HISTORY ------------- REVISION A - ________ boards All Revision A Boards obsolete: 31-JAN-1990 REVISION B - 115 boards: 31-JAN-1990 ECO HISTORY ----------- REVISION A: All Revision A ECOs were incorporated into Revision B etch. REVISION B: 1. All 6-pin and 8-pin SIP resistors indicated as 51 ohms in the print set actually require 68 ohm resistor packs. The resistors involved are: R37-R141, R157-R211, R213-R217 2. The "Adder ripple carry" ECO is covered in the following note. Problem with the First Stage Adder Circuit in the CAT2 Rev B Card --------------------------------------------------------------------- 28-June-1991 A major problem was discovered in the logic circuit design of the CAT2 Rev B first stage adders. This problem is due to the attempted use of the F100180 6 Bit Adder chips in a ripple carry mode. The problem is in all 4 of the first stage adders. These are shown on pages 24...27 of the CAT2 Rev B print sets. Because the F100180 6 Bit Adder chips are designed to be used with a Carry Lookahead Generator (F100179) the Carry In (Cn*) input does not effect the Carry Generate (G*) output (or the Carry Propagate P* output). The Carry In only affects the six Function Outputs (F0...F5). This makes sense because if the Carry In effected the Carry Generate output then the chip would be ripple carrying and thus it could not be controlled by a Lookahead Carry Generator for fast long word operation. The result of the attempt to use the F100180 in a ripple carry mode in the first stage adders on the CAT2 Rev B board is the following: 1. IF the higher order chip (i.e. bits 7 through 12) of a first stage adder is ready to carry (i.e. for each bit value of bits 7 through 12 there is one and only one input bit set high, either of operand A or of operand B) 2. AND IF for this same first stage adder the low order chip (i.e. bits 1 through 6) has enough of its inputs bits set high so that it is Generating a Carry output 3. THEN what you would expect is for the low order chip's active Carry Output to ripple through the high order chip and cause the high order chip to "carry" (i.e. all of the high order chip's output bits 7...12 would go to the low state and this high order chip's Carry output would become active that is bit 13 would become logical High). 4. BUT the F100180 does not work this way. The Carry In to the high order adder chip causes all of its outputs to go logic Low but does not cause this high order adder chip's Carry Generate output to become active i.e. Bit 13 stays logic Low, no Carry Out is Generated. Recall that before this chip received an active Carry In all of its 6 Function Outputs where logic High. 5. THUS for this range of inputs (one and only one of each bit from 7 through 12 set High AND bits 1 through 6 generating a carry) the output from a first stage added will be 4096 lower than it should be. NOTES: -------- 1. This logic design error does not cause a problem for CAT2 Rev B cards used in Tier 1 cells or for the CAT2 Rev B cards used in Tier 2 COUNTER TREE applications. This problem only occurs when the CAT2 Rev B card is used in a Tier 2 Energy or Momentum ADDER TREE applications. Of all of the CAT2 Rev B cards only 24 are used in these Tier 2 ADDER TREES. 2. The CAT3 card suffers from a similar problem on page 29 of the schematic. The details of this problem and the solution can be found under CAT3 ECO in the CAT3 description. SOLUTION: ----------- 1. The Bit 13 from a first stage adder should become logic High when: EITHER the high order chip's Generate Garry output is active OR when the low order chip's Generate Carry output is active AND the high order chip's Carry Propagate output is active. Note many of these signals are active when at the lower voltage level. 2. Spare logic in two F100179 Lookahead Carry Generator chips (U79 and U85) can be connected to the first stage adders to correct the logic. The Cn+6 section of U79 will be used in the adder for operands 1 and 2. The Cn+8 section of U79 will be used in the adder for operands 3 and 4. The Cn+6 section of U85 will be used in the adder for operands 5 and 6. The Cn+8 section of U85 will be used in the adder for operands 7 and 8. CIRCUIT BOARD WORK: (See Board Plots for Visual View) --------------------- ACTION OPERAND 1+2 OPERAND 3+4 OPERAND 5+6 OPERAND 7+8 -------- --------------- --------------- --------------- --------------- CUT H.O. Carry TRC @ U69-P11 TRC @ U72-P11 TRC @ U75-P11 TRC @ U78-P11 GENRATE to TRC @ U73-P1 TRC @ U73-P15 TRC @ R114-P5 TRC @ R114-P4 INVERTER Note: All trace cuts are on the component side except TRC @ R114-P5 and TRC @ R114-P4 which are on the solder side. CONNECT (Solder Side) P5* or P7* WRW @ U79-P15 WRW @ U79-P21 WRW @ U85-P15 WRW @ U85-P21 to a WRW @ R126-P7 WRW @ R126-P5 WRW @ R129-P7 WRW @ R129-P5 PULL-DOWN P5* P7* P5* P7* CONNECT (Solder Side) G5* or G7* WRW @ U79-P14 WRW @ U79-P20 WRW @ U85-P14 WRW @ U85-P20 to a WRW @ R126-P8 WRW @ R126-P6 WRW @ R129-P8 WRW @ R129-P6 PULL-DOWN G5* G7* G5* G7* CONNECT (Solder Side) ECL HIGH JMP U79-P10 JMP U79-P10 JMP U85-P10 JMP U85-P10 to P4* JMP U79-P13 JMP U79-P17 JMP U85-P13 JMP U85-P17 and P6* P4* P6* P4* P6* CONNECT (Solder Side) L.O. Carry WRW @ U68-P11 WRW @ U71-P11 WRW @ U74-P11 WRW @ U77-P11 GENRATE to WRW @ U79-P12 WRW @ U79-P16 WRW @ U85-P12 WRW @ U85-P16 G4* or G6* G4* G6* G4* G6* CONNECT (Component Side) H.O. Carry WRW @ U69-P10 WRW @ U72-P10 WRW @ U75-P10 WRW @ U78-P10 PROPAGT to WRW @ U79-P15 WRW @ U79-P21 WRW @ U85-P15 WRW @ U85-P21 P5* or P7* P5* P7* P5* P7* CONNECT (Component Side) H.O. Carry WRW @ U69-P11 WRW @ U72-P11 WRW @ U75-P11 WRW @ U78-P11 GENRATE to WRW @ U79-P14 WRW @ U79-P20 WRW @ U85-P14 WRW @ U85-P20 G5* or G7* G5* G7* G5* G7* CONNECT (Component Side) Cn+6* or Cn+6* Cn+8* Cn+6* Cn+8* Cn+8* to WRW @ U79-P8 WRW @ U79-P9 WRW @ U85-P8 WRW @ U85-P9 INVERTER TRC @ U73-P1 TRC @ U73-P15 TRC @ U73-P17 TRC @ U73-P21 NOTE: All Wire Wrap Wires will be glued down, and Trace cuts sealed with a drop of glue. ----------- END OF ECO'S ------------ POWER SUPPLY CURRENT CALCULATION ------------------------------------ - IC's proposed Adder Section typical maximum total total max 28 100114 .073 .106 2.04 2.97 16 100123 .170 .235 2.72 3.76 16 100151 .155 .210 2.48 3.36 4 100179 .150 .220 0.60 0.88 20 100180 .195 .290 3.90 5.80 Comparator Section 1 100114 .073 .106 0.07 0.11 15 100123 .170 .235 2.55 3.53 15 100151 .155 .210 2.33 3.15 8 100166 .170 .238 1.36 1.90 Computer Bus Interface 1 100101 .026 .038 0.03 0.04 15 100114 .073 .106 1.10 1.59 4 100123 .170 .235 0.68 0.94 1 100166 .170 .238 0.17 0.24 7 100170 .109 .153 0.76 1.07 TOTAL 144 20.79 29.34 Amps Note following the procedure outlined in Calculating the Current Requirement of Power Supplies, Electronic Products, January 1, 1985, the maximum current per card can be calculated such 99.8 per cent of the cards will be below this value. The calculation is shown below. n type Imax-Ityp n(Imax-Imin)^2 ------------------------------------------- 1 100101 .012 1.4e-4 44 100114 .033 .048 35 100123 .065 .148 31 100151 .055 .094 9 100166 .068 .042 7 100170 .044 .014 4 100179 .070 .020 20 100180 .095 .181 ------------------------------------------- sum .545 square root of sum .738 Thus the maximum current per card would be approximately 20.5 Amps. CAT2 POWER CONSUMPTION ---------------------- Current to 12 tier 2 CAT2's was measured on 29-July-1991 and found to be 21.6 A @ 4.543 V and 8.3 A @ 2.035 V per board. Appendix A A brief analysis of building this card with 10k ECL logic. Following is an approximate list of the chips that would be required to make up a CAT2 card from 10k ECL logic and the currents that it would require. From this it appears that a CAT2 card built with 10k ECL would take less VEE current than a 100k CAT2 card. The number of chips however is more than will fit on a standard D0 trigger card and the number of signal lines is much larger than with 100k thus requiring a larger VTT supply. Another limiting factor about 10k ECL is the speed. It would take about 100 ns worst case to produce the sum. Adder Section 24 10H115 .042 1.01 24 10H173 .066 1.58 16 10H179 .072 1.15 54 10H180 .086 4.64 24 10H188 .042 1.01 Comparator Section 14 10H101 .026 .36 2 10H115 .042 .08 16 10H166 .106 1.70 24 10H173 .066 1.58 24 10H188 .042 1.01 Computer Bus Interface 4 10H101 .026 .10 2 10H102 .026 .05 7 10H115 .042 .29 5 10H161 .076 .38 2 10H166 .106 .21 13 10H188 .042 .55 TOTAL 255 15.7 Amps ----------------------------------------------------------------------------- PROPAGATION DELAY ANALYSIS ------------------------------ Although propagation delay times had been calculated before production, an actual test was necessary to determine the tolerance of the projected delay times. For this, the MTG was used utilizing two of the many available timing signals; Namely the standard clock frequency and a signal at half the clock frequency to provide the operand data. An oscilloscope, monitoring both input and output signals simultaneously, was used to measure the delay. All connections and test leads were kept as short as possible, so as not to introduce any further delays and produce misleading results. The procedure was as follows: 1. Relevant data was put on the inputs of all the operands, all operands receiving the same logical value. This was done to insure all carry situations would be exercised. 2. These were then "latched" using the clock signal. 3. The resulting output was compared to the rising edge of the clock signal used to latch the data input, resulting in Tpd, the propogation delay. 4. The procedure was repeated using alternating logic values as data. RESULTS: Delay times were determined for the following quantities: 1. Partial Sum 2. Final Sum 3. Comparator 4. Resulting Carrys, tracing worst-case paths Maximum, minimum, and nominal values are given as: QUANTITY MAXIMUM MINIMUM NOMIMAL --------------------------------------------------------------- Partial Sum 25 nS 25 nS 25 nS Final Sum 28 nS 26 nS 27 nS Comparator 31 nS 30 nS 31 nS Carry(s) 32 nS 31 nS 32 nS