---------------------------------------------------------------- ! ! ! D0 FIRST LEVEL TRIGGER SYSTEM CALORIMETER ADDER TREE CARD ! ! TYPE 3 ! ---------------------------------------------------------------- Michigan State University - 21-JAN-1991 fix programming info: 22-MAR-1991 update timing info: 18-APR-1991 fix programming info: 15-MAY-1991 add Partial Sum ECO: 18-SEP-1991 inverted comparator outputs: 30-JAN-1992 add Final Sum ECO: 26-MAY-1992 Drawing Number Change: 28-SEP-1992 add Sign-Extension Notes: 9-FEB-1993 correct Sign-Extension Notes: 12-AUG-1993 GENERAL DESCRIPTION The CAT3 card is found in the Third Tier of all Adder Trees. There is only one Third Tier backplane, with 16 CAT3's. The inputs to these cards are the corrected outputs from the Second Tier of the Adder Trees. The outputs are the final, corrected sum for the event. The CAT3 operand inputs are differential ECL and may be 0 to 16 bits in length. All operand inputs are terminated on card. Unused inputs or unused bits of an input default to logical 0. Each operand input is then latched. These latches are activated by timing signal H. By design these latches may be selected at the time of assembly to be either the 100150 transparent latches or the 100151 edge triggered latches. A board with the 100150 transparent latches may be used asynchronously as a fast ripple adder. When used in that manner a CAT3 card requires that timing signal H be held low. A board with the 100151 edge triggered latches may be used in a synchronous clocked system. In a clocked system the data set up at the 100151 inputs is latched on the rising edge of timing signal H. In either case the input operands may be latched for computer bus readout to be used in system testing. The outputs of the transparent latches are fed to an adder tree which produces the sum of the 6 input operands. The sum produced is 19 bits wide. The 19 bit sum is fed to four 19 bit magnitude comparators. Each magnitude comparator has a computer loadable register for its other input. The sum may thus be compared to 4 predetermined thresholds. The 'less than' outputs of these comparators is converted to differential ECL, and driven off card directly. NOTE THAT THIS IS DIFFERENT FROM THE BEHAVIOR OF A CAT2 CARD, WHICH PROVIDES A 'GREATER THAN OR EQUAL TO' SIGNAL. The output of the CAT3 is thus INVERTED with respect to the output of the CAT2. The 19 bit sum is also converted to differential ECL and driven off card. Following the comparators the 19 bit sum is sent to a final adder where a two's complement number, computer loaded into a register may be added to the sum. Thus the 19 bit sum may be corrected to a 24 bit result. All 24 bits of this final adder are output as differential ECL. An important difference between the CAT2 and the CAT3 cards is the lack of an "asynchronous reset" input for the CAT3. This omission is justified by two reasons: o The "asynchronous reset" function is not completely given up, in that the CAT3 is fed by a CAT2, which still has this function o It is not really needed in a CAT3 because it was always thought to be a way to perform different functions for First Lookup and Second Lookup, which are de-multiplexed for the CAT3 The accelerator RF system operates at a frequency of 53.104 MHz. This gives the time of an RF period to be 18.831 nanoseconds. At maximum luminosity the closest bunch to bunch spacing will be every 7th RF bucket. This is based on the information that are 1113 RF buckets in the accelerator and that the maximum fill is 144 bunches. This gives the shortest bunch to bunch time spacing of 131.82 nanoseconds. During this period the First Level Calorimeter Trigger System Adder Tree will need to cycle two times. Note that each CAT3 only provides one sum (this is where the First Lookup/Second Lookup time demultiplexing takes place), however, the Second Lookup CAT3's still must respond before the end of the cycle. Thus the period available for a CAT3 Card to cycle is 65.91 nanoseconds. The First Level Calorimeter Trigger is be designed so that all CAT3 Card cycles will be of equal length (i.e. during a period of 7 RF buckets there will NOT be a short cycle followed by a long cycle). The following table summarizes the timing delays for the CAT3 card at 25 degrees. running running minimum minimum maximum maximum Operand Input Setup Time operand rcv & latch 100114 0.6 ns 2.4 ns 100151 0.8 ns 2.4 ns -------- -------- subtotal 1.4 ns 1.4 ns 4.8 ns 4.8 ns Adder Tree Delay Time first adder stage delay 100180 1.4 ns 3.8 ns + 100179 1.1 ns 2.9 ns + 100180 1.1 ns 3.9 ns -------- -------- subtotal: 3.6 ns 5.0 ns 10.6 ns 15.4 ns subsequent adder stages 100180 1.4 ns 3.8 ns + 100179 1.1 ns 2.9 ns + 100180 1.1 ns 3.9 ns -------- -------- subtotal (1) 3.6 ns 10.6 ns subtotal (3) 10.8 ns 15.8 ns 31.8 ns 47.2 ns output buffer stage 100114 0.6 ns 16.4 ns 2.4 ns 49.6 ns -------------------------------------------------------------- total 16.4 ns 49.6 ns Comparator Delay Time adder stages delay 12.2 ns 12.2 ns 36.6 ns 36.6 ns delay through comparator 100166 1.4 ns 3.5 ns +100166 1.4 ns 3.5 ns +100166 1.4 ns 3.5 ns -------- -------- subtotal 4,2 ns 16.4 ns 10.5 ns 47.1 ns output buffer stage 100114 0.6 ns 17.0 ns 2.4 ns 49.5 ns -------------------------------------------------------------- total 17.0 ns 49.5 ns Note there is a non corrected output available one adder stage delay earlier than the corrected output ie at 39.0 ns. The CAT3 must deal with two types of input: either 15-bit wide unsigned integers (EM, HD, +Px, +Py), or 16-bit 2's complement signed integers (-Px, -Py coming out of Tier 2 will be converted from 15-bit unsigned integers to 16-bit 2's complement with the CAT2 correction register & a polarity-inverting cable). However, it will be made primarily of 18-bit adder sections. Therefore, bits 16, 17, and 18 (the 3 MSB) must be tied together, to provide sign-extension from 16 bits to 18 bits. This is required because the 2nd stage adder would otherwise be adding a 16-bit signed number to a 17-bit signed number, providing an erroneous result. See the CAT3 block diagram. The Correction Stage adder must then be 19-bits wide. This requires a 24-bit adder (4, 6-bit adders). The carry out of the 3rd stage adder must be inverted (it is active-low) and fed to bits 19-24 (the 6 MSB) of the Correction Stage Adder. This provides a 24-bit, sign-extended 2's complement result after the correction stage (the correction register must be loaded with a 24-bit, sign-extended 2's complement value as well). Finally, for maximum generality, it would be ideal to allow 16-bit unsigned integers as input. This is done by using a jumper for the sign-extension described above. That is, on the 1st stage, input bit 16 will go to adder bit 16, while 17 and 18 will be tied together and jumpered to 16. In second stage, the output of the 1st stage adder will flow through directly, while the 16-bit input (from the input latches) will receive the treatment described above. The 3rd stage will have all 18 bits wired directly. The Correction Stage will have the carry out from stage 3 flow (inverted) to input bit 19, bits 20-24 will be tied together, and jumpered to 19. PROGRAMMING The CAT3 card has 16 read only registers used to read the value of the 16 bit input operands and 20 read/write registers used to load the magnitude comparison registers and the correction register. The 16 read only registers occupy Function Addresses 0 through 15. Three or four Function Addresses are used for each 16 bit operand, with a Function Address occasionally "split" between two operands. Four read/write registers, used for the correction register, occupy Function Addresses 48 through 51. They hold the 24 bit correction value. Sixteen read/write registers, located at Function Addresses 16-19, 24-27, 32-35, and 40-43, hold the threshold comparison values. Four Function Addresses are used for each 19 bit value. Note that there are five "extra bits" in the most significant (6-bit) byte of each threshold comparison input. Three of these bits are used to feed-back the comparator outputs to the CBUS. Also note that the comparator register and correction register bytes are NOT mapped in monotonically increasing Function Address order, but are "scrambled" as described in the table below. Additionally, note that the contents of Function Addresses 20-23, 28-31, 36-39, 44-47, and 52-55 are duplications of the contents of Function Addresses 16-19, 24-27, 32-35, 40-43, and 48-51 respectively. The Function Address allocation is summarized in the table below. Function Address Read Function --------------------------------------------------------------- 0 read input operand latch 1 bits 0- 5 1 read input operand latch 1 bits 6-11 2 read input operand latch 1 bits 12-15 and operand 2 bits 0- 1 3 read input operand latch 2 bits 2- 7 4 read input operand latch 2 bits 8-13 5 read input operand latch 2 bits 14-15 and operand 3 bits 0- 3 6 read input operand latch 3 bits 4- 9 7 read input operand latch 3 bits 10-15 8 read input operand latch 4 bits 0- 5 9 read input operand latch 4 bits 6-11 10 read input operand latch 4 bits 12-15 and operand 5 bits 0- 1 11 read input operand latch 5 bits 2- 7 12 read input operand latch 5 bits 8-13 13 read input operand latch 5 bits 14-15 and operand 6 bits 0- 3 14 read input operand latch 6 bits 4- 9 15 read input operand latch 6 bits 10-15 16 read comparator register 1 bits 6-11 17 read comparator register 1 bit 18 and comparator 1 output bits 18 read comparator register 1 bits 12-17 19 read comparator register 1 bits 0- 5 24 read comparator register 2 bits 6-11 25 read comparator register 2 bit 18 and comparator 2 output bits 26 read comparator register 2 bits 12-17 27 read comparator register 2 bits 0- 5 32 read comparator register 3 bits 6-11 33 read comparator register 3 bit 18 and comparator 3 output bits 34 read comparator register 3 bits 12-17 35 read comparator register 3 bits 0- 5 40 read comparator register 4 bits 6-11 41 read comparator register 4 bit 18 and comparator 4 output bits 42 read comparator register 4 bits 12-17 43 read comparator register 4 bits 0- 5 48 read correction register bits 6-11 49 read correction register bits 18-23 50 read correction register bits 12-17 51 read correction register bits 0- 5 The CAT2 uses 6-bit registers, NOT 8-bit registers. The upper two bits of each register will always be set to 0. Note that Function Addresses 17, 25, 33, and 41 contain the following information: Bit Contents --- -------- (8) Zero (7) Zero 6 1: Partial sum < Comparator n (0: PS >=C) 5 1: Partial sum > Comparator n (0: PS <= C) 4 1: Partial sum <> Comparator n (0: PS = C) 3 Zero 2 Zero 1 Comparator n data bit 18 Note that the comparator read-back bits (4-6) are used identically on the CAT3 and the CAT2. Function Address Write Function ---------------------------------------------------------------- 16 write comparator register 1 bits 6-11 17 write comparator register 1 bit 18 18 write comparator register 1 bits 12-17 19 write comparator register 1 bits 0- 5 24 write comparator register 2 bits 6-11 25 write comparator register 2 bit 18 26 write comparator register 2 bits 12-17 27 write comparator register 2 bits 0- 5 32 write comparator register 3 bits 6-11 33 write comparator register 3 bit 18 34 write comparator register 3 bits 12-17 35 write comparator register 3 bits 0- 5 40 write comparator register 4 bits 6-11 41 write comparator register 4 bit 18 42 write comparator register 4 bits 12-17 43 write comparator register 4 bits 0- 5 48 write correction register bits 6-11 49 write correction register bits 18-23 50 write correction register bits 12-17 51 write correction register bits 0- 5 There is one DIP switch, S1, to select the Card Address Finally, there are three front panel connectors: o J13 is a 50-position connector to drive the Partial Sum off-card o J14 is a 50-position connector to drive the Final Sum off-card o J15 is a 16-position connector to drive the Comparator outputs off card. Note that the comparator outputs are inverted with respect to the CAT2 J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 1 Bit 1 Inverted IN IIO1.1 34 Input Operand 1 Bit 2 Inverted IN IIO1.2 35 Input Operand 1 Bit 3 Inverted IN IIO1.3 36 Input Operand 1 Bit 4 Inverted IN IIO1.4 37 Input Operand 1 Bit 5 Inverted IN IIO1.5 38 Input Operand 1 Bit 6 Inverted IN IIO1.6 39 Input Operand 1 Bit 7 Inverted IN IIO1.7 40 Input Operand 1 Bit 8 Inverted IN IIO1.8 41 Input Operand 1 Bit 9 Inverted IN IIO1.9 42 Input Operand 1 Bit 10 Inverted IN IIO1.10 43 Input Operand 1 Bit 11 Inverted IN IIO1.11 44 Input Operand 1 Bit 12 Inverted IN IIO1.12 45 Input Operand 1 Bit 13 Inverted IN IIO1.13 46 Input Operand 1 Bit 14 Inverted IN IIO1.14 47 Input Operand 1 Bit 15 Inverted IN IIO1.15 48 Input Operand 1 Bit 16 Inverted IN IIO1.16 49 Input Operand 2 Bit 1 Inverted IN IIO2.1 50 Input Operand 2 Bit 2 Inverted IN IIO2.2 51 Input Operand 2 Bit 3 Inverted IN IIO2.3 52 Input Operand 2 Bit 4 Inverted IN IIO2.4 53 Input Operand 2 Bit 5 Inverted IN IIO2.5 54 Input Operand 2 Bit 6 Inverted IN IIO2.6 55 Input Operand 2 Bit 7 Inverted IN IIO2.7 56 Input Operand 2 Bit 8 Inverted IN IIO2.8 57 Input Operand 2 Bit 9 Inverted IN IIO2.9 58 Input Operand 2 Bit 10 Inverted IN IIO2.10 59 Input Operand 2 Bit 11 Inverted IN IIO2.11 60 Input Operand 2 Bit 12 Inverted IN IIO2.12 61 Input Operand 2 Bit 13 Inverted IN IIO2.13 62 Input Operand 2 Bit 14 Inverted IN IIO2.14 63 Input Operand 2 Bit 15 Inverted IN IIO2.15 64 Input Operand 2 Bit 16 Inverted IN IIO2.16 65 Input Operand 1 Bit 1 Non-inverted IN NIO1.1 66 Input Operand 1 Bit 2 Non-inverted IN NIO1.2 67 Input Operand 1 Bit 3 Non-inverted IN NIO1.3 68 Input Operand 1 Bit 4 Non-inverted IN NIO1.4 69 Input Operand 1 Bit 5 Non-inverted IN NIO1.5 70 Input Operand 1 Bit 6 Non-inverted IN NIO1.6 71 Input Operand 1 Bit 7 Non-inverted IN NIO1.7 72 Input Operand 1 Bit 8 Non-inverted IN NIO1.8 73 Input Operand 1 Bit 9 Non-inverted IN NIO1.9 74 Input Operand 1 Bit 10 Non-inverted IN NIO1.10 75 Input Operand 1 Bit 11 Non-inverted IN NIO1.11 76 Input Operand 1 Bit 12 Non-inverted IN NIO1.12 77 Input Operand 1 Bit 13 Non-inverted IN NIO1.13 78 Input Operand 1 Bit 14 Non-inverted IN NIO1.14 79 Input Operand 1 Bit 15 Non-inverted IN NIO1.15 80 Input Operand 1 Bit 16 Non-inverted IN NIO1.16 81 Input Operand 2 Bit 1 Non-inverted IN NIO2.1 82 Input Operand 2 Bit 2 Non-inverted IN NIO2.2 83 Input Operand 2 Bit 3 Non-inverted IN NIO2.3 84 Input Operand 2 Bit 4 Non-inverted IN NIO2.4 85 Input Operand 2 Bit 5 Non-inverted IN NIO2.5 86 Input Operand 2 Bit 6 Non-inverted IN NIO2.6 87 Input Operand 2 Bit 7 Non-inverted IN NIO2.7 88 Input Operand 2 Bit 8 Non-inverted IN NIO2.8 89 Input Operand 2 Bit 9 Non-inverted IN NIO2.9 90 Input Operand 2 Bit 10 Non-inverted IN NIO2.10 91 Input Operand 2 Bit 11 Non-inverted IN NIO2.11 92 Input Operand 2 Bit 12 Non-inverted IN NIO2.12 93 Input Operand 2 Bit 13 Non-inverted IN NIO2.13 94 Input Operand 2 Bit 14 Non-inverted IN NIO2.14 95 Input Operand 2 Bit 15 Non-inverted IN NIO2.15 96 Input Operand 2 Bit 16 Non-inverted IN NIO2.16 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 3 Bit 1 Inverted IN IIO3.1 34 Input Operand 3 Bit 2 Inverted IN IIO3.2 35 Input Operand 3 Bit 3 Inverted IN IIO3.3 36 Input Operand 3 Bit 4 Inverted IN IIO3.4 37 Input Operand 3 Bit 5 Inverted IN IIO3.5 38 Input Operand 3 Bit 6 Inverted IN IIO3.6 39 Input Operand 3 Bit 7 Inverted IN IIO3.7 40 Input Operand 3 Bit 8 Inverted IN IIO3.8 41 Input Operand 3 Bit 9 Inverted IN IIO3.9 42 Input Operand 3 Bit 10 Inverted IN IIO3.10 43 Input Operand 3 Bit 11 Inverted IN IIO3.11 44 Input Operand 3 Bit 12 Inverted IN IIO3.12 45 Input Operand 3 Bit 13 Inverted IN IIO3.13 46 Input Operand 3 Bit 14 Inverted IN IIO3.14 47 Input Operand 3 Bit 15 Inverted IN IIO3.15 48 Input Operand 3 Bit 16 Inverted IN IIO3.16 49 Input Operand 4 Bit 1 Inverted IN IIO4.1 50 Input Operand 4 Bit 2 Inverted IN IIO4.2 51 Input Operand 4 Bit 3 Inverted IN IIO4.3 52 Input Operand 4 Bit 4 Inverted IN IIO4.4 53 Input Operand 4 Bit 5 Inverted IN IIO4.5 54 Input Operand 4 Bit 6 Inverted IN IIO4.6 55 Input Operand 4 Bit 7 Inverted IN IIO4.7 56 Input Operand 4 Bit 8 Inverted IN IIO4.8 57 Input Operand 4 Bit 9 Inverted IN IIO4.9 58 Input Operand 4 Bit 10 Inverted IN IIO4.10 59 Input Operand 4 Bit 11 Inverted IN IIO4.11 60 Input Operand 4 Bit 12 Inverted IN IIO4.12 61 Input Operand 4 Bit 13 Inverted IN IIO4.13 62 Input Operand 4 Bit 14 Inverted IN IIO4.14 63 Input Operand 4 Bit 15 Inverted IN IIO4.15 64 Input Operand 4 Bit 16 Inverted IN IIO4.16 65 Input Operand 3 Bit 1 Non-inverted IN NIO3.1 66 Input Operand 3 Bit 2 Non-inverted IN NIO3.2 67 Input Operand 3 Bit 3 Non-inverted IN NIO3.3 68 Input Operand 3 Bit 4 Non-inverted IN NIO3.4 69 Input Operand 3 Bit 5 Non-inverted IN NIO3.5 70 Input Operand 3 Bit 6 Non-inverted IN NIO3.6 71 Input Operand 3 Bit 7 Non-inverted IN NIO3.7 72 Input Operand 3 Bit 8 Non-inverted IN NIO3.8 73 Input Operand 3 Bit 9 Non-inverted IN NIO3.9 74 Input Operand 3 Bit 10 Non-inverted IN NIO3.10 75 Input Operand 3 Bit 11 Non-inverted IN NIO3.11 76 Input Operand 3 Bit 12 Non-inverted IN NIO3.12 77 Input Operand 3 Bit 13 Non-inverted IN NIO3.13 78 Input Operand 3 Bit 14 Non-inverted IN NIO3.14 79 Input Operand 3 Bit 15 Non-inverted IN NIO3.15 80 Input Operand 3 Bit 16 Non-inverted IN NIO3.16 81 Input Operand 4 Bit 1 Non-inverted IN NIO4.1 82 Input Operand 4 Bit 2 Non-inverted IN NIO4.2 83 Input Operand 4 Bit 3 Non-inverted IN NIO4.3 84 Input Operand 4 Bit 4 Non-inverted IN NIO4.4 85 Input Operand 4 Bit 5 Non-inverted IN NIO4.5 86 Input Operand 4 Bit 6 Non-inverted IN NIO4.6 87 Input Operand 4 Bit 7 Non-inverted IN NIO4.7 88 Input Operand 4 Bit 8 Non-inverted IN NIO4.8 89 Input Operand 4 Bit 9 Non-inverted IN NIO4.9 90 Input Operand 4 Bit 10 Non-inverted IN NIO4.10 91 Input Operand 4 Bit 11 Non-inverted IN NIO4.11 92 Input Operand 4 Bit 12 Non-inverted IN NIO4.12 93 Input Operand 4 Bit 13 Non-inverted IN NIO4.13 94 Input Operand 4 Bit 14 Non-inverted IN NIO4.14 95 Input Operand 4 Bit 15 Non-inverted IN NIO4.15 96 Input Operand 4 Bit 16 Non-inverted IN NIO4.16 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Input Operand 5 Bit 1 Inverted IN IIO5.1 34 Input Operand 5 Bit 2 Inverted IN IIO5.2 35 Input Operand 5 Bit 3 Inverted IN IIO5.3 36 Input Operand 5 Bit 4 Inverted IN IIO5.4 37 Input Operand 5 Bit 5 Inverted IN IIO5.5 38 Input Operand 5 Bit 6 Inverted IN IIO5.6 39 Input Operand 5 Bit 7 Inverted IN IIO5.7 40 Input Operand 5 Bit 8 Inverted IN IIO5.8 41 Input Operand 5 Bit 9 Inverted IN IIO5.9 42 Input Operand 5 Bit 10 Inverted IN IIO5.10 43 Input Operand 5 Bit 11 Inverted IN IIO5.11 44 Input Operand 5 Bit 12 Inverted IN IIO5.12 45 Input Operand 5 Bit 13 Inverted IN IIO5.13 46 Input Operand 5 Bit 14 Inverted IN IIO5.14 47 Input Operand 5 Bit 15 Inverted IN IIO5.15 48 Input Operand 5 Bit 16 Inverted IN IIO5.16 49 Input Operand 6 Bit 1 Inverted IN IIO6.1 50 Input Operand 6 Bit 2 Inverted IN IIO6.2 51 Input Operand 6 Bit 3 Inverted IN IIO6.3 52 Input Operand 6 Bit 4 Inverted IN IIO6.4 53 Input Operand 6 Bit 5 Inverted IN IIO6.5 54 Input Operand 6 Bit 6 Inverted IN IIO6.6 55 Input Operand 6 Bit 7 Inverted IN IIO6.7 56 Input Operand 6 Bit 8 Inverted IN IIO6.8 57 Input Operand 6 Bit 9 Inverted IN IIO6.9 58 Input Operand 6 Bit 10 Inverted IN IIO6.10 59 Input Operand 6 Bit 11 Inverted IN IIO6.11 60 Input Operand 6 Bit 12 Inverted IN IIO6.12 61 Input Operand 6 Bit 13 Inverted IN IIO6.13 62 Input Operand 6 Bit 14 Inverted IN IIO6.14 63 Input Operand 6 Bit 15 Inverted IN IIO6.15 64 Input Operand 6 Bit 16 Inverted IN IIO6.16 65 Input Operand 5 Bit 1 Non-inverted IN NIO5.1 66 Input Operand 5 Bit 2 Non-inverted IN NIO5.2 67 Input Operand 5 Bit 3 Non-inverted IN NIO5.3 68 Input Operand 5 Bit 4 Non-inverted IN NIO5.4 69 Input Operand 5 Bit 5 Non-inverted IN NIO5.5 70 Input Operand 5 Bit 6 Non-inverted IN NIO5.6 71 Input Operand 5 Bit 7 Non-inverted IN NIO5.7 72 Input Operand 5 Bit 8 Non-inverted IN NIO5.8 73 Input Operand 5 Bit 9 Non-inverted IN NIO5.9 74 Input Operand 5 Bit 10 Non-inverted IN NIO5.10 75 Input Operand 5 Bit 11 Non-inverted IN NIO5.11 76 Input Operand 5 Bit 12 Non-inverted IN NIO5.12 77 Input Operand 5 Bit 13 Non-inverted IN NIO5.13 78 Input Operand 5 Bit 14 Non-inverted IN NIO5.14 79 Input Operand 5 Bit 15 Non-inverted IN NIO5.15 80 Input Operand 5 Bit 16 Non-inverted IN NIO5.16 81 Input Operand 6 Bit 1 Non-inverted IN NIO6.1 82 Input Operand 6 Bit 2 Non-inverted IN NIO6.2 83 Input Operand 6 Bit 3 Non-inverted IN NIO6.3 84 Input Operand 6 Bit 4 Non-inverted IN NIO6.4 85 Input Operand 6 Bit 5 Non-inverted IN NIO6.5 86 Input Operand 6 Bit 6 Non-inverted IN NIO6.6 87 Input Operand 6 Bit 7 Non-inverted IN NIO6.7 88 Input Operand 6 Bit 8 Non-inverted IN NIO6.8 89 Input Operand 6 Bit 9 Non-inverted IN NIO6.9 90 Input Operand 6 Bit 10 Non-inverted IN NIO6.10 91 Input Operand 6 Bit 11 Non-inverted IN NIO6.11 92 Input Operand 6 Bit 12 Non-inverted IN NIO6.12 93 Input Operand 6 Bit 13 Non-inverted IN NIO6.13 94 Input Operand 6 Bit 14 Non-inverted IN NIO6.14 95 Input Operand 6 Bit 15 Non-inverted IN NIO6.15 96 Input Operand 6 Bit 16 Non-inverted IN NIO6.16 ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 TSS H Operand Latch Clk Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 TSS H Operand Latch Clk Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 ------------------------------------------------------------------------------ J13: FIRST LEVEL CALORIMETER TRIGGER CAT3 PARTIAL SUM CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Partial Sum Bit 1 Non-inverted OUT 1 NPS1 2 Partial Sum Bit 1 Inverted OUT 2 IPS1 3 Partial Sum Bit 2 Non-inverted OUT 1 NPS2 4 Partial Sum Bit 2 Inverted OUT 2 IPS2 5 Partial Sum Bit 3 Non-inverted OUT 1 NPS3 6 Partial Sum Bit 3 Inverted OUT 2 IPS3 7 Partial Sum Bit 4 Non-inverted OUT 1 NPS4 8 Partial Sum Bit 4 Inverted OUT 2 IPS4 9 Partial Sum Bit 5 Non-inverted OUT 1 NPS5 10 Partial Sum Bit 5 Inverted OUT 2 IPS5 11 Partial Sum Bit 6 Non-inverted OUT 1 NPS6 12 Partial Sum Bit 6 Inverted OUT 2 IPS6 13 Partial Sum Bit 7 Non-inverted OUT 1 NPS7 14 Partial Sum Bit 7 Inverted OUT 2 IPS7 15 Partial Sum Bit 8 Non-inverted OUT 1 NPS8 16 Partial Sum Bit 8 Inverted OUT 2 IPS8 17 Partial Sum Bit 9 Non-inverted OUT 1 NPS9 18 Partial Sum Bit 9 Inverted OUT 2 IPS9 19 Partial Sum Bit 10 Non-inverted OUT 1 NPS10 20 Partial Sum Bit 10 Inverted OUT 2 IPS10 21 Partial Sum Bit 11 Non-inverted OUT 1 NPS11 22 Partial Sum Bit 11 Inverted OUT 2 IPS11 23 Partial Sum Bit 12 Non-inverted OUT 1 NPS12 24 Partial Sum Bit 12 Inverted OUT 2 IPS12 25 Partial Sum Bit 13 Non-inverted OUT 1 NPS13 26 Partial Sum Bit 13 Inverted OUT 2 IPS13 27 Partial Sum Bit 14 Non-inverted OUT 1 NPS14 28 Partial Sum Bit 14 Inverted OUT 2 IPS14 29 Partial Sum Bit 15 Non-inverted OUT 1 NPS15 30 Partial Sum Bit 15 Inverted OUT 2 IPS15 31 Partial Sum Bit 16 Non-inverted OUT 1 NPS16 32 Partial Sum Bit 16 Inverted OUT 2 IPS16 33 Partial Sum Bit 17 Non-inverted OUT 1 NPS17 34 Partial Sum Bit 17 Inverted OUT 2 IPS17 35 Partial Sum Bit 18 Non-inverted OUT 1 NPS18 36 Partial Sum Bit 18 Inverted OUT 2 IPS18 37 Partial Sum Bit 19 Non-inverted OUT 1 NPS19 38 Partial Sum Bit 19 Inverted OUT 2 IPS19 39 Unused 40 Unused 41 Unused 42 Unused 43 Unused 44 Unused 45 Unused 46 Unused 47 Unused 48 Unused 49 Unused 50 Unused ------------------------------------------------------------------------------ J14: FIRST LEVEL CALORIMETER TRIGGER CAT3 PARTIAL SUM CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Final Sum Bit 1 Non-inverted OUT 1 NFS1 2 Final Sum Bit 1 Inverted OUT 2 IFS1 3 Final Sum Bit 2 Non-inverted OUT 1 NFS2 4 Final Sum Bit 2 Inverted OUT 2 IFS2 5 Final Sum Bit 3 Non-inverted OUT 1 NFS3 6 Final Sum Bit 3 Inverted OUT 2 IFS3 7 Final Sum Bit 4 Non-inverted OUT 1 NFS4 8 Final Sum Bit 4 Inverted OUT 2 IFS4 9 Final Sum Bit 5 Non-inverted OUT 1 NFS5 10 Final Sum Bit 5 Inverted OUT 2 IFS5 11 Final Sum Bit 6 Non-inverted OUT 1 NFS6 12 Final Sum Bit 6 Inverted OUT 2 IFS6 13 Final Sum Bit 7 Non-inverted OUT 1 NFS7 14 Final Sum Bit 7 Inverted OUT 2 IFS7 15 Final Sum Bit 8 Non-inverted OUT 1 NFS8 16 Final Sum Bit 8 Inverted OUT 2 IFS8 17 Final Sum Bit 9 Non-inverted OUT 1 NFS9 18 Final Sum Bit 9 Inverted OUT 2 IFS9 19 Final Sum Bit 10 Non-inverted OUT 1 NFS10 20 Final Sum Bit 10 Inverted OUT 2 IFS10 21 Final Sum Bit 11 Non-inverted OUT 1 NFS11 22 Final Sum Bit 11 Inverted OUT 2 IFS11 23 Final Sum Bit 12 Non-inverted OUT 1 NFS12 24 Final Sum Bit 12 Inverted OUT 2 IFS12 25 Final Sum Bit 13 Non-inverted OUT 1 NFS13 26 Final Sum Bit 13 Inverted OUT 2 IFS13 27 Final Sum Bit 14 Non-inverted OUT 1 NFS14 28 Final Sum Bit 14 Inverted OUT 2 IFS14 29 Final Sum Bit 15 Non-inverted OUT 1 NFS15 30 Final Sum Bit 15 Inverted OUT 2 IFS15 31 Final Sum Bit 16 Non-inverted OUT 1 NFS16 32 Final Sum Bit 16 Inverted OUT 2 IFS16 33 Final Sum Bit 17 Non-inverted OUT 1 NFS17 34 Final Sum Bit 17 Inverted OUT 2 IFS17 35 Final Sum Bit 18 Non-inverted OUT 1 NFS18 36 Final Sum Bit 18 Inverted OUT 2 IFS18 37 Final Sum Bit 19 Non-inverted OUT 1 NFS19 38 Final Sum Bit 19 Inverted OUT 2 IFS19 39 Final Sum Bit 20 Non-inverted OUT 1 NFS20 40 Final Sum Bit 20 Inverted OUT 2 IFS20 41 Final Sum Bit 21 Non-inverted OUT 1 NFS21 42 Final Sum Bit 21 Inverted OUT 2 IFS21 43 Final Sum Bit 22 Non-inverted OUT 1 NFS22 44 Final Sum Bit 22 Inverted OUT 2 IFS22 45 Final Sum Bit 23 Non-inverted OUT 1 NFS23 46 Final Sum Bit 23 Inverted OUT 2 IFS23 47 Final Sum Bit 24 Non-inverted OUT 1 NFS24 48 Final Sum Bit 24 Inverted OUT 2 IFS24 49 Unused 50 Unused ------------------------------------------------------------------------------ J15 FIRST LEVEL CALORIMETER TRIGGER CAT3 COMPARATOR CONNECTOR ------------------------------------------------------------------------------ Pin Function Mnemonic ------------------------------------------------------------------------------ 1 Comparator 1 Less Than Non-inverted OUT 1 NGT1 2 Comparator 1 Less Than Inverted OUT 2 IGT1 3 Comparator 2 Less Than Non-inverted OUT 1 NGT2 4 Comparator 2 Less Than Inverted OUT 2 IGT2 5 Comparator 3 Less Than Non-inverted OUT 1 NGT3 6 Comparator 3 Less Than Inverted OUT 2 IGT3 7 Comparator 4 Less Than Non-inverted OUT 1 NGT4 8 Comparator 4 Less Than Inverted OUT 2 IGT4 9 Unused 10 Unused 11 Unused 12 Unused 13 Unused 14 Unused 15 Unused 16 Unused NOTE: The comparator outputs are 'Partial Sum < Threshold.' The 'Partial Sum >= Threshold' signal is simply the inversion of this signal. The signal of principal use is the 'Partial Sum >= Threshold' signal. ECO HISTORY ----------- -------------------- 1. Partial Sum Adder -------------------- A major problem was discovered in the logic circuit design of the CAT3 Rev A third stage adder. This problem is due to the attempted use of the F100180 6 Bit Adder chips in a ripple carry mode. The problem is in the highest order bits of the third stage adder. This is shown on page 29 of the CAT3 Rev A print sets. Because the F100180 6 Bit Adder chips are designed to be used with a Carry Lookahead Generator (F100179) the Carry In (Cn*) input does not effect the Carry Generate (G*) output (or the Carry Propagate P* output). The Carry In only affects the six Function Outputs (F0...F5). This makes sense because if the Carry In effected the Carry Generate output then the chip would be ripple carrying and thus it could not be controlled by a Lookahead Carry Generator for fast long word operation. The result of the attempt to use the F100180 in a ripple carry mode in the third stage adder on the CAT3 Rev A board is the following: 1. IF the higher order chip (i.e. bits 13 through 18) of the third stage adder is ready to carry (i.e. for each bit value of bits 13 through 18 there is one and only one input bit set high, either of operand A or of operand B) 2. AND IF for this third stage adder the low order chips (i.e. bits 1 through 12) have enough of their input bits set high so that the 100179 is generating a Carry output at the Cn+4 stage 3. THEN what you would expect is for the 100179's Cn+4 Output to ripple through the high order chip and cause the high order chip to "carry" (i.e. all of the high order chip's output bits 7...12 would go to the low state and this high order chip's Carry output would become active that is bit 19 would become logical High). 4. BUT the F100180 does not work this way. The Carry In to the high order adder chip causes all of its outputs to go logic Low but does not cause this high order adder chip's Carry Generate output to become active i.e. Bit 19 stays logic Low, no Carry Out is Generated. Recall that before this chip received an active Carry In all of its 6 Function Outputs where logic High. 5. THUS for this range of inputs (one and only one of each bit from 13 through 18 set High AND bits 1 through 12 generating a carry) the output of the third stage adder (Partial Sum) will be 262144 lower than it should be. NOTES: -------- 1. This logic design error does not cause a problem for CAT3 Rev A cards used in Tier 3 EM Adder Trees or Tier 3 HD Adder Trees. This problem only occurs when the CAT3 Rev A card is used in a Tier 3 Momentum Adder Tree or a Tier 3 (Tier 4) Total Adder Tree. Of all the CAT3 Rev A cards only 6 are used in these Tier 3 Momentum Adder Trees and Total Adder Trees. 2. The CAT2 Rev B card suffers from a similar problem on pages 24..27 of the schematic. The details of this problem and the solution can be found under CAT2 ECO in the CAT2 description. SOLUTION: ----------- 1. The Bit 19 from the third stage adder should become logic High when: EITHER the high order chip's Generate Garry output is active OR when the low order chip's Generate Carry output is active AND the high order chip's Carry Propagate output is active. Note many of these signals are active when at the lower voltage level. CIRCUIT BOARD WORK: (See Board Plots for Visual View) --------------------- 1. CUT: U115 pin 11 -- R171 pin 8 (cut comp. side trace between via and resistor pack pin) 2. ADD: U115 pin 11 -- R170 pin 8 (wire wrap wire from via noted above to resistor pack pin, on solder side) 3. ADD: U115 pin 11 -- U112 pin 12 (wire wrap wire from via noted above to IC pin, on solder side) 4. ADD: U112 pin 8 -- U116 pin 15 (wire wrap wire from via to IC pin, on solder side) 5. ADD: U112 pin 10 -- U112 pin 14 (wire wrap wire from IC pin to IC pin, on solder side) 6. ADD: U115 pin 10 -- R169 pin 8 (wire wrap wire from IC pin to resistor pack pin, on solder side) 7. ADD: R169 pin 8 -- U112 pin 13 (wire wrap wire from resistor pack pin to IC pin, on solder side) ------------------ 2. Final Sum Adder ------------------ A logic bug was discovered in the Final Sum Adder of the CAT3 card. The problem is that the carry Generate and carry Propagate from the next-to-the-most-significant 6-bit Adder (U132) to the Lookahead Carry Generator (U129) are SWAPPED. That is, the Generate from U132 goes to the pin that is appropriate for the Propagate on the U129 end, and vice-versa. This causes an incorrect Carry In to the most significant 6-bit Adder chip under some circumstances. SOLUTION -------- Cut the following traces: ------------------------ U 132 pin 10 to nearby via (solder side) U 132 pin 11 to via near U130 pin 11 (component side) Add the following white wires: ----------------------------- U 132 pin 10 to via near U130 pin 11 U 132 pin 11 to nearby via (formerly connected to U132 pin 10) ------------------------- 3. Sign-Extension Jumpers ------------------------- For proper operation of the CAT3 card in each of its possible environments, correct positioning of the sign-extension jumpers is essential. For details, see the file TRGHARD:[CAT3]CAT3_USAGE.TXT. Note that in one case, (Tier 3 Px, Py adder cards), the sign-extension jumper between the partial sum adder stage and the final sum adder stage must be put in a NON-STANDARD location. This jumper must connect bit 18 to bits 19-24 (rather than the standard connection of bit 19 to bits 20-24). This has been done as described below: Cut the following traces on the solder side ------------------------------------------- U116 pin 13 to J11 pin 1 P SUM BIT 19 to Jumper J11 R182 pin 4 to U133 pin 23 68 Ohm pull down for P SUM SGN EXT Add the following white wires ----------------------------- U132 pin 13 to J11 pin 1 P SUM BIT 18 to Jumper J11 U116 pin 13 to R175 pin 4 P SUM BIT 19 to 68 Ohm pull down Install the following jumper ---------------------------- J11 pin 1 to J11 pin 2 This ECO allows partial sum bit 19 to travel to the comparators and partial sum output driver, while feeding partial sum bit 18 to bits 18-24. Note that there are two pull-down resistors on partial sum bit 18, for a total of 34 ohms. The drivers are able to drive 25 ohm lines. Drawing Number Change 28-SEPT-1992 ------------------------------------- The Drawing Numbers for the CAT3 Rev A Card have been changed from: 3740.422-EC-224430-A through 3740.422-EC-224496 to: 3740.422-EC-294400-A through 3740.422-EC-294466 on 28-SEPT-1992.