+---------------------------------------------------------------+ | FIRST LEVEL TRIGGER | | CALORIMETER HOT TOWER COUNTING and REGISTERING CARD | +---------------------------------------------------------------+ Original: 21-JUNE-1990 Edited: 29-APR-2003 - Replace RefSet numbering #1..4 with #0..3 (but left the channel numbering one-based, left the bit numbering one-based, and left the pin "mnemonics" untouched) - Add Eta/Phi correspondance to register content GENERAL DESCRIPTION The Calorimeter Hot Tower Counting and Registering Card (CHTCR) performs four main functions called: i) the First Tier of the Hot Tower COUNTER TREES, ii) the first section of the FAST TRIGGER HINTS, iii) the JET PATTERN COLLECTOR, iv) the HOT TOWER REGISTERING. Other sections of the card provide connection to the rest of the system: v) the CBUS INTERFACE allows readout of the card during the Data Block Building Sequence, or data access by the control computer. vi) the TBUS INTERFACE allows readout of the card during the Hot Tower Table Building Sequence. vii) the 8 FIRST TIER COUNT DRIVER circuitry sending data to the second tier of the counter trees. viii) the FIRST TIER TRIGGER HINT DRIVER circuitry. Each EM Et and Total Et Trigger Tower energy is submitted to four Cluster Threshold Comparators (one for each Reference Set) located on the CTFE Cards. Each Cluster Threshold Comparator provides a single bit output: logical one if the Trigger Tower energy is above the Cluster Threshold, or logical zero if the Trigger Tower energy is below the Cluster Threshold. The CHTCR cards receive these signals from the Cluster Threshold Comparators. A CHTCR Card services 8 CTFE Cards. Thus a CHTCR Card receives: 4 Cluster Threshold Comparators x 2 signal types (EM Et or Total Et) x 4 Trigger Towers per CTFE Card x 8 CTFE Cards serviced each CHTCR Card --- 256 input signals to a CHTCR card These 256 Comparison Bits are all TTL level signals series terminated on the driving end. They are received with 74AS573 transparent latches. It is envisioned that in the 6x6 bunch mode of operation, the latches can remain in the transparent mode, while in high luminosity mode, the latches are provided with an Input Latch clock to latch the CTFE outputs while they are valid. These latches have approximately the same timing requirements as the 74AS574 D-type latches, and provide the benefit of the aforementioned transparent mode, not available with the 74AS574. There are 8 separate Counting Channels on a CHTCR card to handle all of the 8 threshold types called EM Et Cluster Thresholds for Reference Set #0, #1, #2, and #3, and Total Et Cluster Thresholds for Reference Set #0, #1, #2, and #3. They are organized as follows: Counting Channel# Threshold ----------------- --------- 1 EM Et Reference Set 0 2 EM Et Reference Set 1 3 EM Et Reference Set 2 4 EM Et Reference Set 3 5 Tot Et Reference Set 0 6 Tot Et Reference Set 1 7 Tot Et Reference Set 2 8 Tot Et Reference Set 3 All 8 Counting Channels include the logic for a First Tier of a Counter Tree, a Jet List Collector, and a Fast Trigger Hint circuitry. Only Counting Channel #1 (EM Et Threshold for Ref. Set. #0) channel has Hot Tower Registering circuitry. THE FIRST TIER OF THE COUNTER TREES The First Tier of the Counter Tree counts, for each channel, the Comparison Bits that were in a logical one state. Each output partial count is a 6 bit number forwarded to the second Tier CAT2 card of its Counter Tree. There are 8 separate Counter Trees with 8 separate sets of CAT2 cards, but a CHTCR card is common to all first tiers of the 8 counter trees. THE FIRST SECTION OF THE FAST TRIGGER HINTS On the CHTCR Card each of the 8 channels also includes a 32 input OR gate. The output of one of these OR gates will be high if at least one among the 32 Cluster Threshold Comparison Bits connected to this channel is a logical one. There are thus eight independent single bit outputs, one from each channel. The resulting signals form the 8 independent Fast Trigger Hints (this is in anticipation of an upgrading of the Tevatron to higher luminosity and higher interaction rate). They are neither pipelined nor double buffered since they are only useful as an aid to fast decision-making in the high luminosity/high interaction rate case. THE JET PATTERN COLLECTOR The CHTCR cards also provide information to the Jet List Builder software, which runs on a VME 68020 CPU board. This information is provided via the First Level Trigger Data Block. The patterns of Trigger Towers hit above each one of the 8 thresholds are constantly recorded in double buffered pipeline memories. The information concerning the beam crossing that induced a positive Level 1.0 Trigger Decision is read from these registers by the Data Block Builder. This information is processed by the 68020 Jet List processor which constructs the two Jet Lists that will be appended to the First Level Trigger Data Block before it is sent to the Level 2 Processor Farm. THE HOT TOWER REGISTERING CIRCUITRY Only the Counting Channel #1 (EM Et Threshold for Ref. Set. #0) has Hot Tower Registering circuitry. On the CHTCR card the 32 Comparison Bits coming from the EM Et Cluster Threshold for Ref. Set. #0 comparators also provide the input information to the Hot Tower Registering Circuitry. It prepares a list of towers to be included in the Hot Tower Table sent to the TRD Trigger as a list of candidates for a Level 1.5 confirmation. A Hot Tower Registering sequence will only be initiated for a beam crossing resulting in a succesful Level 1.0 Trigger Decision and if a Level 1.5 TRD Trigger confirmation was requested in the programming of a Level 1 Specific Trigger that fired. The Hot Tower Registering is performed by scanning the 32 Comparison Bits and recording in a FIFO the addresses of the Trigger Towers corresponding to Comparison Bits in a logical one state (i.e. the coordinates of the Trigger Towers having a deposit of energy greater than the EM Et Threshold for Ref. Set. #0). These are the Hot Towers. If no EM Tower was hit above this threshold no information will be recorded. In order to allow the pipelined operation of the Calorimeter Trigger at high luminosity, the state of the 32 Counting Channel #1 Comparison Bits must be memorised in a pipeline register at least 8 beam crossings long. The Hot Tower Table can thus be built based on the information corresponding to the beam crossing that caused the Level One Trigger Decision. The operation of the Registering circuitry is asynchronous from the operation of the Data Block Builder. A Hot Tower Table can be requested while the Data Block Builder is reading out information about a previous successful Trigger decision. Hence the Registering Circuitry cannot use the same pipeline as the Jet List and needs a private set of pipeline registers. This pipelined information does not need to be double buffered. All Level One Trigger activity is suspended between any Level 1.0 decision and its corresponding Level 1.5 decision. The information included in the Data Block comes from the Jet List pipelines, which are double buffered. This single buffered pipeline register is implemented to be 16 beam crossings long. The depth at which the information has to be retrieved from the pipeline is selectable on a dip switch. This depth depends on the luminosity in the collider and the overall organization of the pipelining of the Trigger System, but does not vary between beam crossings. Hot Tower Table Builder communication is performed on the Hot Tower Table Builder Bus (TBUS). Up to twelve CHTCR cards communicate with one Hot Tower Table Builder (HTTB) COMINT card on each separate TBUS. This bus contains the following signals: Signal Function Source ------ -------- ------ HT CYCLE: This signal is active during the COMINT entire Hot Tower Cycle window. The Hot Tower Circuitry is kept to a reset state when this signal is low. HT REG SEQ: This signal is active during the COMINT Hot Tower Registering Sequence. Its rising edge starts the Sequence. 6bits CARD ADD: These lines will select the address COMINT of the CHTCR card to be read out 2bits FUNC ADD: These lines will select the function COMINT address being read. Currently, only one function address per card is used. STROBE: This signal pulses to perform COMINT sequential FIFO readout of each CHTCR card. 8bits eta DATA: These lines will provide the ETA CHTCR coordinate of the registered towers. 7bits phi DATA: These lines will provide the PHI CHTCR coordinate of the registered towers. FIFO NOT EMPTY: This line will be negated by a CHTCR CHTCR card to terminate its readout. The complete Hot Tower Table Builder Cycle is composed of three phases: a Flushing phase clearing the FIFO of previous information, a Registering phase simultaneously performed by all CHTCR cards, and a Readout phase sequentially scanning the CHTCR cards. DETAILS OF THE HOT TOWER TABLE CYCLE: The Hot Tower Table Builder Cycle begins with the HTTB COMINT card first asserting HT CYCLE and (about 200ns later ) the HT REG SEQ signal. Upon receiving the HT CYCLE signal, the CHTCR will quit forcing the flip-flops to their reset state, and will quit preloading the counters. Flushing sequence: Upon receiving the HT REG SEQ signal, the CHTCR will start its Scan Counter. The first 16 steps of the count will address non-existent Comparison Bits, which will default to the high state. If the first addressed 16 locations in the PROMs are programmed with 0, the whole 16-deep TBUS pipeline register will be cleared. Two copies of the Hot Tower Table will be built. The flushing sequence little affects the copy sent to the TRD Trigger, but allows us to find the real Hot Towers within the block of address space scanned by the Data Block Builder (they will appear as the only non-zero data). The Flushing sequence is performed at the beginning of each Hot Tower Cycle. If it is desirable, the Flushing sequence can be applied to only the lower 8 levels of the pipe by selecting (via jumpers) a different preload value for the Scan Counter. A preload of 00010000=16 will clear all 16 levels, while a preload of 00011000=24 will clear only the lower 8. The Scan Counter must read 100000=32 at the last step of the Flushing sequence. The FIFO Counter on the CHTCR is preloaded with a value defined using a set of jumpers to either 00001111=15 (respectively 00010111=23) for 16- (respectively 8-) level deep Flushing sequence described above. This counter is incremented 16 times (respectively 8 times) during the Flushing sequence. At the end of the Flushing sequence and before the real Comparison Bits are scanned, the FIFO Counter must read 011111=31, the higher order bit being 0 indicates an empty FIFO. Registering sequence: The Registering sequence is controlled by two counters, the Scan counter and the FIFO Counter. Once the memory has been flushed, the Scan Counter will keep incrementing and will start addressing real Comparison Bits, searching for Hot Towers. This count will be used both to address the PROMs which generate the Tower coordinates and to scan through the 32 input bits of the Channel #1. The FIFO Counter and the pipeline register are not affected when a tower which was not hit above threshold is being scanned. For each Hot Tower found, the FIFO Counter is incremented and the PROM data (corresponding to the coordinates of the Hot Tower) is latched/shifted into the TBUS pipeline registers. For example, when the first tower is found, the FIFO Counter is incremented to 00100000=32. The higher order bit being 1 indicates a non-empty fifo, the lower 4 bits of the FIFO Counter now point to and will always follow the first tower registered while it is being shifted through the pipeline. In order to take best advantage of the clock cycle time and to minimize the time spent on the Registering sequence, the operation of the Registering circuitry is pipelined. When the Scan Counter reaches 32, the first real Comparison Bit is being addressed. At the next rising edge of the clock, this Comparison Bit is latched, and the Scan Counter now reads 33. This is also the new PROM address. If the Comparison Bit was in a logical one state, the data displayed by the PROM will be latched/shifted in the Am29525 at the next rising edge of the clock. An estimate of the timing of this operation is included in this document. The Hot Tower Address Mapping PROMs should thus be programmed as follows: ADDRESS CONTENT 0 coordinate of Tower #32 1 unused . . 16 unused 17 0 . . 32 0 33 coordinate of Tower #1 . . 32+n coordinate of Tower #n . . 63 coordinate of Tower #31 In fact the 2k x 8 PROMs used on the CHTCR can hold 32 such maps and the appropriate 2 sections are selected on two dip switches. Up to 16 Hot Towers can be registered. However, a maximum count in the range 0..15 is selected via a 4-bit DIP switch and is imposed on the FIFO Counter, limiting the number of towers each CHTCR card sends to the TRD Trigger to 1..16. Note that 0 is outside of this range, but the HTTB COMINT could be programmed to skip a CHTCR instead. This feature allows "fine tuning" of the maximum contribution of each card with respect to the maximum size of the list sent to the TRD trigger. After all 32 Towers have been scanned the Scan Counter stops counting but will only return to its preload value when HT REG SEQ is negated again. The FIFO Counter remains at its last value, which will be the address in the pipe of the first Hot Tower found (i.e. the deepest level of the pipe containing nonzero data). Note that LATCH/SHIFT signals during the Hot Tower Registering Sequence will cause the fixed-depth pipeline registers storing the private copy of the input towers to point at a beam crossing that DID NOT cause the Level 1.5 request. Therefore, LATCH/SHIFT signals to this card are disallowed during this sequence. Provisions have been made (jumper-selectable) to mask out the LATCH/SHIFT signal to these registers on the CHTCR card during the registering sequence, allowing the LATCH/SHIFT signal to continue running during this time. Readout phase: Now, the CHTCR must wait to be addressed by the HTTB COMINT card. When it is addressed, it will place the contents of the level of the pipe pointed to by the FIFO Counter (that is, the address of the first Hot Tower) on the TBUS data bus. It also drives FIFO NOT EMPTY to the correct state. The FIFO NOT EMPTY signal is driven either from the higher order bit of the Scan Counter as described above or from the bit #8 of the Phi Data byte (jumper-selectable). The HTTB COMINT bases its next actions on the state of FIFO NOT EMPTY. If asserted, the driven data is valid and is kept by the HTTB COMINT for examination by the TRD Trigger. Then the HTTB COMINT provides the STROBE pulse to the CHTCR. The STROBE causes the FIFO Counter to decrement and causes the contents of that next pipe level (the address of the next Hot Tower) to be placed on the data bus, and FIFO NOT EMPTY to be reevaluated. If, however, FIFO NOT EMPTY is negated, the driven data is invalid (in fact, it will be zero) and will be ignored. The HTTB COMINT will stop addressing this CHTCR, and interrogate the next CHTCR. Note that a CHTCR only responds to the STROBE signal when it is properly addressed, thus not being disturbed by the readout of the other CHTCR cards on the same TBUS. Timing Diagram: HOT ------------ ------------ ------------------------------ --- TOWER / ... ... ... \ TABLE -- -- CYCLE HOT -------- TOWER / \ ... ... ... REG --- -- ------------ ------------------------------ ------ SEQUENCE --------- --------- CARD ... / ... \ ... N ---------------- -- -------------------- ------ WAKEUP (2 towers) ------ CARD ... ... / \ ... N+1 ---------------- ------------ ------------- --------- ------ WAKEUP (0 towers) --------- ----- FIFO ... / ... \ ... NOT ---------------- -- ------------------------ ------ EMPTY MEM --- --- STROBE ... / \ ... / \ ... ---------------- ----- -- -- ----------------------- ------ ^^ ^ ^ ^ ^ ^ ^ ^ ^ || | | | | | | \ | /| all | non-empty strobe | |empty \ | / | CHTCR | FIFO, until | |FIFO, \ | / | have | strobe empty | |no strobe \ | HT | completed | for next | | | | cycle | Registering | data | start stop | begins| Sequence | | reading addressing | | | | card card n+1 | | | | n+1 | | | | | | start stop | | reading addressing | | card card n | | n | | | Registering Hot Tower Sequence Cycle Begins Ends THE CONTROL COMPUTER BUS INTERFACE There are no writable registers on a CHTCR card. This card needs more than the normal 8 bit function address space. In order to access more than 256 function addresses, two consecutive card addresses are used for each CHTCR card. In other words, the lowest card address line is used as a 9th function address line. The base address of the card must be EVEN. The state of the 256 latched Comparison Bits from the 8 serviced CTFE cards can be read by the Control Computer for the current and the last 7 beam crossings. This information is also double buffered. The 8 different Trigger Hint signals are also accessible through the Control Bus in a single 8 bit register. This information is not latched, nor double buffered, nor pipelined. A copy of the Hot Tower Addresses is recorded by the Registering Circuitry into a double buffered register. This register may be read by the Control Computer or the Data Block Builder at any time except during the Hot Tower Registering Sequence. This copy of the table can be double buffered (the selection is made with jumpers) but is not pipelined. If the Hot Tower Table is not double buffered, up to 16 Hot Tower Addresses can be accessed on CBUS. If the Hot Tower Table is double buffered the meaning of the control signal WRITE A/B received on the TSS bus can be inverted on two other sets of jumpers to allow the readout by the data block builder of the proper A/B pipe. The Hot Tower Table is indeed built after the normal swapping of the pipe A/B being written and while the the Data Block is being built but should be completed before the DBB has time to reach the CHTCR cards. The eight different 6 bit First Tier counts can not be read directly from the CHTCR card but may be read in the Second Tier of the Counter Trees (on the CAT2 cards). CHTCR REGISTER ADDRESSES AND CONTENTS ===================================== CARD FUNCTION ADDRESS ADDRESS BEAM CROSSING (base n=[0..7] -0 = current address (0: oldest -7 = oldest even) 7: current) REGISTER CONTENT p=preset(switch) ------- -------- ---------------- ------------- base 32n + 0 Counting Channel #1 Bits 1-8 - (7-n) LSB is Comparison Bit # 1, MSB is Bit # 8 Channel #1 is EM Ref Set #0. This byte corresponds to Relative Eta 0 : e.g. Eta=+1 for CHTCR covering Eta +1:+4, or Eta=-1 for CHTCR covering Eta -1:-4. LSB is Relative Phi 7, MSB is Rel Phi 0 : e.g. for CHTCR covering Phi 1:8 LSB is Phi 8, MSB is Phi 1. Caution: Phi order is different for EM and Tot Et base 32n + 1 Counting Channel #1 Bits 9-16 - (7-n) LSB is Comparison Bit # 9, MSB is Bit #16 base 32n + 2 Counting Channel #1 Bits 17-24 - (7-n) LSB is Comparison Bit #17, MSB is Bit #24 base 32n + 3 Counting Channel #1 Bits 25-32 - (7-n) LSB is Comparison Bit #25, MSB is Bit #32 This byte corresponds to Relative Eta 3 : e.g. Eta=+4 for CHTCR covering Eta +1:+4, or Eta=-4 for CHTCR covering Eta -1:-4. LSB is Relative Phi 7, MSB is Rel Phi 0 : e.g. for CHTCR covering Phi 1:8 LSB is Phi 8, MSB is Phi 1. base 32n + 4 Counting Channel #2 Bits 1-8 - (7-n) base 32n + 5 Counting Channel #2 Bits 9-16 - (7-n) base 32n + 6 Counting Channel #2 Bits 17-24 - (7-n) base 32n + 7 Counting Channel #2 Bits 25-32 - (7-n) Channel #2 is EM Ref Set #1. base 32n + 8 Counting Channel #3 Bits 1-8 - (7-n) base 32n + 9 Counting Channel #3 Bits 9-16 - (7-n) base 32n +10 Counting Channel #3 Bits 17-24 - (7-n) base 32n +11 Counting Channel #3 Bits 25-32 - (7-n) Channel #3 is EM Ref Set #2. base 32n +12 Counting Channel #4 Bits 1-8 - (7-n) base 32n +13 Counting Channel #4 Bits 9-16 - (7-n) base 32n +14 Counting Channel #4 Bits 17-24 - (7-n) base 32n +15 Counting Channel #4 Bits 25-32 - (7-n) Channel #4 is EM Ref Set #3. base 32n +16 Counting Channel #5 Bits 1-8 - (7-n) Channel #5 is Tot Ref Set #0. This byte corresponds to Relative Eta 0 : e.g. Eta=+1 for CHTCR covering Eta +1:+4, or Eta=-1 for CHTCR covering Eta -1:-4. LSB is Relative Phi 0, MSB is Rel Phi 7 : e.g. for CHTCR covering Phi 1:8 LSB is Phi 1, MSB is Phi 8. Caution: Phi order is different for EM and Tot Et base 32n +17 Counting Channel #5 Bits 9-16 - (7-n) base 32n +18 Counting Channel #5 Bits 17-24 - (7-n) base 32n +19 Counting Channel #5 Bits 25-32 - (7-n) This byte corresponds to Relative Eta 3 : e.g. Eta=+3 for CHTCR covering Eta +1:+4, or Eta=-3 for CHTCR covering Eta -1:-4. LSB is Relative Phi 0, MSB is Rel Phi 7 : e.g. for CHTCR covering Phi 1:8 LSB is Phi 1, MSB is Phi 8. base 32n +20 Counting Channel #6 Bits 1-8 - (7-n) base 32n +21 Counting Channel #6 Bits 9-16 - (7-n) base 32n +22 Counting Channel #6 Bits 17-24 - (7-n) base 32n +23 Counting Channel #6 Bits 25-32 - (7-n) Channel #6 is Tot Ref Set #1. base 32n +24 Counting Channel #7 Bits 1-8 - (7-n) base 32n +25 Counting Channel #7 Bits 9-16 - (7-n) base 32n +26 Counting Channel #7 Bits 17-24 - (7-n) base 32n +27 Counting Channel #7 Bits 25-32 - (7-n) Channel #7 is Tot Ref Set #2. base 32n +28 Counting Channel #8 Bits 1-8 - (7-n) base 32n +29 Counting Channel #8 Bits 9-16 - (7-n) base 32n +30 Counting Channel #8 Bits 17-24 - (7-n) base 32n +31 Counting Channel #8 Bits 25-32 - (7-n) Channel #8 is Tot Ref Set #3. base +1 0 Hot Tower #1 Eta Coordinate - p base +1 1 Hot Tower #1 Phi Coordinate - p base +1 2 Hot Tower #2 Eta Coordinate - p base +1 3 Hot Tower #2 Phi Coordinate - p base +1 4 Hot Tower #3 Eta Coordinate - p base +1 5 Hot Tower #3 Phi Coordinate - p base +1 6 Hot Tower #4 Eta Coordinate - p base +1 7 Hot Tower #4 Phi Coordinate - p base +1 8 Hot Tower #5 Eta Coordinate - p base +1 9 Hot Tower #5 Phi Coordinate - p base +1 10 Hot Tower #6 Eta Coordinate - p base +1 11 Hot Tower #6 Phi Coordinate - p base +1 12 Hot Tower #7 Eta Coordinate - p base +1 13 Hot Tower #7 Phi Coordinate - p base +1 14 Hot Tower #8 Eta Coordinate - p base +1 15 Hot Tower #8 Phi Coordinate - p base +1 16 - p . . Hot Tower #9-16 . . When not double buffered base +1 31 - p base +1 32 Fast Trigger Hint Byte - 0 Trigger Hint Bit# Contains ----------------- -------- 1 (LSB) EM Et Thresh. 1 Hint 2 EM Et Thresh. 2 Hint 3 EM Et Thresh. 3 Hint 4 EM Et Thresh. 4 Hint 5 Tot Et Thresh. 1 Hint 6 Tot Et Thresh. 2 Hint 7 Tot Et Thresh. 3 Hint 8 (MSB) Tot Et Thresh. 4 Hint base +1 17 . . unused . base +1 255 As an example, a routine to read EM Et Threshold Comparator for Reference Set #1 Bit 1, starting at the OLDEST beam crossing and continuing to the CURRENT beam crossing (i.e. a complete history of EM Et Threshold Comparator for Reference Set #0 Tower 1) would look like: MBDADD = mother board address CARDADD = base address M = 0 FOR N = 0, 7, 1 DO FUNCADD = (32*N) + M RESULT(N) = READ_REG(MBDADD, CARDADD, FUNCADD) NEXT N The low order bit of RESULT(N) then contains the state of EM Et Threshold Comparator #0 Tower 1 for each beam crossing (0 through 7). Another way to read data from the card is to hold the beam crossing depth constant, and read all (or a subset) of the Comparison Bits. The following routine will read all of the Comparison Bits from the CURRENT beam crossing (n=7): MBDADD = mother board address CARDADD = base address N = 7 FOR M = 0, 31, 1 DO FUNCADD = (32*N) + M RESULT(M) = READ_REG(MBDADD, CARDADD, FUNCADD) NEXT M The array RESULT(M) then contains all of the Threshold Comparison Bits (EM Et and Total Et Thresholds 0-3) for the MOST RECENT beam crossing. TIMING SIGNALS The CHTCR card uses only 4 Timing and Synchronization Signals. They are as follows: CBUS Timing and Sync. Signal Function ------------ -------- A Write A/B B Latch/Shift C Read A/B D Input Latch SWITCHES AND JUMPERS There are five 8-position DIP switches on this card. One 5-bit DIP switch selects the CBUS card base address that this card will occupy. As previously mentioned, the base address of this card must be EVEN, and the card's address space spans over two consecutive CBUS card addresses. To guarantee that this condition is met, the card address switch can only set Card Address Bit 6 through Card Address Bit 2. Card Address Bit 1 is disregarded in the decision to select the card, allowing the card to wake up at both the even base address, and the odd base+1 address. Card Address Bit 1 is then decoded as if it were a 9th function address line. Card Address Bit 1 low corresponds to accessing the Threshold Comparator input bits, while Card Address Bit 1 high corresponds to accessing either the Hot Tower Table data or the Fast Trigger Hint byte. Since all registers on this card are read-only registers, the Direction line must be high (read), and the Strobe line must be low, in addition to the address constraint, for the card to wake up. Another 8-bit DIP switch selects the Hot Tower information depth and the maximum Hot Tower List Length: The first 4 bits select the depth at which the Hot Tower Table data should be retrieved from the pipeline during a Hot Tower Registering sequence. This depth depends on the operation scheme chosen for the First Level Calorimeter Trigger and Framework, and the choice of the repartition of the time segments in the pipeline. The last 4 bits select the maximum length of the section of Hot Tower List built the CHTCR card that will be included in the complete Hot Tower List sent to the TRD Trigger. Another 8-bit DIP switch selects the card and function address of the Hot Tower FIFO on the Hot Tower Bus. Two 5-bit wire wrap arrays select the PROM base addresses for the lookup of the phi and eta information, thus minimizing the number of different PROMS existing for this Hot Tower list. Different PROM sections can fit 32 different maps. There are in fact only 4 different Phi cell types (1:8, 9:16, 17:24, 25:32) and 12 different Eta cell types (1:4, 5:8, 9:12, 13:16, 17:20, 21:24, -1:-4, -5:-8, -9:-12, -13:-16, -17:-20, -21:-24). Two 8-bit wire wrap arrays (J124 and J128) select the preload values for the Scan Counter and the FIFO Counter respectively, as discussed in the Hot Tower Registering circuitry description. The recommended settings are summarized below: Recommended Jumper Connection Function ------ ---------- ---------------------------------- J124 00010000 SCAN COUNTER PRELOAD = 16 J126 --> ETA ROM BASE ADDRESS as appropriate for card location J127 --> PHI ROM BASE ADDRESS as appropriate for card location J128 00001111 FIFO COUNTER PRELOAD = 15 There are 7 single-bit wire wrap terminals located throughout the board. They perform the following functions: Recommended Jumper Connection Function (recommended / alternative) ------ ---------- ------------------------------------ J9 1&2 Mask / don't mask LATCH/SHIFT during Hot Tower Registering Sequence J10 3&2 WRITE B / WRITE A to CBUS HT Reg I0 J11 1&2 WRITE A / WRITE B to CBUS HT Reg I1 J12 3&2 READ B / CBUS FA5 to CBUS HT S3 (selects 8-level double-buffered/16-level single buffered storage of CBUS Hot Tower List) J13 3&2 GND / VCC to TBUS HT Reg I0 J14 1&2 VCC / GND to TBUS HT Reg I1 (J14 selects 8-/16-level storage of TBUS Hot Tower List if J13 is wired as above) J15 1&2 FIFO EMPTY BAR / PHI DATA 8 (from PROM) to TBUS PHI DATA8 (FIFO NOT EMPTY) CRITICAL TIMING PATHS The primary time-critical path is found in the Hot Tower Registering circuitry. As discussed earlier, the Hot Tower Registering circuitry is pipelined. Following is an estimate of the propagation delays seen in each stage of the pipelined operation using a 20MHz clock. Clock/ Time Hot Tower Scan Eta/Phi (ns) Memory Counter PROM ---- --------- ------- ------- 0 Clock rising edge 12 Scan Counter PROM address outputs settled (n - 1) set up __ 22 29525 OE settled 39 29525 outputs settled 46 HOT TOWER FOUND BAR (n) PROM data settled (n - 1) settled 50 Clock rising edge 60 HOT TOWER LATCH BAR (n) settled 62 Scan Counter PROM address outputs settled (n) set up 80 FIFO WR STB REQ (n) falling edge 85 FIFO WR STB (n) falling edge 96 HOT TOWER FOUND BAR (n + 1) PROM data settled (n) settled 100 Clock rising edge 105 FIFO WR STB (n) rising edge The Hot Tower address will be latch/shifted into the 29525's on FIFO WR STB rising edge. This implies that the Clock rising edge at t=100ns will not cause the Scan Counter outputs to change until after t=105ns. This is a reasonable assumption, as the Scan Counter is a synchronous counter (meaning the outputs do not change until internally settled). The outputs can change at any time after t=105ns, as the 29525's have a negligible 'hold time' requirement. Upon testing, this has proven workable. ----------------------------------------------------------------------------- CONNECTOR ASSIGNMENTS --------------------- INPUT CONNECTOR EM COMPARATORS J1 96/96 pin backplane connector EM COMPARATORS J2 32/96 pin backplane connector TOTAL Et COMPARATORS J2 32/96 pin backplane connector TOTAL Et COMPARATORS J3 96/96 pin backplane connector OUTPUT EM FIRST TIER COUNTS J7 48/50 pin front connector TOTAL Et FIRST TIER COUNTS J8 48/50 pin front connector EM FAST TRIGGER HINT J6 8/16 pin front connector TOTAL Et FAST TRIGGER HINT J6 8/16 pin front connector BUS CONTROL BUS J4 64/96 pin backplane connector TABLE BUS J5 56/64 pin front connector POWER 16 pin VCC J2 16/96 pin backplane connector 8 pin VEE J4 8/96 pin backplane connector 4 pin VTT J4 4/96 pin backplane connector -- 28 power pins 11 pin GND J2 11/96 pin backplane connector 16 pin GND J4 16/96 pin backplane connector -- 27 ground pins ----------------------------------------------------------------------------- J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Counting Channel 8 TTL Comparison Bit # 1 C8B01 2 Counting Channel 8 TTL Comparison Bit # 4 C8B04 3 Counting Channel 8 TTL Comparison Bit # 7 C8B07 4 Counting Channel 8 TTL Comparison Bit # 10 C8B10 5 Counting Channel 8 TTL Comparison Bit # 13 C8B13 6 Counting Channel 8 TTL Comparison Bit # 16 C8B16 7 Counting Channel 8 TTL Comparison Bit # 19 C8B19 8 Counting Channel 8 TTL Comparison Bit # 22 C8B22 9 Counting Channel 8 TTL Comparison Bit # 25 C8B25 10 Counting Channel 8 TTL Comparison Bit # 28 C8B28 11 Counting Channel 8 TTL Comparison Bit # 31 C8B31 12 Counting Channel 7 TTL Comparison Bit # 2 C7B01 13 Counting Channel 7 TTL Comparison Bit # 5 C7B04 14 Counting Channel 7 TTL Comparison Bit # 8 C7B07 15 Counting Channel 7 TTL Comparison Bit # 11 C7B10 16 Counting Channel 7 TTL Comparison Bit # 14 C7B13 17 Counting Channel 7 TTL Comparison Bit # 17 C7B16 18 Counting Channel 7 TTL Comparison Bit # 20 C7B19 19 Counting Channel 7 TTL Comparison Bit # 23 C7B22 20 Counting Channel 7 TTL Comparison Bit # 26 C7B25 21 Counting Channel 7 TTL Comparison Bit # 29 C7B28 22 Counting Channel 7 TTL Comparison Bit # 32 C7B31 23 Counting Channel 6 TTL Comparison Bit # 3 C6B01 24 Counting Channel 6 TTL Comparison Bit # 6 C6B04 25 Counting Channel 6 TTL Comparison Bit # 9 C6B07 26 Counting Channel 6 TTL Comparison Bit # 12 C6B10 27 Counting Channel 6 TTL Comparison Bit # 15 C6B13 28 Counting Channel 6 TTL Comparison Bit # 18 C6B16 29 Counting Channel 6 TTL Comparison Bit # 21 C6B19 30 Counting Channel 6 TTL Comparison Bit # 24 C6B22 31 Counting Channel 6 TTL Comparison Bit # 27 C6B25 32 Counting Channel 6 TTL Comparison Bit # 30 C6B28 33 Counting Channel 8 TTL Comparison Bit # 2 C8B02 34 Counting Channel 8 TTL Comparison Bit # 5 C8B05 35 Counting Channel 8 TTL Comparison Bit # 8 C8B08 36 Counting Channel 8 TTL Comparison Bit # 11 C8B11 37 Counting Channel 8 TTL Comparison Bit # 14 C8B14 38 Counting Channel 8 TTL Comparison Bit # 17 C8B17 39 Counting Channel 8 TTL Comparison Bit # 20 C8B20 40 Counting Channel 8 TTL Comparison Bit # 23 C8B23 41 Counting Channel 8 TTL Comparison Bit # 26 C8B26 42 Counting Channel 8 TTL Comparison Bit # 29 C8B29 43 Counting Channel 8 TTL Comparison Bit # 32 C8B32 44 Counting Channel 7 TTL Comparison Bit # 3 C7B03 45 Counting Channel 7 TTL Comparison Bit # 6 C7B06 46 Counting Channel 7 TTL Comparison Bit # 9 C7B09 47 Counting Channel 7 TTL Comparison Bit # 12 C7B12 48 Counting Channel 7 TTL Comparison Bit # 15 C7B15 49 Counting Channel 7 TTL Comparison Bit # 18 C7B18 50 Counting Channel 7 TTL Comparison Bit # 21 C7B21 51 Counting Channel 7 TTL Comparison Bit # 24 C7B24 52 Counting Channel 7 TTL Comparison Bit # 27 C7B27 53 Counting Channel 7 TTL Comparison Bit # 30 C7B30 54 Counting Channel 6 TTL Comparison Bit # 1 C6B01 55 Counting Channel 6 TTL Comparison Bit # 4 C6B04 56 Counting Channel 6 TTL Comparison Bit # 7 C6B07 57 Counting Channel 6 TTL Comparison Bit # 10 C6B10 58 Counting Channel 6 TTL Comparison Bit # 13 C6B13 59 Counting Channel 6 TTL Comparison Bit # 16 C6B16 60 Counting Channel 6 TTL Comparison Bit # 19 C6B19 61 Counting Channel 6 TTL Comparison Bit # 22 C6B22 62 Counting Channel 6 TTL Comparison Bit # 25 C6B25 63 Counting Channel 6 TTL Comparison Bit # 28 C6B28 64 Counting Channel 6 TTL Comparison Bit # 31 C8B31 65 Counting Channel 8 TTL Comparison Bit # 3 C8B03 66 Counting Channel 8 TTL Comparison Bit # 6 C8B06 67 Counting Channel 8 TTL Comparison Bit # 9 C8B09 68 Counting Channel 8 TTL Comparison Bit # 12 C8B12 69 Counting Channel 8 TTL Comparison Bit # 15 C8B15 70 Counting Channel 8 TTL Comparison Bit # 18 C8B18 71 Counting Channel 8 TTL Comparison Bit # 21 C8B21 72 Counting Channel 8 TTL Comparison Bit # 24 C8B24 73 Counting Channel 8 TTL Comparison Bit # 27 C8B27 74 Counting Channel 8 TTL Comparison Bit # 30 C8B30 75 Counting Channel 7 TTL Comparison Bit # 1 C7B01 76 Counting Channel 7 TTL Comparison Bit # 4 C7B04 77 Counting Channel 7 TTL Comparison Bit # 7 C7B07 78 Counting Channel 7 TTL Comparison Bit # 10 C7B10 79 Counting Channel 7 TTL Comparison Bit # 13 C7B13 80 Counting Channel 7 TTL Comparison Bit # 16 C7B16 81 Counting Channel 7 TTL Comparison Bit # 19 C7B19 82 Counting Channel 7 TTL Comparison Bit # 22 C7B22 83 Counting Channel 7 TTL Comparison Bit # 25 C7B25 84 Counting Channel 7 TTL Comparison Bit # 28 C7B28 85 Counting Channel 7 TTL Comparison Bit # 31 C7B31 86 Counting Channel 6 TTL Comparison Bit # 2 C6B02 87 Counting Channel 6 TTL Comparison Bit # 5 C6B05 88 Counting Channel 6 TTL Comparison Bit # 8 C6B08 89 Counting Channel 6 TTL Comparison Bit # 11 C6B11 90 Counting Channel 6 TTL Comparison Bit # 14 C6B14 91 Counting Channel 6 TTL Comparison Bit # 17 C6B17 92 Counting Channel 6 TTL Comparison Bit # 20 C6B20 93 Counting Channel 6 TTL Comparison Bit # 23 C6B23 94 Counting Channel 6 TTL Comparison Bit # 26 C6B26 95 Counting Channel 6 TTL Comparison Bit # 29 C6B29 96 Counting Channel 6 TTL Comparison Bit # 32 C6B32 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Power +5.0 V VCC 12 Unused 13 Power +5.0 V VCC 14 Power +5.0 V VCC 15 Power +5.0 V VCC 16 Power +5.0 V VCC 17 Unused 18 Power +5.0 V VCC 19 Power +5.0 V VCC 20 Power +5.0 V VCC 21 Power +5.0 V VCC 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Counting Channel 5 TTL Comparison Bit # 1 C5B01 34 Counting Channel 5 TTL Comparison Bit # 3 C5B03 35 Counting Channel 5 TTL Comparison Bit # 5 C5B05 36 Counting Channel 5 TTL Comparison Bit # 7 C5B07 37 Counting Channel 5 TTL Comparison Bit # 9 C5B09 38 Counting Channel 5 TTL Comparison Bit # 11 C5B11 39 Counting Channel 5 TTL Comparison Bit # 13 C5B13 40 Counting Channel 5 TTL Comparison Bit # 15 C5B15 41 Counting Channel 5 TTL Comparison Bit # 17 C5B17 42 Counting Channel 5 TTL Comparison Bit # 19 C5B19 43 Counting Channel 5 TTL Comparison Bit # 21 C5B21 44 Counting Channel 5 TTL Comparison Bit # 23 C5B23 45 Counting Channel 5 TTL Comparison Bit # 25 C5B25 46 Counting Channel 5 TTL Comparison Bit # 27 C5B27 47 Counting Channel 5 TTL Comparison Bit # 29 C5B29 48 Counting Channel 5 TTL Comparison Bit # 31 C5B31 49 Counting Channel 4 TTL Comparison Bit # 1 C4B01 50 Counting Channel 4 TTL Comparison Bit # 3 C4B03 51 Counting Channel 4 TTL Comparison Bit # 5 C4B05 52 Counting Channel 4 TTL Comparison Bit # 7 C4B07 53 Counting Channel 4 TTL Comparison Bit # 9 C4B09 54 Counting Channel 4 TTL Comparison Bit # 11 C4B11 55 Counting Channel 4 TTL Comparison Bit # 13 C4B13 56 Counting Channel 4 TTL Comparison Bit # 15 C4B15 57 Counting Channel 4 TTL Comparison Bit # 17 C4B17 58 Counting Channel 4 TTL Comparison Bit # 29 C4B29 59 Counting Channel 4 TTL Comparison Bit # 21 C4B21 60 Counting Channel 4 TTL Comparison Bit # 23 C4B23 61 Counting Channel 4 TTL Comparison Bit # 25 C4B25 62 Counting Channel 4 TTL Comparison Bit # 27 C4B27 63 Counting Channel 4 TTL Comparison Bit # 39 C4B39 64 Counting Channel 4 TTL Comparison Bit # 31 C4B31 65 Counting Channel 5 TTL Comparison Bit # 2 C5B02 66 Counting Channel 5 TTL Comparison Bit # 4 C5B04 67 Counting Channel 5 TTL Comparison Bit # 6 C5B06 68 Counting Channel 5 TTL Comparison Bit # 8 C5B08 69 Counting Channel 5 TTL Comparison Bit # 10 C5B10 70 Counting Channel 5 TTL Comparison Bit # 12 C5B12 71 Counting Channel 5 TTL Comparison Bit # 14 C5B14 72 Counting Channel 5 TTL Comparison Bit # 16 C5B16 73 Counting Channel 5 TTL Comparison Bit # 18 C5B18 74 Counting Channel 5 TTL Comparison Bit # 20 C5B20 75 Counting Channel 5 TTL Comparison Bit # 22 C5B22 76 Counting Channel 5 TTL Comparison Bit # 24 C5B24 77 Counting Channel 5 TTL Comparison Bit # 26 C5B26 78 Counting Channel 5 TTL Comparison Bit # 28 C5B28 79 Counting Channel 5 TTL Comparison Bit # 30 C5B30 80 Counting Channel 5 TTL Comparison Bit # 32 C5B32 81 Counting Channel 4 TTL Comparison Bit # 2 C4B02 82 Counting Channel 4 TTL Comparison Bit # 4 C4B04 83 Counting Channel 4 TTL Comparison Bit # 6 C4B06 84 Counting Channel 4 TTL Comparison Bit # 8 C4B08 85 Counting Channel 4 TTL Comparison Bit # 10 C4B10 86 Counting Channel 4 TTL Comparison Bit # 12 C4B12 87 Counting Channel 4 TTL Comparison Bit # 14 C4B14 88 Counting Channel 4 TTL Comparison Bit # 16 C4B16 89 Counting Channel 4 TTL Comparison Bit # 18 C4B18 90 Counting Channel 4 TTL Comparison Bit # 20 C4B20 91 Counting Channel 4 TTL Comparison Bit # 22 C4B22 92 Counting Channel 4 TTL Comparison Bit # 24 C4B24 93 Counting Channel 4 TTL Comparison Bit # 26 C4B26 94 Counting Channel 4 TTL Comparison Bit # 28 C4B28 95 Counting Channel 4 TTL Comparison Bit # 30 C4B30 96 Counting Channel 4 TTL Comparison Bit # 32 C4B32 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Counting Channel 3 TTL Comparison Bit # 1 C3B01 2 Counting Channel 3 TTL Comparison Bit # 4 C3B04 3 Counting Channel 3 TTL Comparison Bit # 7 C3B07 4 Counting Channel 3 TTL Comparison Bit # 10 C3B10 5 Counting Channel 3 TTL Comparison Bit # 13 C3B13 6 Counting Channel 3 TTL Comparison Bit # 16 C3B16 7 Counting Channel 3 TTL Comparison Bit # 19 C3B19 8 Counting Channel 3 TTL Comparison Bit # 22 C3B22 9 Counting Channel 3 TTL Comparison Bit # 25 C3B25 10 Counting Channel 3 TTL Comparison Bit # 28 C3B28 11 Counting Channel 3 TTL Comparison Bit # 31 C3B31 12 Counting Channel 2 TTL Comparison Bit # 2 C2B01 13 Counting Channel 2 TTL Comparison Bit # 5 C2B04 14 Counting Channel 2 TTL Comparison Bit # 8 C2B07 15 Counting Channel 2 TTL Comparison Bit # 11 C2B10 16 Counting Channel 2 TTL Comparison Bit # 14 C2B13 17 Counting Channel 2 TTL Comparison Bit # 17 C2B16 18 Counting Channel 2 TTL Comparison Bit # 20 C2B19 19 Counting Channel 2 TTL Comparison Bit # 23 C2B22 20 Counting Channel 2 TTL Comparison Bit # 26 C2B25 21 Counting Channel 2 TTL Comparison Bit # 29 C2B28 22 Counting Channel 2 TTL Comparison Bit # 32 C2B31 23 Counting Channel 1 TTL Comparison Bit # 3 C1B01 24 Counting Channel 1 TTL Comparison Bit # 6 C1B04 25 Counting Channel 1 TTL Comparison Bit # 9 C1B07 26 Counting Channel 1 TTL Comparison Bit # 12 C1B10 27 Counting Channel 1 TTL Comparison Bit # 15 C1B13 28 Counting Channel 1 TTL Comparison Bit # 18 C1B16 29 Counting Channel 1 TTL Comparison Bit # 21 C1B19 30 Counting Channel 1 TTL Comparison Bit # 24 C1B22 31 Counting Channel 1 TTL Comparison Bit # 27 C1B25 32 Counting Channel 1 TTL Comparison Bit # 30 C1B28 33 Counting Channel 3 TTL Comparison Bit # 2 C3B02 34 Counting Channel 3 TTL Comparison Bit # 5 C3B05 35 Counting Channel 3 TTL Comparison Bit # 8 C3B08 36 Counting Channel 3 TTL Comparison Bit # 11 C3B11 37 Counting Channel 3 TTL Comparison Bit # 14 C3B14 38 Counting Channel 3 TTL Comparison Bit # 17 C3B17 39 Counting Channel 3 TTL Comparison Bit # 20 C3B20 40 Counting Channel 3 TTL Comparison Bit # 23 C3B23 41 Counting Channel 3 TTL Comparison Bit # 26 C3B26 42 Counting Channel 3 TTL Comparison Bit # 29 C3B29 43 Counting Channel 3 TTL Comparison Bit # 32 C3B32 44 Counting Channel 2 TTL Comparison Bit # 3 C2B03 45 Counting Channel 2 TTL Comparison Bit # 6 C2B06 46 Counting Channel 2 TTL Comparison Bit # 9 C2B09 47 Counting Channel 2 TTL Comparison Bit # 12 C2B12 48 Counting Channel 2 TTL Comparison Bit # 15 C2B15 49 Counting Channel 2 TTL Comparison Bit # 18 C2B18 50 Counting Channel 2 TTL Comparison Bit # 21 C2B21 51 Counting Channel 2 TTL Comparison Bit # 24 C2B24 52 Counting Channel 2 TTL Comparison Bit # 27 C2B27 53 Counting Channel 2 TTL Comparison Bit # 30 C2B30 54 Counting Channel 1 TTL Comparison Bit # 1 C1B01 55 Counting Channel 1 TTL Comparison Bit # 4 C1B04 56 Counting Channel 1 TTL Comparison Bit # 7 C1B07 57 Counting Channel 1 TTL Comparison Bit # 10 C1B10 58 Counting Channel 1 TTL Comparison Bit # 13 C1B13 59 Counting Channel 1 TTL Comparison Bit # 16 C1B16 60 Counting Channel 1 TTL Comparison Bit # 19 C1B19 61 Counting Channel 1 TTL Comparison Bit # 22 C1B22 62 Counting Channel 1 TTL Comparison Bit # 25 C1B25 63 Counting Channel 1 TTL Comparison Bit # 28 C1B28 64 Counting Channel 1 TTL Comparison Bit # 31 C1B31 65 Counting Channel 3 TTL Comparison Bit # 3 C3B03 66 Counting Channel 3 TTL Comparison Bit # 6 C3B06 67 Counting Channel 3 TTL Comparison Bit # 9 C3B09 68 Counting Channel 3 TTL Comparison Bit # 12 C3B12 69 Counting Channel 3 TTL Comparison Bit # 15 C3B15 70 Counting Channel 3 TTL Comparison Bit # 18 C3B18 71 Counting Channel 3 TTL Comparison Bit # 21 C3B21 72 Counting Channel 3 TTL Comparison Bit # 24 C3B24 73 Counting Channel 3 TTL Comparison Bit # 27 C3B27 74 Counting Channel 3 TTL Comparison Bit # 30 C3B30 75 Counting Channel 2 TTL Comparison Bit # 1 C2B01 76 Counting Channel 2 TTL Comparison Bit # 4 C2B04 77 Counting Channel 2 TTL Comparison Bit # 7 C2B07 78 Counting Channel 2 TTL Comparison Bit # 10 C2B10 79 Counting Channel 2 TTL Comparison Bit # 13 C2B13 80 Counting Channel 2 TTL Comparison Bit # 16 C2B16 81 Counting Channel 2 TTL Comparison Bit # 19 C2B19 82 Counting Channel 2 TTL Comparison Bit # 22 C2B22 83 Counting Channel 2 TTL Comparison Bit # 25 C2B25 84 Counting Channel 2 TTL Comparison Bit # 28 C2B28 85 Counting Channel 2 TTL Comparison Bit # 31 C2B31 86 Counting Channel 1 TTL Comparison Bit # 2 C1B02 87 Counting Channel 1 TTL Comparison Bit # 5 C1B05 88 Counting Channel 1 TTL Comparison Bit # 8 C1B08 89 Counting Channel 1 TTL Comparison Bit # 11 C1B11 90 Counting Channel 1 TTL Comparison Bit # 14 C1B14 91 Counting Channel 1 TTL Comparison Bit # 17 C1B17 92 Counting Channel 1 TTL Comparison Bit # 20 C1B20 93 Counting Channel 1 TTL Comparison Bit # 23 C1B23 94 Counting Channel 1 TTL Comparison Bit # 26 C1B26 95 Counting Channel 1 TTL Comparison Bit # 29 C1B29 96 Counting Channel 1 TTL Comparison Bit # 32 C1B32 ---------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR Pin Function Mnemonic ---------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -5.2 V VEE 13 Power -5.2 V VEE 14 Power -5.2 V VEE 15 Power -5.2 V VEE 16 Unused 17 Power -5.2 V VEE 18 Power -5.2 V VEE 19 Power -5.2 V VEE 20 Power -5.2 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 Timing & Sync. Signal H Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 Timing & Sync. Signal H Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 ---------------------------------------------------------------------------- J5 : HOT TOWER TABLE BUS FRONT CONNECTOR Pin Function Mnemonic ---------------------------------------------------------------------------- 1 brown Hot Tower Phi Data Bit# 1 Non-inverted NHTPHI1 2 tan Hot Tower Phi Data Bit# 1 Inverted IHTPHI1 3 red Hot Tower Phi Data Bit# 2 Non-inverted NHTPHI2 4 tan Hot Tower Phi Data Bit# 2 Inverted IHTPHI2 5 orange Hot Tower Phi Data Bit# 3 Non-inverted NHTPHI3 6 tan Hot Tower Phi Data Bit# 3 Inverted IHTPHI3 7 yellow Hot Tower Phi Data Bit# 4 Non-inverted NHTPHI4 8 tan Hot Tower Phi Data Bit# 4 Inverted IHTPHI4 9 green Hot Tower Phi Data Bit# 5 Non-inverted NHTPHI5 10 tan Hot Tower Phi Data Bit# 5 Inverted IHTPHI5 11 blue Hot Tower Phi Data Bit# 6 Non-inverted NHTPHI6 12 tan Hot Tower Phi Data Bit# 6 Inverted IHTPHI6 13 violet Hot Tower Phi Data Bit# 7 Non-inverted NHTPHI7 14 tan Hot Tower Phi Data Bit# 7 Inverted IHTPHI7 15 grey Fifo Not Empty Non-inverted NFIFONE 16 tan Fifo Not Empty Inverted IFIFONE 17 white Hot Tower Eta Data Bit# 1 Non-inverted NHTETA1 18 tan Hot Tower Eta Data Bit# 1 Inverted IHTETA1 19 black Hot Tower Eta Data Bit# 2 Non-inverted NHTETA2 20 tan Hot Tower Eta Data Bit# 2 Inverted IHTETA2 21 brown Hot Tower Eta Data Bit# 3 Non-inverted NHTETA3 22 tan Hot Tower Eta Data Bit# 3 Inverted IHTETA3 23 red Hot Tower Eta Data Bit# 4 Non-inverted NHTETA4 24 tan Hot Tower Eta Data Bit# 4 Inverted IHTETA4 25 orange Hot Tower Eta Data Bit# 5 Non-inverted NHTETA5 26 tan Hot Tower Eta Data Bit# 5 Inverted IHTETA5 27 yellow Hot Tower Eta Data Bit# 6 Non-inverted NHTETA6 28 tan Hot Tower Eta Data Bit# 6 Inverted IHTETA6 29 green Hot Tower Eta Data Bit# 7 Non-inverted NHTETA7 30 tan Hot Tower Eta Data Bit# 7 Inverted IHTETA7 31 blue Hot Tower Eta Data Bit# 8 Non-inverted NHTETA8 32 tan Hot Tower Eta Data Bit# 8 Inverted IHTETA8 33 violet Card Address Bit# 1 Non-inverted NTCA1 34 tan Card Address Bit# 1 Inverted ITCA1 35 grey Card Address Bit# 2 Non-inverted NTCA2 36 tan Card Address Bit# 2 Inverted ITCA2 37 white Card Address Bit# 3 Non-inverted NTCA3 38 tan Card Address Bit# 3 Inverted ITCA3 39 black Card Address Bit# 4 Non-inverted NTCA4 40 tan Card Address Bit# 4 Inverted ITCA4 41 brown Card Address Bit# 5 Non-inverted NTCA5 42 tan Card Address Bit# 5 Inverted ITCA5 43 red Card Address Bit# 6 Non-inverted NTCA6 44 tan Card Address Bit# 6 Inverted ITCA6 45 orange Function Address Bit# 1 Non-inverted NTFA2 46 tan Function Address Bit# 1 Inverted ITFA2 47 yellow Function Address Bit# 2 Non-inverted NTFA3 48 tan Function Address Bit# 2 Inverted ITFA3 49 green TBUS TSS A HT Cycle Non-inverted NTTSSA 50 tan TBUS TSS A HT Cycle Inverted ITTSSA 51 blue TBUS TSS B HT Register/ Non-inverted NTTSSB 52 tan TBUS TSS B Inverted ITTSSB 53 violet TBUS TSS C noise guard Non-inverted NTTSSC 54 tan TBUS TSS C noise guard Inverted ITTSSC 55 grey TBUS TSS D Strobe Non-inverted NTTSSD 56 tan TBUS TSS D Strobe Inverted ITTSSD 57 white 58 tan 59 black 60 tan 61 brown 62 tan 63 red 64 tan ---------------------------------------------------------------------------- J6: FAST TRIGGER HINT FRONT CONNECTOR Pin Function Mnemonic ---------------------------------------------------------------------------- 1 brown EM Et Thresh. 0 Fast Hint Non-inverted NEMH1 2 tan EM Et Thresh. 0 Fast Hint Inverted IEMH1 3 red EM Et Thresh. 1 Fast Hint Non-inverted NEMH2 4 tan EM Et Thresh. 1 Fast Hint Inverted IEMH2 5 orange EM Et Thresh. 2 Fast Hint Non-inverted NEMH3 6 tan EM Et Thresh. 2 Fast Hint Inverted IEMH3 7 yellow EM Et Thresh. 3 Fast Hint Non-inverted NEMH4 8 tan EM Et Thresh. 3 Fast Hint Inverted IEMH4 9 green Tot Et Thresh. 0 Fast Hint Non-inverted NTOH1 10 tan Tot Et Thresh. 0 Fast Hint Inverted ITOH1 11 blue Tot Et Thresh. 1 Fast Hint Non-inverted NTOH2 12 tan Tot Et Thresh. 1 Fast Hint Inverted ITOH2 13 violet Tot Et Thresh. 2 Fast Hint Non-inverted NTOH3 14 tan Tot Et Thresh. 2 Fast Hint Inverted ITOH3 15 grey Tot Et Thresh. 3 Fast Hint Non-inverted NTOH4 16 tan Tot Et Thresh. 3 Fast Hint Inverted ITOH4 ---------------------------------------------------------------------------- J7: EM Et FIRST TIER COUNT FRONT CONNECTOR Pin Function Mnemonic ---------------------------------------------------------------------------- 1 brown EM Et Thresh. 0 Count Bit# 1 Non-inverted NEMT1.1 2 tan EM Et Thresh. 0 Count Bit# 1 Inverted IEMT1.1 3 red EM Et Thresh. 0 Count Bit# 2 Non-inverted NEMT1.2 4 tan EM Et Thresh. 0 Count Bit# 2 Inverted IEMT1.2 5 orange EM Et Thresh. 0 Count Bit# 3 Non-inverted NEMT1.3 6 tan EM Et Thresh. 0 Count Bit# 3 Inverted IEMT1.3 7 yellow EM Et Thresh. 0 Count Bit# 4 Non-inverted NEMT1.4 8 tan EM Et Thresh. 0 Count Bit# 4 Inverted IEMT1.4 9 green EM Et Thresh. 0 Count Bit# 5 Non-inverted NEMT1.5 10 tan EM Et Thresh. 0 Count Bit# 5 Inverted IEMT1.5 11 blue EM Et Thresh. 0 Count Bit# 6 Non-inverted NEMT1.6 12 tan EM Et Thresh. 0 Count Bit# 6 Inverted IEMT1.6 13 violet EM Et Thresh. 1 Count Bit# 1 Non-inverted NEMT2.1 14 tan EM Et Thresh. 1 Count Bit# 1 Inverted IEMT2.1 15 grey EM Et Thresh. 1 Count Bit# 2 Non-inverted NEMT2.2 16 tan EM Et Thresh. 1 Count Bit# 2 Inverted IEMT2.2 17 white EM Et Thresh. 1 Count Bit# 3 Non-inverted NEMT2.3 18 tan EM Et Thresh. 1 Count Bit# 3 Inverted IEMT2.3 19 black EM Et Thresh. 1 Count Bit# 4 Non-inverted NEMT2.4 20 tan EM Et Thresh. 1 Count Bit# 4 Inverted IEMT2.4 21 brown EM Et Thresh. 1 Count Bit# 5 Non-inverted NEMT2.5 22 tan EM Et Thresh. 1 Count Bit# 5 Inverted IEMT2.5 23 red EM Et Thresh. 1 Count Bit# 6 Non-inverted NEMT2.6 24 tan EM Et Thresh. 1 Count Bit# 6 Inverted IEMT2.6 25 orange EM Et Thresh. 2 Count Bit# 1 Non-inverted NEMT3.1 26 tan EM Et Thresh. 2 Count Bit# 1 Inverted IEMT3.1 27 yellow EM Et Thresh. 2 Count Bit# 2 Non-inverted NEMT3.2 28 tan EM Et Thresh. 2 Count Bit# 2 Inverted IEMT3.2 29 green EM Et Thresh. 2 Count Bit# 3 Non-inverted NEMT3.3 30 tan EM Et Thresh. 2 Count Bit# 3 Inverted IEMT3.3 31 blue EM Et Thresh. 2 Count Bit# 4 Non-inverted NEMT3.4 32 tan EM Et Thresh. 2 Count Bit# 4 Inverted IEMT3.4 33 violet EM Et Thresh. 2 Count Bit# 5 Non-inverted NEMT3.5 34 tan EM Et Thresh. 2 Count Bit# 5 Inverted IEMT3.5 35 grey EM Et Thresh. 2 Count Bit# 6 Non-inverted NEMT3.6 36 tan EM Et Thresh. 2 Count Bit# 6 Inverted IEMT3.6 37 white EM Et Thresh. 3 Count Bit# 1 Non-inverted NEMT4.1 38 tan EM Et Thresh. 3 Count Bit# 1 Inverted IEMT4.1 39 black EM Et Thresh. 3 Count Bit# 2 Non-inverted NEMT4.2 40 tan EM Et Thresh. 3 Count Bit# 2 Inverted IEMT4.2 41 brown EM Et Thresh. 3 Count Bit# 3 Non-inverted NEMT4.3 42 tan EM Et Thresh. 3 Count Bit# 3 Inverted IEMT4.3 43 red EM Et Thresh. 3 Count Bit# 4 Non-inverted NEMT4.4 44 tan EM Et Thresh. 3 Count Bit# 4 Inverted IEMT4.4 45 orange EM Et Thresh. 3 Count Bit# 5 Non-inverted NEMT4.5 46 tan EM Et Thresh. 3 Count Bit# 5 Inverted IEMT4.5 47 yellow EM Et Thresh. 3 Count Bit# 6 Non-inverted NEMT4.6 48 tan EM Et Thresh. 3 Count Bit# 6 Inverted IEMT4.6 49 green 50 tan ---------------------------------------------------------------------------- J8: TOTAL Et FIRST TIER COUNT FRONT CONNECTOR Pin Function Mnemonic ---------------------------------------------------------------------------- 1 brown Tot Et Thresh. 0 Count Bit# 1 Non-inverted NTOT1.1 2 tan Tot Et Thresh. 0 Count Bit# 1 Inverted ITOT1.1 3 red Tot Et Thresh. 0 Count Bit# 2 Non-inverted NTOT1.2 4 tan Tot Et Thresh. 0 Count Bit# 2 Inverted ITOT1.2 5 orange Tot Et Thresh. 0 Count Bit# 3 Non-inverted NTOT1.3 6 tan Tot Et Thresh. 0 Count Bit# 3 Inverted ITOT1.3 7 yellow Tot Et Thresh. 0 Count Bit# 4 Non-inverted NTOT1.4 8 tan Tot Et Thresh. 0 Count Bit# 4 Inverted ITOT1.4 9 green Tot Et Thresh. 0 Count Bit# 5 Non-inverted NTOT1.5 10 tan Tot Et Thresh. 0 Count Bit# 5 Inverted ITOT1.5 11 blue Tot Et Thresh. 0 Count Bit# 6 Non-inverted NTOT1.6 12 tan Tot Et Thresh. 0 Count Bit# 6 Inverted ITOT1.6 13 violet Tot Et Thresh. 1 Count Bit# 1 Non-inverted NTOT2.1 14 tan Tot Et Thresh. 1 Count Bit# 1 Inverted ITOT2.1 15 grey Tot Et Thresh. 1 Count Bit# 2 Non-inverted NTOT2.2 16 tan Tot Et Thresh. 1 Count Bit# 2 Inverted ITOT2.2 17 white Tot Et Thresh. 1 Count Bit# 3 Non-inverted NTOT2.3 18 tan Tot Et Thresh. 1 Count Bit# 3 Inverted ITOT2.3 19 black Tot Et Thresh. 1 Count Bit# 4 Non-inverted NTOT2.4 20 tan Tot Et Thresh. 1 Count Bit# 4 Inverted ITOT2.4 21 brown Tot Et Thresh. 1 Count Bit# 5 Non-inverted NTOT2.5 22 tan Tot Et Thresh. 1 Count Bit# 5 Inverted ITOT2.5 23 red Tot Et Thresh. 1 Count Bit# 6 Non-inverted NTOT2.6 24 tan Tot Et Thresh. 1 Count Bit# 6 Inverted ITOT2.6 25 orange Tot Et Thresh. 2 Count Bit# 1 Non-inverted NTOT3.1 26 tan Tot Et Thresh. 2 Count Bit# 1 Inverted ITOT3.1 27 yellow Tot Et Thresh. 2 Count Bit# 2 Non-inverted NTOT3.2 28 tan Tot Et Thresh. 2 Count Bit# 2 Inverted ITOT3.2 29 green Tot Et Thresh. 2 Count Bit# 3 Non-inverted NTOT3.3 30 tan Tot Et Thresh. 2 Count Bit# 3 Inverted ITOT3.3 31 blue Tot Et Thresh. 2 Count Bit# 4 Non-inverted NTOT3.4 32 tan Tot Et Thresh. 2 Count Bit# 4 Inverted ITOT3.4 33 violet Tot Et Thresh. 2 Count Bit# 5 Non-inverted NTOT3.5 34 tan Tot Et Thresh. 2 Count Bit# 5 Inverted ITOT3.5 35 grey Tot Et Thresh. 2 Count Bit# 6 Non-inverted NTOT3.6 36 tan Tot Et Thresh. 2 Count Bit# 6 Inverted ITOT3.6 37 white Tot Et Thresh. 3 Count Bit# 1 Non-inverted NTOT4.1 38 tan Tot Et Thresh. 3 Count Bit# 1 Inverted ITOT4.1 39 black Tot Et Thresh. 3 Count Bit# 2 Non-inverted NTOT4.2 40 tan Tot Et Thresh. 3 Count Bit# 2 Inverted ITOT4.2 41 brown Tot Et Thresh. 3 Count Bit# 3 Non-inverted NTOT4.3 42 tan Tot Et Thresh. 3 Count Bit# 3 Inverted ITOT4.3 43 red Tot Et Thresh. 3 Count Bit# 4 Non-inverted NTOT4.4 44 tan Tot Et Thresh. 3 Count Bit# 4 Inverted ITOT4.4 45 orange Tot Et Thresh. 3 Count Bit# 5 Non-inverted NTOT4.5 46 tan Tot Et Thresh. 3 Count Bit# 5 Inverted ITOT4.5 47 yellow Tot Et Thresh. 3 Count Bit# 6 Non-inverted NTOT4.6 48 tan Tot Et Thresh. 3 Count Bit# 6 Inverted ITOT4.6 49 green 50 tan ---------------------------------------------------------------------------- PARTS USED ---------- Qty Reqd Description / Identification ---- ---------------------------- 22 QUAD TTL-TO-ECL TRANSLATOR 10H124 8 QUAD ECL-TO-TTL TRANSLATOR 10H125 9 HEX BUFFER WITH ENABLE 10H188 2 1K OHM, 10 PIN, SIP RESISTOR PACK 110A102 6 470 OHM, 10 PIN, SIP RESISTOR PACK 110A471 2 RESISTOR PACK 10 PIN SIP 5600 OHM 110A562 1 CRYSTAL OSCILLATOR CLOCK MODULE K1100A 9 RESISTOR PACK 316A560 3 RESISTOR PACK 316B471 4 96 PIN DIN CONNECTOR 531796-1 2 8 BIT ADDRESS COMPARATOR 74ALS520 10 OCTAL NON-INVERTING BUFFER 74ALS541 2 HEX INVERTER ADVANCED SCHOTTKY 74AS04 1 QUAD 2-INPUT POSITIVE-AND GATE 74AS08 6 3-TO-8 DECODER 74AS138 1 DUAL 2-TO-4 DECODER 74AS139 1 8-TO-1 MUX COMPL OUTPUTS 74AS151 8 8-INPUT POSITIVE-NAND GATE 74AS30 2 QUAD 2-INPUT POSITIVE-OR GATE 74AS32 32 OCTAL D-TYPE TRANSPARENT LATCH 74AS573 2 DUAL D-TYPE EDGE-TRIGGERED FLIP-FLOP 74AS74 2 8-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER 74AS869 32 DUAL 5 INPUT NOR GATE 74F260 1 IC DIGITAL 1-4 DUAL BINARY DECODER 74S85 3 SWX 8POS DIP PIANO STYLE 76PSB08 2 IC MEM PROM 2KX8 35NS 27S291A 24 PROM 2K X 4 35NS AM27S185 8 PROM 4K x 8 40NS AM27S43 40 DUAL 8 DEEP PIPELINE REGISTERS AM29525 1 16-pin connector 3MR16 2 3433-1302 CON 50PIN RT-AN SLDR HDR 3MR50 1 64 PIN CONNECTOR 3MR64 305 0.1 MFD MONOLITHIC CAPACITOR MONOCAP 4 24 PIN WIRE WRAP POST WRAP24 7 3 PIN WIRE WRAP POST WRAP3 CURRENT CONSUMPTION ------------------- The expected current consumption is: Supply min max ------ --- --- VCC (+5.0) 21.0 A 26.9 A VEE (-5.2) 2.2 A 2.2 A VTT (-2.0) 2.0 A 2.0 A ASSEMBLY NOTES -------------- See file TRGHARD:CHTCR_ASSEMBLY.TXT for assembly instructions. REVISION HISTORY ---------------- Revision A manufactured--March 1989. See file TRGHARD:CHTCR_REV_A_FIXES.TXT for list of problems and fixes in revision A. Revision A obsolete--February 1990. Revision B manufactured--February 1990. ECO NOTES --------- Revision B: 1. The silkscreened reference designators are incorrect for U66 and U70-U75. The silkscreened type designators are correct. The BOM, schematic, and blueprints are correct in ALL respects. U70-U74 are called 10H124 on both PCB silkscreen and in documentation. U75 is called 10H124 on PCB, and called 74ALS541 in documentation. U66 is called 74ALS541 on PCB, and called 10H124 in documentation. Reference Designator PCB Ref Designator should read in PCB silkscreen Ref. Designator used everywhere else ------------------- ------------------------------------ U66 U75 U70 U66 U71 U67 U72 U68 U73 U69 U74 U70 U75 U71