________________________________________________________________ | | | | | CALORIMETER TRIGGER FRONT END CELL BACKPLANE | | | | REVISION B | |______________________________________________________________| Original 25-AUG-1989 Location vs Function of CAT2's 6-JAN-1990 Add a new table of PCB Layer vs Levels and Files, Modify the 4 original tables at the end for Rev.B 14-MAR-1990 Describe location of terminator resistors (SG) 26-NOV-1990 Update CTFE to CHTCR and CTFE to CAT2 Information, Connector Map, T&SS Map, and Rev. B Information 1-JAN-1991 Move Terminator Resistor info to a new file (SG) 23-MAY-1991 I. FUNCTIONAL OVERVIEW OF THE CAL TRIGGER FRONT END BACKPLANE One calorimeter trigger front end cell consists of sixteen Calorimeter Trigger Front End cards, two Calorimeter Hot Tower Counter/Register cards, eight Calorimeter Adder Tree cards, and a Motherboard Bus Driver card. The sixteen CTFE boards are held responsible for conditioning the analog signals from the calorimeter electronics and performing table lookup, addition, and threshold detection operations on these signals. Each of the sixteen CTFE cards is responsible for observing 4 TRIGGER TOWERS that are adjacent in eta and at a particular phi within the calorimeter. The CTFE then takes this threshold detection information and board total sum information and delivers it to two places: Individual THRESHOLD COMPARATOR outputs are sent to one of the two CHTCR cards, and four BOARD TOTAL operands are routed to the appropriate CAT2 cards. The THRESHOLD COMPARATOR output bits from the CTFE are scanned by the CHTCR card. The bits are scanned in a monotonic increasing order through Eta on all reference sets. The EM REFERENCE SETS (CHTCR channels 1 - 4) are scanned in a monotonic decreasing order through Phi, while the TOTAL Et REFERENCE SETS (CHTCR channels 5 - 8) are scanned in a monotonic increasing order through Phi. This arrangement provides maximum flexibility in that it allows for any size TRD detector cell while still scanning the towers in a rational order. In the following example CTFE card Ch#1 serves Eta Index 1 and CTFE card Ch#4 serves Eta Index 4. Wiring of the CTFE "Cluster Comparator" outputs to the CHTCR "Channel Input Bit" inputs ------------------------------------------------- CTFE Card Location CTFE "Cluster Comparator" CHTCR "Input Bit" ------------------ ------------------------- ----------------- PHI 1 ETA 1 Ch #1 EM Cluster Comp #1 Channel 1 Bit 8 " ETA 1 Ch #1 EM Cluster Comp #4 Channel 4 Bit 8 " ETA 4 Ch #4 EM Cluster Comp #1 Channel 1 Bit 32 " ETA 4 Ch #4 EM Cluster Comp #4 Channel 4 Bit 32 " ETA 1 Ch #1 Tot Et Clst Comp #1 Channel 5 Bit 1 " ETA 1 Ch #1 Tot Et Clst Comp #4 Channel 8 Bit 1 " ETA 4 Ch #4 Tot Et Clst Comp #1 Channel 5 Bit 25 " ETA 4 Ch #4 Tot Et Clst Comp #4 Channel 8 Bit 25 PHI 8 ETA 1 Ch #1 EM Cluster Comp #1 Channel 1 Bit 1 " ETA 1 Ch #1 EM Cluster Comp #4 Channel 4 Bit 1 " ETA 4 Ch #4 EM Cluster Comp #1 Channel 1 Bit 25 " ETA 4 Ch #4 EM Cluster Comp #4 Channel 4 Bit 25 " ETA 1 Ch #1 Tot Et Clst Comp #1 Channel 5 Bit 8 " ETA 1 Ch #1 Tot Et Clst Comp #4 Channel 8 Bit 8 " ETA 4 Ch #4 Tot Et Clst Comp #1 Channel 5 Bit 32 " ETA 4 Ch #4 Tot Et Clst Comp #4 Channel 8 Bit 32 CTFE EM Comparator to CHTCR Channel Input Bits ---- -------------- -------------- -------------- -------------- | 1 8 | | 9 16 | | 17 24 | | 25 32 | -------------- -------------- -------------- -------------- e1 e1 e2 e2 e3 e3 e4 e4 p8 p1 p8 p1 p8 p1 p8 p1 CTFE Total Et Comparator to CHTCR Channel Input Bits -------- -------------- -------------- -------------- -------------- | 1 8 | | 9 16 | | 17 24 | | 25 32 | -------------- -------------- -------------- -------------- e1 e1 e2 e2 e3 e3 e4 e4 p1 p8 p1 p8 p1 p8 p1 p8 CTFE Board Totals to CAT2 Operand Inputs -------------------------------------------- The BOARD TOTAL operands from each CTFE card are 10 bit differential ECL words that serve as inputs to the CAT2 cards. Each CAT2 card is responsible for summing over the eight CTFE cards, one data type per CAT2. The eight CTFE cards serve eight adjacent phi indexes. Four CAT2 cards are required to sum the EM, HD, PX, and PY data, one data type per CAT2 card. Note that since the CAT2 input operands are differential ECL, special care must be taken during the routing of these signals--specifically, the inverted and non-inverted signal pairs should be treated as balanced transmission lines. Wiring of the CTFE "Board Total" outputs to the CAT2 "Operand Inputs" --------------------------------------------------------------------- CTFE Card Location CAT2 INPUT OPERAND NUMBER ------------------ ---------------------------- PHI 1 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 1 PHI 2 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 2 PHI 3 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 3 PHI 4 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 4 PHI 5 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 5 PHI 6 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 6 PHI 7 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 7 PHI 8 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 8 PHI 9 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 1 PHI 10 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 2 PHI 11 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 3 PHI 12 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 4 PHI 13 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 5 PHI 14 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 6 PHI 15 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 7 PHI 16 ETA 1 to 4 CAT2 INPUT OPERAND NUMBER 8 The backplane is also responsible for containing the CBUS; a control bus used for passing commands and data to and from the backplane's constituent cards. The CBUS is, for the most part, simply bussed the entire length of the backplane, using the rightmost column of connectors (looking into crate). Timing & Sync Signals on the CBUS are not connected to all of the application cards. Each type of application card requires a slightly different set of timing signals. More Timing & Sync Signal are needed than the CBUS was originally designed for. In addition to the original eight TIMING & SYNC Signals (A,B,C,D,E,F,G,H) on J203 of the Monter Board Driver, more T&SS signals have been added to the adjacent connector of the MOTHER BOARD DRIVER. J202 now has an additional eight TIMING & SYNC Signals (J,K,L,M,N,P,R,S). Mother Board Driver connectors J203 and J204 now carry the following Timing & Sync Signals (all pin numbers in form non-inv,inv): J202 pins 89,57 T&SS J J203 pins 65,33 T&SS A J202 pins 90,58 T&SS K J203 pins 66,34 T&SS B J202 pins 91,59 T&SS L J203 pins 67,35 T&SS C J202 pins 92,60 T&SS M J203 pins 68,36 T&SS D J202 pins 93,61 T&SS N J203 pins 69,37 T&SS E J202 pins 94,62 T&SS P J203 pins 70,38 T&SS F J202 pins 95,63 T&SS R J203 pins 71,39 T&SS G J202 pins 96,64 T&SS S J203 pins 72,40 T&SS H TIMING SIGNAL USAGE BY CARD TYPE ---------------------------------- CTFE CARD --------- CTBP CTFE CTMBD NET CTFE Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-A WRITE A/B 65,33 J203 65,33 TSS-A TSS-B LATCH SHIFT 66,34 J203 66,34 TSS-B TSS-C READ A/B 67,35 J203 67,35 TSS-C TSS-D SEL ENERGY MAP LSB 68,36 J203 68,36 TSS-D TSS-E SEL ENERGY MAP MDB 69,37 J203 69,37 TSS-E TSS-F X CLOCK 70,38 J203 70,38 TSS-F TSS-G 2X CLOCK 71,39 J203 71,39 TSS-G TSS-H ADC CLOCK 72,40 J203 72,40 TSS-H TSS-J SEL ENERGY MAP MSB 22,23 J202 89,57 TSS-J TSS-K SEL MONENTM MAP LSB 24,25 J202 90,58 TSS-K TSS-L SEL MOMENTM MAP MDB 26,27 J202 91,59 TSS-L TSS-M SEL MOMENTM MAP MSB 28,29 J202 92,60 TSS-M CHTCR CARD ---------- CTBP CHTCR CTMBD NET CHTCR Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-A WRITE A/B 65,33 J203 65,33 TSS-A TSS-B LATCH/SHIFT 66,34 J203 66,34 TSS-B TSS-C READ A/B 67,35 J203 67,35 TSS-C TSS-D CHTCR INPUT CLOCK 68,36 J202 95,63 TSS-R TSS-E CHTCR (UNCOMITTED) 69,37 J202 96,64 TSS-S CAT2 CARD ENERGY ADDER ----------******------ ENERGY CTBP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-G CAT2 (UNCOMITTED) 71,39 J202 96,64 TSS-S TSS-H OPRAND LATCH CLOCK 72,40 J202 94,62 TSS-P CAT2 CARD MOMENTUM ADDER ----------********------ MOMENTUM CTBP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-G CAT2 (UNCOMITTED) 71,39 J202 96,64 TSS-S TSS-H OPRAND LATCH CLOCK 72,40 J202 93,61 TSS-N CALORIMETER TRIGGER MOTHER BOARD DRIVER TIMING SIGNAL OUTPUT'S FRONT VIEW -------------------------------------------------------------------------- M E S O N C P L M R H A A T G T R W T C E R C R C C R I H E C C C C A A C T / A C C C C C T T T T T T C A E S D T T T T T F F F F L T H F F F F F E E E E C C O A I A E E E E E L L C H / F / J K L M K K K T B T B D E F G H J K L M N P R S A B C D E F G H T&SS # - - ----------------------------- ---------------------------- - - | | X X X X X X X X | | X X X X X X X X | | - - ----------------------------- ---------------------------- - - J202 J203 LOCATION OF TERMINATOR PACKS ---------------------------- Each differential CBUS signal on the backplane must be parallel terminated. Since the CTMBD is in the middle of the backplane, and the loads are distributed along the backplane, it is not immediately obvious how this termination should proceed. It is proposed that an acceptable solution is to terminate these lines in a fashion similar to the Framework backplanes, that is, with a single 110 Ohm resistor per signal, mounted at (or near) one terminus of the trace. This terminates one "branch" of the trace normally, while leaving the other branch unterminated. See the file TRGHARD:CTBP_TERMINATOR_LOCATIONS.TXT for a complete description of the types and locations of terminator packs required. Note that these terminators are not an integral part of the backplane (in contrast to e.g. the power foils), but are "pressed on" after assembly is complete. See TRGHARD:CTBP_ASSEMBLY.TXT for backplane assembly instructions. Finally, the backplane must supply the required power to each type of card. As each type of card presents different demands on each supply voltage (See TRGHARD:CTBP_POWER_REQUIREMENTS.TXT for details) the effective distribution of power is an important issue. As each trace layer has unused areas filled with ground plane, the magnitude of ground potential differences has been kept to a minimum. The +5V Vcc supply, however, has some complicated distribution problems. The largest problem is that the CHTCR card can draw up to 28 Amps of supply current, yet has a comparatively small number of Vcc connector pins. Add to this that the Vcc supply comes into the card in the center of the backplane--each strip of copper between two connector rows has between 2.5 and 5.0 milli-Ohms of resistance. An analysis of one CHTCR and CTFE card pair shows that 31mV and 16mV drop can be expected on the Vcc supply to each card, respectively. MAP OF THE 108 BACKPLANE CONNECTORS VIEWED FROM THE FRONT ----------------------------------------------------------- TOP OF THE CRATE CBUS J103 J104 J105 J106 CAT2 HD J99 J100 J101 J102 CAT2 PY J95 J96 J97 J98 CAT2 PX J91 J92 J93 J94 CAT2 EM J87 J88 J89 J90 CTFE J83 J84 J85 J86 CTFE J79 J80 J81 J82 CTFE J75 J76 J77 J78 CTFE J71 J72 J73 J74 CTFE J67 J68 J69 J70 CTFE J63 J64 J65 J66 CTFE J59 J60 J61 J62 CTFE J55 J56 J57 J58 CHTCR J200 J201 J202 J203 CTMBD J49 J50 J51 J52 CAT2 HD J45 J46 J47 J48 CAT2 PY J41 J42 J43 J44 CAT2 PX J37 J38 J39 J40 CAT2 EM J33 J34 J35 J36 CTFE J29 J30 J31 J32 CTFE J25 J26 J27 J28 CTFE J21 J22 J23 J24 CTFE J17 J18 J19 J20 CTFE J13 J14 J15 J16 CTFE J9 J10 J11 J12 CTFE J5 J6 J7 J8 CTFE J1 J2 J3 J4 CHTCR BOTTOM OF THE CRATE This is the view looking into the crate (i.e. the component side view of the backplane). II. ARRANGEMENT OF BOARDS IN A CALORIMETER TRIGGER BACKPLANE The example shown is for the top backplane (BACKPLANE #1) of rack M103. This is the positive eta's 1 - 4 with phi's 1 - 16. The view is from the front of the rack looking into the crate. CARD FILE CARD BOARD JACK SLOT ADDRESS TYPE NUMBER ---- ------- ---------------------------------- ------ 27 16 CAT2 HD SUM FOR PHI 1 to 8 103-106 TOP 26 20 CAT2 +PY SUM FOR PHI 1 to 8 99-102 25 24 CAT2 +PX SUM FOR PHI 1 to 8 95-93 24 28 CAT2 EM SUM FOR PHI 1 to 8 91-94 23 32-33 CTFE PHI 1 ETA 1 to 4 87-90 22 34-35 CTFE PHI 2 ETA 1 to 4 83-86 21 36-37 CTFE PHI 3 ETA 1 to 4 79-82 20 38-39 CTFE PHI 4 ETA 1 to 4 75-78 19 40-41 CTFE PHI 5 ETA 1 to 4 71-74 18 42-43 CTFE PHI 6 ETA 1 to 4 67-70 17 44-45 CTFE PHI 7 ETA 1 to 4 63-66 16 46-47 CTFE PHI 8 ETA 1 to 4 59-62 15 2-3 CHTCR FOR EM AND HD PHI 1 to 8 55-58 14 -- CTMBD MOTHER BOARD ADRS = 169 200-203 13 17 CAT2 HD SUM FOR PHI 9 to 16 49-52 12 21 CAT2 +PY SUM FOR PHI 9 to 16 45-48 11 25 CAT2 -PX SUM FOR PHI 9 to 16 41-44 10 29 CAT2 EM SUM FOR PHI 9 to 16 37-40 9 48-49 CTFE PHI 9 ETA 1 to 4 33-36 8 50-51 CTFE PHI 10 ETA 1 to 4 29-32 7 52-53 CTFE PHI 11 ETA 1 to 4 25-28 6 54-55 CTFE PHI 12 ETA 1 to 4 21-24 5 56-57 CTFE PHI 13 ETA 1 to 4 17-20 4 58-59 CTFE PHI 14 ETA 1 to 4 13-16 3 60-61 CTFE PHI 15 ETA 1 to 4 9-12 2 62-63 CTFE PHI 16 ETA 1 to 4 5-8 1 4-5 CHTCR FOR EM AND HD PHI 9 to 16 1-4 BOTTOM The example shown is for the bottom backplane (BACKPLANE #2) of rack M103. This is the positive eta's 1 - 4 with phi 17 - 32. The view is from the front of the rack looking into the crate. CARD FILE CARD BOARD JACK SLOT ADDRESS TYPE NUMBER ---- ------- ---------------------------------- ------ 27 16 CAT2 HD SUM FOR PHI 17 to 24 103-106 TOP 26 20 CAT2 -PY SUM FOR PHI 17 to 24 99-102 25 24 CAT2 -PX SUM FOR PHI 17 to 24 95-93 24 28 CAT2 EM SUM FOR PHI 17 to 24 91-94 23 32-33 CTFE PHI 17 ETA 1 to 4 87-90 22 34-35 CTFE PHI 18 ETA 1 to 4 83-86 21 36-37 CTFE PHI 19 ETA 1 to 4 79-82 20 38-39 CTFE PHI 20 ETA 1 to 4 75-78 19 40-41 CTFE PHI 21 ETA 1 to 4 71-74 18 42-43 CTFE PHI 22 ETA 1 to 4 67-70 17 44-45 CTFE PHI 23 ETA 1 to 4 63-66 16 46-47 CTFE PHI 24 ETA 1 to 4 59-62 15 2-3 CHTCR FOR EM AND HD PHI 17 to 24 55-58 14 -- CTMBD MOTHER BOARD ADRS = 169 200-203 13 17 CAT2 HD SUM FOR PHI 25 to 32 49-52 12 21 CAT2 -PY SUM FOR PHI 25 to 32 45-48 11 25 CAT2 +PX SUM FOR PHI 25 to 32 41-44 10 29 CAT2 EM SUM FOR PHI 25 to 32 37-40 9 48-49 CTFE PHI 25 ETA 1 to 4 33-36 8 50-51 CTFE PHI 26 ETA 1 to 4 29-32 7 52-53 CTFE PHI 27 ETA 1 to 4 25-28 6 54-55 CTFE PHI 28 ETA 1 to 4 21-24 5 56-57 CTFE PHI 29 ETA 1 to 4 17-20 4 58-59 CTFE PHI 30 ETA 1 to 4 13-16 3 60-61 CTFE PHI 31 ETA 1 to 4 9-12 2 62-63 CTFE PHI 32 ETA 1 to 4 5-8 1 4-5 CHTCR FOR EM AND HD PHI 25 to 32 1-4 BOTTOM III. BACKPLANE PRINTED CIRCUIT BOARD DESIGN RULES 1. 0.012" traces on 0.025" centers, 0.062" diameter pads. No 90^ angles are permitted; all corners have 45^ bends. 2. Only one trace between 0.1" centered pads. 3. Traces may come no closer than 0.080" to a mounting hole. This distance is indicated by a graphic circle placed on level 50. 4. Inverted/Non Inverted ECL traces run parallel on adjacent levels. 5. A maximum of 10 traces on 0.025" centers in any horizontal trough between connector rows. 6. Traces running vertically in between connector columns should be spaced on 0.050" or 0.075" centers. 7. If more than on CAT operand shares a vertical trough, an extra 0.025" should be placed between them to provide visual seperation. 8. Any trace running vertically next to a connector should be at least 0.050" from its end column of pins. 9. Traces exiting from a connector may break to 45^ no closer than the 0.050" above/below the connector pins. DETAILS OF THE CTBP CIRCUIT BOARD REVISION: 14-MAR-1990 CTBP PCB LAYER ALLOCATION STRATEGY ===================================== PCB CAD CAD LAYER LEVEL LAYER CONTENTS ----- ----- ----- ---------------------------------------------------- 36 COMPONENT SIDE SILK SCREEN 21 SOLDER MASK (Same both side) 1 11 1 GROUND PLANE 2 55 13 CTFE NUMBER 1 HD (INVERTED) HORIZONTAL TTL LAYER 3 54 12 CTFE NUMBER 1 HD (POSITIVE) VERTICAL TTL LAYER 4 11 1 GROUND PLANE 5 13 3 CTFE NUMBERS 4 ALL, AND 8 ALL (INVERTED) 6 12 2 CTFE NUMBERS 4 ALL, AND 8 ALL (POSITIVE) 7 15 5 CTFE NUMBERS 3 ALL, AND 7 ALL (INVERTED) 8 14 4 CTFE NUMBERS 3 ALL, AND 7 ALL (POSITIVE) 9 17 7 CTFE NUMBERS 2 ALL, 6 HD, PX, PY, AND CBUS (INVERTED) 10 16 6 CTFE NUMEBRS 2 ALL, 6 HD, PX, PY, AND CBUS (POSITIVE) 11 51 9 CTFE NUMBERS 1 PX,EM, 5 ALL, AND SOME T&SS (INVERTED) 12 18 8 CTFE NUMBERS 1 PX,EM, 5 ALL, AND SOME T&SS (POSITIVE) 13 53 11 CTFE NUMBERS 1 PY, AND 6 EM (INVERTED) 14 52 10 CTFE NUMBERS 1 PY, AND 6 EM (POSITIVE) 15 57 15 VCC AND GROUND PLANES 16 58 16 VCC AND VEE POWER PLANES 21 SOLDER MASK (Same both side) 40 SOLDER SIDE SILK SCREEN GERBER FILES TO BE GENERATED ================================ FILE FILE CONTENTS NUMBER LAYER --> PCB ASSEMBLY LAYER ------ ---------------------------- 1. BOARD OUTLINE TEST PLOT 2. LAYER 1 (COMPONENT SIDE) GROUND PLANE 3. LAYER 2 TRACES, THIS IS A BURRIED VIA PAIR WITH LAYER 3 4. LAYER 3 TRACES, THIS IS A BURIED VIA PAIR WITH LAYER 2 5. LAYER 5 TRACES AND ITS GND PLANE 6. LAYER 6 TRACES AND ITS GND PLANE 7. LAYER 7 TRACES AND ITS GND PLANE 8. LAYER 8 TRACES AND ITS GND PLANE 9. LAYER 9 TRACES AND ITS GND PLANE 10. LAYER 10 TRACES AND ITS GND PLANE 11. LAYER 11 TRACES AND ITS GND PLANE 12. LAYER 12 TRACES AND ITS GND PLANE 13. LAYER 13 TRACES AND ITS GND PLANE 14. LAYER 14 TRACES AND ITS GND PLANE 15. LAYER 15 VCC AND GROUND PLANES 16. LAYER 16 (SOLDER SIDE) VCC AND VEE POWER PLANES 17. SOLDER MASK 18. COMPONENT SIDE SILKSCREEN 19. SOLDER SIDE SILKSCREEN 20. DRILL FILE #1 CONNECT PCB LAYERS 1 THROUGH 4 (636 HOLES) 21. DRILL FILE #2 CONNECT BURIED VIAS PCB LAYERS 2 AND 3 (86 HOLES) 22. DRILL FILE #3 CONNECT PCB LAYERS 15 AND 16 (636 HOLES) 23. DRILL FILE #4 CONNECTOR PIN HOLES (10,368 HOLES) 24. DRILL FILE #5 MOUNTING HOLES OUTER 2 ROWS (14 HOLES) 25. DRILL FILE #6 MOUNTING HOLES CENTER ROW ( 4 HOLES) SUMMARY OF THE IEDS LEVELS USED =================================== IEDS LEVEL USED FOR (LAYER --> IEDS LAYER) PCB ASSEMBLY LAYER ------- ---------------------------------------- ------------------- 1 = Vias for connecting PCB Layers 1 through 4 2 = Vias for connecting PCB Layers 15 and 16 9 = PINS, VIA HOLES 11 = LAYER 1 GROUND PLANE PCB LAYER 1, 4 12 = LAYER 2 CAT 4 ALL & 8 ALL - POS PCB LAYER 6 13 = LAYER 3 CAT 4 ALL & 8 ALL - INV PCB LAYER 5 14 = LAYER 4 CAT 3 ALL & 7 ALL - POS PCB LAYER 8 15 = LAYER 5 CAT 3 ALL & 7 ALL - INV PCB LAYER 7 16 = LAYER 6 CAT 2 ALL & 6 HD,PX,PY - POS PCB LAYER 10 17 = LAYER 7 CAT 2 ALL & 6 HD,PX,PY - INV PCB LAYER 9 18 = LAYER 8 CAT 5 ALL & 1 PX,EM - POS PCB LAYER 12 51 = LAYER 9 CAT 5 ALL & 1 PX,EM - INV PCB LAYER 11 52 = LAYER 10 CAT 1 PY & 6 EM - POS PCB LAYER 14 53 = LAYER 11 CAT 1 PY & 6 EM - INV PCB LAYER 13 54 = LAYER 12 CAT 1 HD - POS, HOT TOWER VIAS PCB LAYER 3 55 = LAYER 13 CAT 1 HD - INV, HOT TOWER VIAS PCB LAYER 2 57 = LAYER 15 VCC AND GROUND PLANES PCB LAYER 15 58 = LAYER 16 VCC AND VEE POWER PLANES PCB LAYER 16 39 = GROUND PLANE FOR IEDS LEVELS 12 AND 13 PCB LAYERS 6, 5 42 = GROUND PLANE FOR IEDS LEVELS 14 AND 15 PCB LAYERS 8, 7 43 = GROUND PLANE FOR IEDS LEVELS 16 AND 17 PCB LAYERS 10, 9 48 = GROUND PLANE FOR IEDS LEVELS 18 AND 51 PCB LAYERS 12,11 49 = GROUND PLANE FOR IEDS LEVELS 52 AND 53 PCB LAYERS 14,13 21 = SOLDER MASK 23 = BOARD TRIM MARKS 25 = MOUNTING HOLES 26 = BODY OUTLINE 27 = BOARD OUTLINE 28 = REFERENCE DESIGNATORS 29 = TYPE DESIGNATOR 36 = SILKSCREEN COMPONENT SIDE 40 = SILKSCREEN SOLDER SIDE 41 = PIN 1 DESIGNATOR 44 = ALIGNMENT MOIRE MARKS TAPE GENERATION ROUTINES ================================= FILE NUMBER IEDS LEVEL, PCB LAYER, REF FILE LEVELS ON PEN TABLE ------ --------------------------------- ----------- ------------- 1. PERIMETER TEST PLOT 27, 23,44 CTBP_PLT.TBL 2. GROUND PLANE PHOTO PLOT 9,11, 23,44 CTBP_GND.TBL 3. IEDS LEVEL 55, PCB LAYER 2, RF = LEV55GND 9,55, 44 CTBP_VIA.TBL 4. IEDS LEVEL 54, PCB LAYER 3, RF = LEV54GND 9,54, 44 CTBP_VIA.TBL 5. IEDS LEVEL 13, PCB LAYER 5, RF = LEV12GND 9,13,39, 44 CTBP_PLT.TBL 6. IEDS LEVEL 12, PCB LAYER 6, RF = LEV12GND 9,12,39, 44 CTBP_PLT.TBL 7. IEDS LEVEL 15, PCB LAYER 7, RF = LEV14GND 9,15,42, 44 CTBP_PLT.TBL 8. IEDS LEVEL 14, PCB LAYER 8, RF = LEV14GNDT 9,14,42, 44 CTBP_PLT.TBL 9. IEDS LEVEL 17, PCB LAYER 9, RF = LEV16GND 9,17,43, 44 CTBP_PLT.TBL 10. IEDS LEVEL 16, PCB LAYER 10, RF = LEV16GND 9,16,43, 44 CTBP_PLT.TBL 11. IEDS LEVEL 51, PCB LAYER 11, RF = LEV18GND 9,51,48, 44 CTBP_PLT.TBL 12. IEDS LEVEL 18, PCB LAYER 12, RF = LEV18GND 9,18,48, 44 CTBP_PLT.TBL 13. IEDS LEVEL 53, PCB LAYER 13, RF = LEV52GND 9,53,49, 44 CTBP_PLT.TBL 14. IEDS LEVEL 52, PCB LAYER 14, RF = LEV52GND 9,52,49, 44 CTBP_PLT.TBL 15. VCC AND GROUND POWER PLANES PHOTO PLOT 9,57, 44 CTBP_POW.TBL 16. VCC AND VEE POWER PLANES PHOTO PLOT 9,58, 23,44 CTBP_POW.TBL 17. SOLDER MASK 9,21, 44 CTBP_MSK.TBL 18. COMPONONT SIDE SILKSCREEN PHOTOPLOT 36, 23,44 CTBP_PLT.TBL 19. SOLDER SIDE SILKSCREEN PHOTOPLOT 40, 23,44 CTBP_PLT.TBL 20. DRILL FILE NUMBER 1 VIAS TO CONNECT LAYERS 1-4 1 CTBP_DRILL_1.TBL 21. DRILL FILE NUMBER 2 BURIED VIAS LAYERS 2-3 9 CTBP_DRILL_2.TBL 22. DRILL FILE NUMBER 3 VIAS TO CONNECT LAYER 15-16 2 CTBP_DRILL_3.TBL 23. DRILL FILE NUMBER 4 CONNECTOR PIN HOLES 9 CTBP_DRILL_4.TBL 24. DRILL FILE NUMBER 5 MOUNTING HOLES, OUTER 2 ROWS 25 CTBP_DRILL_5.TBL 25. DRILL FILE NUMBER 5 MOUNTING HOLES, CENTER ROW 25 CTBP_DRILL_6.TBL CTBP Revision B PCB LAYER vs TRACE AND PLANE SOURCE FILES AND LEVELS ------------------------------------------------------------------------ 14-MAR-1990 CTBP GROUND PLANE TRACES FOR SIGNAL TRACES FOR REV. B THIS PCB LAYER ARE ON THIS LEVEL THIS PCB LAYER ARE ON PCB LAYER AND ARE STORED IN THIS FILE NAME THIS LEVEL IN THIS FILE --------- ------------------------------------- ----------------------- 1 LEVEL 11 CTBP.TRACES_GROUND --- 2 LEVEL 55 CTBP.TRACES_LEV55GND LEVEL 55 CTBP.BRD 3 LEVEL 54 CTBP.TRACES_LEV54GND LEVEL 54 CTBP.BRD 4 LEVEL 11 CTBP.TRACES_GROUND --- 5 LEVEL 39 CTBP.TRACES_LEV12GND_MT39 LEVEL 13 CTBP.BRD 6 LEVEL 39 CTBP.TRACES_LEV12GND_MT39 LEVEL 12 CTBP.BRD 7 LEVEL 42 CTBP.TRACES_LEV14GND_MT42 LEVEL 15 CTBP.BRD 8 LEVEL 42 CTBP.TRACES_LEV14GND_MT42 LEVEL 14 CTBP.BRD 9 LEVEL 43 CTBP.TRACES_LEV16GND_MT43 LEVEL 17 CTBP.BRD 10 LEVEL 43 CTBP.TRACES_LEV16GND_MT43 LEVEL 16 CTBP.BRD 11 LEVEL 48 CTBP.TRACES_LEV18GND_MT48 LEVEL 51 CTBP.BRD 12 LEVEL 48 CTBP.TRACES_LEV18GND_MT48 LEVEL 18 CTBP.BRD 13 LEVEL 49 CTBP.TRACES_LEV52GND_MT49 LEVEL 53 CTBP.BRD 14 LEVEL 49 CTBP.TRACES_LEV52GND_MT49 LEVEL 52 CTBP.BRD 15 LEVEL 57 CTBP.TRACES_LEV57GND LEVEL 57 CTBP.TRACES_LEV57VCCTOP CTBP.TRACES_LEV57VCCBOT 16 --- LEVEL 58 CTBP.TRACES_VCCTOP CTBP.TRACES_VCCBOT CTBP.TRACES_VEEBOTL CTBP.TRACES_VEEBOTR CTBP.TRACES_VEETOPL CTBP.TRACES_VEETOPR For the CTBP Revision B Project the permanent storage file for the data in CTBP.BRD is the file CTBP.REV_B_LOCKED_BRD. CTBP LAYER ALLOCATION FOR THE NEW CBUS TIMING SIGNALS ------------------------------------------------------- PCB CAD CAD SIGNAL LAYER LAYER LEVEL PLRTY REVISION B TIMING SIGNAL FUNCTIONS ----- ----- ----- ----- ---------------------------------------- 5 3 13 INV These layers carry the bulk of the new 6 2 12 POS T&SS traces. All new CTFE T&SS's and their connection to the CTMBD outputs. These layers carry the spare T&SS from the CTMBD output to the bus between the lower 4 CAT2's. 9 7 17 INV These layers carry the standard CBUS. 10 6 16 POS They also carry the T&SS's to the lower CHTCR. They also carry the T&SS's to the upper 4 CAT2's and bus the upper CAT2's. The energy T&SS between the lower CAT2's is bused on these layers. 11 9 51 INV These layers carry the T&SS's to the 12 8 18 POS upper CHTCR card. They also carry the energy and momentum T&SS's from the CTMBD to the lower CAT2's and they bus the momentum and and spare T&SS's on the lower CAT2's.