---------------------------------------------------------------- ! ! ! D0 FIRST LEVEL TRIGGER SYSTEM CTFE CARD ! ! ! ! Revision B ! ---------------------------------------------------------------- Michigan State University Original Rev A 25-AUG-1989 Add Rev B Information 21-FEB-1990 Most recent version 17-APR-1991 GENERAL DESCRIPTION --------------------- The Calorimeter Trigger Front End card contains the analog circuity and digital logic to handle 4 EM-HD Trigger Tower pairs. This card includes the following circuit elements: the differential line receiver with pedestal summer, the pedestal offset DAC, the flash converter, the double buffer FIFO memory, the lookup memory for translation of Et to E,Et,Px,Py, etc., four digital adder circuits for the Total Et signal, the digital adder circuits for the board sum of the EM channels, the digital adder circuit for the board sum of the HD channels, the minimum EM Et threshold comparator circuits, HD veto comparators for the EM threshold comparators, the minimum Total Et comparator circuits, the timing and control logic for all the above, and the C Bus interface. Normally a CTFE card is used to handle the Trigger Tower Signals from 4 adjacent EM-HD Trigger Tower Pairs. The 4 Trigger Tower Pairs all have the same Trigger Tower Phi Index coordinate and are adjacent in eta. The channels on the CTFE Card are numbered in the following way: EM Channel 1, HD Channel 1, through EM Channel 4, HD Channel 4. The analog front-end section of this card contains: a terminator-attenuator for the differential coax lines from the BLS, a differential amplifier stage, a fixed offset voltage summer, and a DAC that is used to inject a variable offset voltage. The frequency passband of the differential amplifier stage (-3 dB points) is from 500 kHz to 3.5 mHz. The actual input range of the MC10319 ADC is from -1.0 to +1.0 Volts. The offset voltage to the differential amplifier stage is such that with zero differential input, the converter "sees" the following: DIFFERENTIAL DAC INPUT VOLTAGE SEEN OUTPUT HEX CODE INPUT VOLTAGE CODE HEX BY THE ADC FROM THE ADC ------------- ---------- ------------ --------------- 0.0 Volts 00 -1.0 Volts 00 0.0 FF -0.333 55 This shows that the LSB in the DAC input is equal to one third of a count on the ADC LSB output code. The differential input amplifier stage has a gain of two so that the differential input Voltage vs ADC output code with the offset DAC set for zero looks like the following (the table shown below is for an input terminator-attenuator with a gain of 1): DIFFERENTIAL DAC HEX VOLTAGE SEEN OUTPUT HEX CODE INPUT VOLTAGE INPUT CODE BY THE ADC FROM THE ADC ------------- ---------- ------------ --------------- 0.0 Volts 00 -1.0 Volts 00 0.5 00 0.0 80 1.0 00 1.0 FF The full scale range of the ADC should be about 64 GeV. This gives a LSB value of one fourth GeV. The typical offset will be about 4 GeV to prevent the "rectifier effect". Thus the running conditions (using an input terminator-attenuator with no attenuation i.e. gain of 1) will be the following: DIFFERENTIAL DAC HEX VOLTAGE SEEN OUTPUT CODE EQUIV. INPUT VOLTAGE INPUT CODE BY THE ADC FROM THE ADC ENERGY ------------- ---------- ------------ ------------ --------- -0.059 Volts 2D -1.000 Volts 00 -3.75 GeV 0.000 2D -0.882 0F 0.0 0.441 2D 0.000 80 28.0 0.941 2D 1.000 FF 60.0 The official definition of the interface between the BLS and the CTFE cards is a signal scaled such that 1 volt differential equals 32 GeV. DIFFERENTIAL BLS OUTPUT VOLTAGE EQUIVALENT ENERGY ------------------ ----------------- 0.0 Volts 0.0 GeV 1.0 32.0 2.0 63.75 (64) The CTFE card will receive on a front panel connectors the 8 differential input signals. These signals pass through header mounted terminator- attenuator networks before they reach the differential line receivers. The gain for the Terminator-Attenuator network for a CTFE channel at Eta Index of 1 (i.e. 90 degrees) is about 1/2. The rear panel connections include: the power supplies, all output signals, and the trigger control computer bus connection. There are a number of connectors on the board: J1 through J4 are 96 pin DIN connectors used to carry Vcc, Vee, Vtt, GND, the trigger control computer CBUS and various output signals from the card. J15, J18, J21, and J24 are 8 pin headers used to carry the differential analog input signals. Each of the connectors is used for an EM-HD signal pair. Note the 8 differential input signals are carried on 16 coax lines. Connectors J16,J19,J22,J25 are Lemo connectors for monitoring the 4 EM channels. Connectors J14,J17,J20,J23 are Lemo connectors for monitoring the 4 HD channels. Connectors J9 through J12 are 16 pin DIP connectors for the input terminator-attenuator networks. Connector J13 is for monitoring the ADC clock signal. The signal seen on J13 is identical to the signal on pin #18 of the MC10319 FADC's. The CTFE card uses power supplies of +5.0 Volts, -2.0Volts and -5.2 Volts. These supplies are then filtered on card to provide separate analog and digital supplies. The +5.0 Volt supply Vcc is on the following 32 pins: J2 8-11, J2 13-16, J2 18-21, J2 23-26, J3 7-10, J3 12-15, J3 17-20, J3 22-25. The -5.2 Volt supply Vee is on the following 16 pins: J1 13-16, J1 18-21, J4 12-15, J4 17-20. The -2.0 Volt supply Vtt is on the following 8 pins: J1 23-26, J4 7-10. The GROUND connection is on the following 46 pins: J1 1-11, J1 28-32, J2 1-6, J2 28-32, J3 1-5, J3 27-32, J4 1-5, J4 30-32. TIMING & SYNCHRONIZATION SIGNALS ---------------------------------- The CTFE Cards use 12 Timing and Synchronization Signals from the Specific Mother-Board CBUS. This requires special trace routing and special use of the J4 backplane connector because the CBUS was only designed to carry 8 Timing & Sync Signals. In addition to the standard CBUS area on J4 T&SS Signals are also carried on J4 pins 22 through 29. Timing & Sync A is used to control which section of the 29525's is written into. When Timing and Sync Signal A is high then the A half of the 29525's is selected for writing into, and when the Timing and Sync Signal A is low than the B half of the 29525's is selected for writing data into. Timing & Sync B is used to LATCH & SHIFT the data in the 29525's. The data is LATCH & SHIFTED in the 29525's on the rising positive edge of Timing & Sync Signal B. This Timing & Sync Signal is also used to control the latch section of the 74F399 ADC Data Multiplexer-Latches. On the falling negative edge of this Timing & Sync Signal the ADC Data Multiplexer-Latches will update. The ADC Data Multiplexer-Latches may also be clocked by loading a bit in the Board Control Status Register. Timing & Sync Signal C is used to select which section of the AM29525 is read. When Timing & Sync Signal C is asserted then the A-half of the AM29525 is read. When the signal is negated then the B-half of the buffer is selected. Timing & Sync Signals D, E, J, K, L, M are used as the high order addresses to the Energy and Momentum Lookup Memories. These signals could supply information to the Lookup Memories indicating the Z position of the interaction vertex and thus pick a lookup table calculated for the correct vertex position. These Timing & Sync Signals could also indicate the presence of beam in the main ring and thus select Lookup Memories which mask part of the Calorimeter from the First Level Trigger. These T&SS signals are used in the following order: Timing and PROM Device Sync. Signal Function Address Bit ------------ ---------------------------- ----------------- T&SS D Energy LUM Page Select LSB Address Bit 8 T&SS E Energy LUM Page Select MDB Address Bit 9 T&SS J Energy LUM Page Select MSB Address Bit 10 T&SS K Momentum LUM Page Select LSB Address Bit 0 T&SS L Momentum LUM Page Select MDB Address Bit 9 T&SS M Momentum LUM Page Select MSB Address Bit 10 NOTE: For details about the connections to the Momentum LUM Page Select address lines see the section below about CTFE Rev. B programmable parts. Timing & Sync Signals F and G are used for the X Clock Signal and the 2X Clock Signal. These are the only Timing Signals necessary to sequence the CTFE Card through its normal operation for each beam crossing. The Total Et Latches are updated on the positive edge of the 2X Clock when the X Clock is high. The EM Et and HD Veto Comparator Latches are also updated on the positive edge of the 2X Clock when the X Clock is High. The Energy Lookup Memory registered PROM's are clocked by all positive edges of the 2X Clock signal. NOTE: For details of the clocking of the EM Et, HD Veto Comparator Latches see the CTFE Rev. B ECO section below. Timing & Sync Signal H is used as the ADC Convert Clock Signal. A delayed version of this Timing & Sync Signal is used to Start the MC10319 ADC (the Converter Clock signal pin 18). To generate the delay in the ADC Clock Signal the CTFE Card includes a delay line with multiple taps. The tap on this delay line is adjusted on each CTFE Card so the Peak of the Trigger Pick-off signals on the card and the falling edge of the ADC Clock occur at the same time. The Delay line has a total length of 100 nsec. and has 10 taps. The length of the delay between Timing & Sync Signal H and the ADC Convert Clock signal (on pin #18 of the MC10319's) is controlled by DIP switch U287. The following table shows the switch settings for each available delay. C ---> CLOSED, No Mark ---> OPEN SWITCH SETTING ADC CLOCK DELAY SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 --------- --- --- --- --- --- --- --- --- Zero nsec. C C 10 nsec. C C 20 nsec. C C 30 nsec. C C 40 nsec. C C 50 nsec. C C 60 nsec. C C 70 nsec. C C 80 nsec. C C 90 nsec. C C 100 nsec. C C 110 nsec. C C The ADC conversion cycle starts on the rising edge of the ADC Clock Signal. This signal must stay high for >5.0 nsec. for it to be valid. New data is stable at the output of the converter 20 nsec. after the falling edge of this Timing & Sync Signal. The output of the MC10319 is stable except for the 20 nsec. after the falling edge of the Converter Clock signal. A copy of the ADC Clock Signal (MC10319 pin 18) may be monitored by the connector J13 on the front of the CTFE Card. The analog signal is sampled immediately prior to the falling edge of the ADC Clock signal. PRINCIPAL SIGNAL FLOW THROUGH THE CTFE BOARD ---------------------------------------------- The flow of the calorimeter signals and the Pedestal Offset DAC signals through the front end differential amplifiers and ADC is described above. These circuits result in an 8 bit digital number from each ADC that is proportional to the Et from the calorimeter section to which the ADC is connected. The ADC Et outputs are not corrected for the Z position of the interaction. The 8 bit output of each of the MC10319 ADC's is one of the two inputs to a pair of 74F399 digital multiplexer-latch IC's; the other multiplexer input comes from the output of a 74AS867 8 bit counter called the Test Data Register. This counter can be incremented, loaded, read, and cleared by software via the C-BUS using bits in the CTFE Card CSR Register (FA = 80) and the Test Data Register at (FA = 82). This multiplexer-latch is used so that either ADC data or test data, from the 74AS867 counter, may be sent to the rest of the digital signal processing circuitry. The latch function, in the 74F399 multiplexer-latch, is required to de-skew the outputs of the ADC's. This is necessary because various ADC's may be clocked at different times. The 74F399's are normally clocked by the falling edge of Timing & Sync Signal B. They may also be clocked via computer control using bits in the Card CSR Register. There is a MUX-LATCH Clock Control Register (FA = 81) to control which channels receive the MUX-LATCH Clock Signal. Starting with the 74F399 multiplexer-latch's all of the rest of the CTFE (and L1 Calorimeter Trigger) operation is isochronous. The output of this multiplexer-latch supplies the inputs to all of the digital signal processing that follows the ADC conversion. The digital signal processing includes the following steps: Double Buffer Memory Arrays, Momentum Look Up Memories and Adder, EM and HD Energy Look Up Memories, various Energy Adders, and Comparators for EM Et Threshold, HD veto on the EM Threshold, and the Total Et Threshold Comparators. Both the EM and HD channels send data to 8 stage deep double buffer memory arrays (the Am 29525's). These 8 stage deep double buffer memory arrays are used to store the results from the last 8 ADC conversions (last 8 beam crossings). There is a memory array for the EM and HD section of each channel on the CTFE Card. These memory arrays are controlled by three signals on the Timing & Sync Bus (29525 READ A/B, 29525 WRITE A/B, and 29525 LATCH-SHIFT). Note that the 29525 LATCH-SHIFT Timing Signal is also used as the clock for the 74F399 multiplexer-latch's. The positive edge of the 29525 LATCH-SHIFT Timing & Sync Signal causes the 29525's to latch and shift data while the falling edge of this Timing & Sync Signal causes the 74F399's to update. The momentum and energy signal processing are handled differently on the card so they will be discussed separately. Momentum Signal Processing The 8 bit Et signals from the ADC Data multiplexer-latch's of an EM and HD Trigger Tower pair are added to form a rough 9 bit Total Et signal. This signal is used as part of the address to the Px and Py Momentum Look Up Memories. This can be done in two different ways on the CTFE Rev B cards. 1. Either this 9 bit rough Total Et signal is used as the lower 9 bit address to the Momentum Look Up Memories with two additional higher order address bits used to select one of 4 pages which provide the Z vertex position correction; or 2. The LSB of the 9 bit rough Total Et signal is dropped thus freeing up a third address line on the Momentum Look Up Memories to be used to select one of 8 pages which provides a finer Z vertex position correction. In the first case the rough Total Et address to the Momentum Look Up Memories typically has 1/4 GeV resolution and in the second case this part of the momentum look up address typically has 1/2 GeV resolution. To implement page selection, the two highest order address lines (A10 and A11) of the Momentum Look Up Memories are driven by Timing & Sync Signals L and M. The third page selection address line (A0), when it is used, is driven by Timing & Sync Signal K. These Timing & Sync lines typically carry information about the Z position of the interaction. Thus, there is space in the 2k by 8 Momentum Look Up Memories for either 4 different maps of Total Et vs Px or Py with 1/4 GeV Total Et address resolution (case 1 above) or else there is space for 8 different maps of Total Et vs Px or Py with 1/2 GeV Total Et address resolution (case 2 above). The interaction Z position will determine which of the maps is used for the look up on a beam crossing by beam crossing basis. For more details about operating the CTFE Rev B card in either of the two momentum look up modes see the section about CTFE programmable parts below. Because momentum is a vector quantity, the Px and Py components are handled separately on the CTFE Card. The components from the 4 channels are added separately to form the Board Total Px and the Board Total Py. These two 10 bit signals are driven off card using differential ECL drivers and go to separate Adder Trees. Energy Signal Processing In each CTFE channel the EM and HD sections each have a separate Energy Look Up Memory. These 2k by 8 registered memories provide 8 maps that can be used to transform the 8 bit Et quantities coming from the ADC Data multiplexer-latch's into any useful form. Either one or two look up can be made per beam crossing. 1. If only one look up is made per beam crossing then all 8 maps may be used to hold accurate vertex Z position corrected data about one transformation (this typically would be an accurate Et). 2. If two look ups are made for each beam crossing; the first will typically be to map the ADC Data multiplexer-latch's Et data into a Z position corrected Et and the second look up to map the ADC Data multiplexer-latch's Et data into E or some other interesting quantity (perhaps Et only for channels above some high threshold). This size memory provides space for 4 Z position dependant maps for both the first and the second look up. The ADC Data multiplexer-latch's from each section provide the low order 8 bits of address to these Energy Look Up Memories. The high order 3 bits comes from Timing & Sync Signals D, E, and J. These are connected to the A8, A9, and A10 address lines on the Energy Look Up Memory devices. If only one lookup is being used per beam crossing then all three of these Timing & Sync Signals will carry information about the vertex Z position. If two look ups are being used per beam crossing then the Z position is carried on two of these Timing & Sync Signals and the third one carried a signal indicating indicating which of the two look ups (first or second) is taking place. The 8 bit results from the EM Energy Look Up Memories and from the HD Energy Look Up Memories are added separately to form the 10 bit Board Total EM Energy Signal and the 10 bit Board Total HD Energy Signal. These signal are driven off card as differential ECL signals and go to the EM Energy Adder Tree and the HD Energy Adder Tree. Cluster Threshold Comparators Total Et Clusters A Total Et signal is made by adding the result of the first EM Energy look-up to the result of the first HD Energy look-up. This 9 bit quantity, the vertex Z position corrected Total Et signal, is latched and is made available on the rear connectors as a differential ECL signal. There are 4 of these Z position corrected Total Et signals, one for each channel on the CTFE Card. In each channel, the 8 most significant bits of the latched Z position corrected Total Et signal are also presented to four 74LS684 comparators called the Total Et Cluster Threshold Comparators. The reference values for these comparators are loaded into 74ALS990 read-back latches via C-Bus operations. The four outputs from these Total Et Comparators pass through a 22V10 PAL where they are only buffered. These Total Et Cluster Threshold Comparator signals go high if and only if the Total Et Cluster signal is greater than its threshold reference value. These buffered Total Et Cluster Threshold Comparator signals are then sending end series terminated and routed as TTL signals via connectors and traces on the backplane to a CHTCR Card. EM Et Clusters The EM Et signal (Z corrected) from the first EM Energy look-up is presented to one input of four 74LS684 comparators that are called the EM Et Cluster Threshold Comparators. The reference values for these comparators are stored in 74ALS990 read-back latches. These latches are loaded via C-Bus cycles. The HD Et signal (Z corrected) from the first HD Energy look-up is presented to one input of another four 74LS684 comparators that are called the HD Veto Comparators. The reference values for these comparators are, once again, stored in read-back latches that are loaded from the C-Bus. For each channel on the CTFE Card the four outputs of the EM Et Cluster Threshold Comparators and the four HD Veto Comparators are combined, in pairs, in the 22V10 PAL and the result from each pair is latched. The resulting output can be high if and only if the EM Et Cluster Threshold Comparator for a given pair is over its threshold and the HD Veto Comparator for that pair is under its threshold. These latched outputs are then routed as sending end series terminated TTL signals via backplane connectors and traces to a CHTCR Card. Analog Reference Supply Section The CTFE Card also includes three analog voltage reference supplies. These supplies provide the reference values to the flash ADC's (+1.000 Volts and -1.000 Volts) and the offset reference to the differential input stage (-1.352 Volts). C-BUS Interface Section The last section of the CTFE Card is the C Bus interface. This section contains the logic for reading and writing to the registers on the CTFE card (note the CTFE card used 2 Card Addresses) and the logic to distribute the timing signals on the card (note the CTFE card receives 12 Timing & Sync Signals, not the standard 8). The CTFE Card can be used with the fast C Bus read cycle. PROGRAMMING ---------------- Because of the number of registers used on the CTFE Card and in order to maintain compatibility between the 29520 and 29525 readout schemes, the CTFE Card uses two Card Addresses. The even Card Address, the lower one of the two adjacent Card Addresses, is used to read the 29525's and the upper Card Address, the odd address is used for the control registers. Programming at the Lower Card Address The lower (even) Card Address will select 64 registers which contain data from the 8 ADC. There are 8 registers in each of 2 pipes for each ADC on the CTFE Card. These registers contain a history starting from the current beam crossing back through 7 previous beam crossings. Data is Loaded into and Shifted through these registers on each positive edge of Timing & Sync Signal B. Each ADC is serviced by an Am29525 pipeline register IC which internally provides two pipes of 8 registers each. The two pipes are used for double buffering this Front-End data. These registers will contain random data upon power up and will only contain real data after it is loaded from the A to D converters (note these registers are read only registers). Data read from any of these registers will have the Low Order bit from the ADC in the Low Order position of the C Bus byte. The detailed definition of the Function Addresses at the lower Card Address which are used to read the ADC data follow: LOWER CARD ADDRESS FUNCTION ADDRESSES OF THE 29525 REGISTERS ---------------------------------------------------------------- FUNCTION ADDRESS FUNCTION -------- ---------------- 0 ADC EM CHANNEL 1 29525 REGISTER 7 | 1 ADC HD CHANNEL 1 29525 REGISTER 7 | 2 ADC EM CHANNEL 2 29525 REGISTER 7 | 3 ADC HD CHANNEL 2 29525 REGISTER 7 | OLDEST 4 ADC EM CHANNEL 3 29525 REGISTER 7 | DATA 5 ADC HD CHANNEL 3 29525 REGISTER 7 | 6 ADC EM CHANNEL 4 29525 REGISTER 7 | 7 ADC HD CHANNEL 4 29525 REGISTER 7 | 32 ADC EM CHANNEL 1 29525 REGISTER 6 | 33 ADC HD CHANNEL 1 29525 REGISTER 6 | 34 ADC EM CHANNEL 2 29525 REGISTER 6 | NEXT 35 ADC HD CHANNEL 2 29525 REGISTER 6 | TO THE 36 ADC EM CHANNEL 3 29525 REGISTER 6 | OLDEST 37 ADC HD CHANNEL 3 29525 REGISTER 6 | DATA 38 ADC EM CHANNEL 4 29525 REGISTER 6 | 39 ADC HD CHANNEL 4 29525 REGISTER 6 | 64 ADC EM CHANNEL 1 29525 REGISTER 5 | 65 ADC HD CHANNEL 1 29525 REGISTER 5 | 66 ADC EM CHANNEL 2 29525 REGISTER 5 | 2ND 67 ADC HD CHANNEL 2 29525 REGISTER 5 | NEXT 68 ADC EM CHANNEL 3 29525 REGISTER 5 | TO THE 69 ADC HD CHANNEL 3 29525 REGISTER 5 | OLDEST 70 ADC EM CHANNEL 4 29525 REGISTER 5 | DATA 71 ADC HD CHANNEL 4 29525 REGISTER 5 | 96 ADC EM CHANNEL 1 29525 REGISTER 4 | 97 ADC HD CHANNEL 1 29525 REGISTER 4 | 98 ADC EM CHANNEL 2 29525 REGISTER 4 | 3RD 99 ADC HD CHANNEL 2 29525 REGISTER 4 | NEXT 100 ADC EM CHANNEL 3 29525 REGISTER 4 | TO THE 101 ADC HD CHANNEL 3 29525 REGISTER 4 | OLDEST 102 ADC EM CHANNEL 4 29525 REGISTER 4 | DATA 103 ADC HD CHANNEL 4 29525 REGISTER 4 | 128 ADC EM CHANNEL 1 29525 REGISTER 3 | 129 ADC HD CHANNEL 1 29525 REGISTER 3 | 130 ADC EM CHANNEL 2 29525 REGISTER 3 | 3RD 131 ADC HD CHANNEL 2 29525 REGISTER 3 | NEXT 132 ADC EM CHANNEL 3 29525 REGISTER 3 | TO THE 133 ADC HD CHANNEL 3 29525 REGISTER 3 | NEWEST 134 ADC EM CHANNEL 4 29525 REGISTER 3 | DATA 135 ADC HD CHANNEL 4 29525 REGISTER 3 | 160 ADC EM CHANNEL 1 29525 REGISTER 2 | 161 ADC HD CHANNEL 1 29525 REGISTER 2 | 162 ADC EM CHANNEL 2 29525 REGISTER 2 | 2ND 163 ADC HD CHANNEL 2 29525 REGISTER 2 | NEXT 164 ADC EM CHANNEL 3 29525 REGISTER 2 | TO THE 165 ADC HD CHANNEL 3 29525 REGISTER 2 | NEWEST 166 ADC EM CHANNEL 4 29525 REGISTER 2 | DATA 167 ADC HD CHANNEL 4 29525 REGISTER 2 | 192 ADC EM CHANNEL 1 29525 REGISTER 1 | 193 ADC HD CHANNEL 1 29525 REGISTER 1 | 194 ADC EM CHANNEL 2 29525 REGISTER 1 | NEXT 195 ADC HD CHANNEL 2 29525 REGISTER 1 | TO THE 196 ADC EM CHANNEL 3 29525 REGISTER 1 | NEWEST 197 ADC HD CHANNEL 3 29525 REGISTER 1 | DATA 198 ADC EM CHANNEL 4 29525 REGISTER 1 | 199 ADC HD CHANNEL 4 29525 REGISTER 1 | 224 ADC EM CHANNEL 1 29525 REGISTER 0 | 225 ADC HD CHANNEL 1 29525 REGISTER 0 | 226 ADC EM CHANNEL 2 29525 REGISTER 0 | 227 ADC HD CHANNEL 2 29525 REGISTER 0 | NEWEST 228 ADC EM CHANNEL 3 29525 REGISTER 0 | DATA 229 ADC HD CHANNEL 3 29525 REGISTER 0 | 230 ADC EM CHANNEL 4 29525 REGISTER 0 | 231 ADC HD CHANNEL 4 29525 REGISTER 0 | Programming at the Upper Card Address The control registers used on CTFE Card fall into three categories. First, function addresses 0 through 7 are used to supply data to the 74ALS990 readback latches which drive the AD558 D to A converters used in the front end amplifier circuit for pedestal control. The second category includes the 48 registers, Function Address 8 through 55, used to load the reference thresholds for the EM Et Cluster Threshold Comparators, the Hadronic Veto Comparators, and the Total Et Cluster Threshold Comparators. The third category of control registers includes the CTFE Board Status and Control Register (FA=80), the Mux-Latch Clock Control Register (FA=81), and the Test Data Register (FA=82). Details of Function Addresses 0 through 7 which are used to load data into the Pedestal Control (offset) DAC's are shown below. The bits in each byte at these Function Addresses are in natural order (the low order bit on the C Bus is loaded into the low order position in the DAC). Function Addresses 0 through 7 will contain random data upon power up and must be initialized to set the offsets of the front end amplifiers. DAC PEDESTAL CONTROL REGISTERS UPPER CARD ADDRESS ------------------------------------------------------ FUNCTION ADDRESS FUNCTION -------- ---------------- 0 Pedestal Control DAC Data for EM Channel 1 1 Pedestal Control DAC Data for HD Channel 1 2 Pedestal Control DAC Data for EM Channel 2 3 Pedestal Control DAC Data for HD Channel 2 4 Pedestal Control DAC Data for EM Channel 3 5 Pedestal Control DAC Data for HD Channel 3 6 Pedestal Control DAC Data for EM Channel 4 7 Pedestal Control DAC Data for HD Channel 4 The following 48 read write registers are used to hold the Reference Data for the EM Et Cluster Threshold Comparators, for the Hadronic Veto Threshold Comparators, and for the Total Et Threshold Comparators. These 48 registers are in the Function Address range 16 through 75. The bits in each byte at these Function Addresses are in natural order (the low order bit on the C Bus is loaded into the low order position in the threshold register). Recall that the scale for the Total Et Threshold value is twice that of either the EM Et or the Hadronic Veto Threshold values. This is because the Total Et comparator looks at the top 8 bits of the 9 bit Total Et signal. Typically the LSB of either the EM Et Threshold or of the Hadronic Veto Threshold will be 1/4 GeV while the LSB of the Total Et Threshold will be 1/2 GeV. THRESHOLD COMPARATOR REFERENCE VALUE REGISTERS UPPER CARD ADDRESS ---------------------------------------------------------------------- FUNCTION ADDRESS FUNCTION -------- ---------------- 16 Reference for EM Et Threshold Comparator #1 Channel #1 17 Reference for EM Et Threshold Comparator #2 Channel #1 18 Reference for EM Et Threshold Comparator #3 Channel #1 19 Reference for EM Et Threshold Comparator #4 Channel #1 20 Reference for the Hadronic Veto of EM Comparator #1 Channel #1 21 Reference for the Hadronic Veto of EM Comparator #2 Channel #1 22 Reference for the Hadronic Veto of EM Comparator #3 Channel #1 23 Reference for the Hadronic Veto of EM Comparator #4 Channel #1 24 Reference for Total Et Threshold Comparator #1 Channel #1 25 Reference for Total Et Threshold Comparator #2 Channel #1 26 Reference for Total Et Threshold Comparator #3 Channel #1 27 Reference for Total Et Threshold Comparator #4 Channel #1 32 Reference for EM Et Threshold Comparator #1 Channel #2 33 Reference for EM Et Threshold Comparator #2 Channel #2 34 Reference for EM Et Threshold Comparator #3 Channel #2 35 Reference for EM Et Threshold Comparator #4 Channel #2 36 Reference for the Hadronic Veto of EM Comparator #1 Channel #2 37 Reference for the Hadronic Veto of EM Comparator #2 Channel #2 38 Reference for the Hadronic Veto of EM Comparator #3 Channel #2 39 Reference for the Hadronic Veto of EM Comparator #4 Channel #2 40 Reference for Total Et Threshold Comparator #1 Channel #2 41 Reference for Total Et Threshold Comparator #2 Channel #2 42 Reference for Total Et Threshold Comparator #3 Channel #2 43 Reference for Total Et Threshold Comparator #4 Channel #2 48 Reference for EM Et Threshold Comparator #1 Channel #3 49 Reference for EM Et Threshold Comparator #2 Channel #3 50 Reference for EM Et Threshold Comparator #3 Channel #3 51 Reference for EM Et Threshold Comparator #4 Channel #3 52 Reference for the Hadronic Veto of EM Comparator #1 Channel #3 53 Reference for the Hadronic Veto of EM Comparator #2 Channel #3 54 Reference for the Hadronic Veto of EM Comparator #3 Channel #3 55 Reference for the Hadronic Veto of EM Comparator #4 Channel #3 56 Reference for Total Et Threshold Comparator #1 Channel #3 57 Reference for Total Et Threshold Comparator #2 Channel #3 58 Reference for Total Et Threshold Comparator #3 Channel #3 59 Reference for Total Et Threshold Comparator #4 Channel #3 64 Reference for EM Et Threshold Comparator #1 Channel #4 65 Reference for EM Et Threshold Comparator #2 Channel #4 66 Reference for EM Et Threshold Comparator #3 Channel #4 67 Reference for EM Et Threshold Comparator #4 Channel #4 68 Reference for the Hadronic Veto of EM Comparator #1 Channel #4 69 Reference for the Hadronic Veto of EM Comparator #2 Channel #4 70 Reference for the Hadronic Veto of EM Comparator #3 Channel #4 71 Reference for the Hadronic Veto of EM Comparator #4 Channel #4 72 Reference for Total Et Threshold Comparator #1 Channel #4 73 Reference for Total Et Threshold Comparator #2 Channel #4 74 Reference for Total Et Threshold Comparator #3 Channel #4 75 Reference for Total Et Threshold Comparator #4 Channel #4 The CTFE Card has 3 registers that are of the control status type. These are called the Board Control Status Register, the MUX-LATCH Clock Control Register, and the Test Data Register. The Function Address and the definition of the bits in each of theses registers follow. Function Address 80 is the Board Control Status Register for the CTFE Card. The function of the eight bits in this register are defined in the following table. CTFE BOARD CONTROL STATUS REGISTER DEFINITION OF THE BITS ----------------------------------------------------------------- DATA BIT FUNCTION ------ -------------------------------------------------------------- 0 HI --> MUX-LATCH selects ADC Data, LOW --> Test Reg Data 1 LOW-HI-LOW --> Clock the MUX-LATCH, LOW --> Normal Operation 2 Not Used 3 Not Used 4 Not Used 5 LOW-HI-LOW -> Clock the Test Data Register, LOW -> Normal 6 This bit controls the mode of the Test Data Register, see table 7 This bit controls the mode of the Test Data Register, see table Control Status Register A WRITE to the Test Data Register BIT 7 BIT 6 will cause the following action -------------- --------------------------------- L L CLEAR the Test Data Register L H DECREMENT the TDR by 1 H L LOAD the TDR with the written value H H INCREMENT the TDR by 1 Function Address 81 is the Mux-Latch Clock Control Register. This register is used to control which of the 74F399 ADC Data Multiplexer-Latches receive a clock signal from either the Timing & Sync Bus or from the Board Control Status Register Bit 2. When a bit in the Mux-Latch Clock Control Register is set high it enables the corresponding CTFE Card channel (EM or HD section) to receive the MUX_LATCH Clock. CTFE CARD MUX-LATCH CLOCK CONTROL REGISTER DEFINITION OF THE BITS --------------------------------------------------------------------- DATA BIT NUMBER FUNCTION ----------- --------------------------------------------------------- 0 HIGH ---> CH #1 EM IS ENABLED TO RECEIVE THE MUX-LTCH CLK 1 HIGH ---> CH #1 HD IS ENABLED TO RECEIVE THE MUX-LTCH CLK 2 HIGH ---> CH #2 EM IS ENABLED TO RECEIVE THE MUX-LTCH CLK 3 HIGH ---> CH #2 HD IS ENABLED TO RECEIVE THE MUX-LTCH CLK 4 HIGH ---> CH #3 EM IS ENABLED TO RECEIVE THE MUX-LTCH CLK 5 HIGH ---> CH #3 HD IS ENABLED TO RECEIVE THE MUX-LTCH CLK 6 HIGH ---> CH #4 EM IS ENABLED TO RECEIVE THE MUX-LTCH CLK 7 HIGH ---> CH #4 HD IS ENABLED TO RECEIVE THE MUX-LTCH CLK Function Address 82 is the Test Data Register. With this register one can load and read the data in the Test Data Register. The action of the Test Data Register is controlled by the upper two bits of Function Address 80 as described above. The Test Data Register is implemented with a 74AS867 integrated circuit. For all operations, except the asynchronous clear, this IC requires a clock signal before the operation is performed. The clock signal to this IC for the increment, decrement, or load operations can be provided either by a CBUS write cycle to FA=82, the Test Data Register, or by setting bit #5 in the Board Control Status Register, FA=80, LOW-HIGH-LOW. Typical Programming of the CTFE Rev B Cards There are no registers to program at the lower Card Address. The typical value read from a 29525 register in the Function Address range of 0 through 231 at the lower Card Address will depend on the pedestal value that the ADC's are tuned to. A typical value might be 0F in hex. Noise of about plus or minus 1 count around the pedestal value would be typical (less on the EM channels than on the HD channels). About 10% of the channels may show significant energy deposit, a few to 10 GeV, or a few to 40 (decimal) counts on top of the pedestal. At the upper Card Address all registers are Read-Write registers and they are all a full 8 bits (i.e. you should always be able to read back what you have written). The DAC Pedestal Control registers are in the Function Address range 0 through 7. A typical value loaded into these registers depends on the pedestal value that the ADC's are being tuned to. A typical ADC pedestal in the range of 0F hex will require a value of about 30 hex to be loaded into the DAC Pedestal Control register. The threshold comparator reference registers are in the Function Address range 16 through 75. Typical values loaded into these registers will be in the range of 10 GeV. With the L1 Trigger operating at 1/4 GeV per bit from the ADC's or energy look up memories the 10 GeV threshold for the EM Et Threshold Comparator or the Hadronic Veto Comparator would require loading a value of 40 decimal (plus any pedestal) into their threshold reference registers. The Total Et Threshold Comparators would require loading one half of this value (i.e. 20 decimal plus any pedestal) into their threshold reference registers to obtain the same threshold of 10 GeV. A typical configuration of the Board Control Status Register (FA = 80) would be: select ADC data, do not force the ADC Data Multiplexer-Latch clock line, do not force the Test Data Register clock line, select the Load function for Test Data Register when it is written to. To select this configuration of the CTFE card would require writing 128 + 1 into the Board Control Status Register. It would be typical to enable the EM and HD section of all 4 channels on a CTFE card to receive the ADC Data Multiplexer-Latch Clock. To do this one would load 255 into the Mux-Latch Clock Control Register at Function Address 81. If the Test Data Register is not being used it would be typical to load zero into it at Function Address 82. CTFE: CARDS ADDRESS SELECTOR SWITCH -------------------------------------- This switch controls the Card Address at which this card will wake up. When a switch is closed the corresponding bit in the Card Address is a 0 and when a switch is open then the corresponding bit is a 1. CARD ADDRESS SWITCH SECTION CARD ADDRESS BIT BIT VALUE ---------------- ------------------ ------------ 1 6 32 2 5 16 3 4 8 4 3 4 5 2 2 6 ALWAYS CLOSED 1 7 ALWAYS CLOSED NO CONNECTION 8 ALWAYS CLOSED NO CONNECTION The CTFE Card uses 8 LED's to indicate the status of various function on the Card. CTFE CARD LED's --------------------------------------------------------------------------- LED REF BOARD NUMBER LOCATION LABEL FUNCTION ------- --------- ------- -------------------------------------- DS1 LEFT MOST WAKE UP "on" --> The card is being addresed by C-BUS DS2 ADC DC Status of the CLK line to the 74F399 ADC Data Latches. LED "on" --> CLK is High. Positive Edge on line updates the latch. DS3 525 LS Latch-Shift line to the 29525's, same as the status of T&S Bus Signal B. LED "on" --> signal is High, Pos Edge Active DS4 525 I0 Status of the 29525 I0 signal. LED "on" --> I0 is High --> Write into pipe B. Signal I0 (and this LED) are always the inverse of the T&S Bus Signal A. DS5 525 S3 Status of the 29525 S3 signal. LED "on" --> S3 is High --> Reading from B pipe. Signal S3 (and this LED) are always the inverse of the T&S Bus Signal C. DS6 LUM CLK Status of the clock line to the registered PROM's. Always the same as the 2X Clock Signal and the T&S Bus G Signal. LED "on" --> this signal is High. Pos Edge Update. DS7 TEt LT Status of the Clock to the 74AS821 Total Et Latches. LED "on" --> line is High. Positive Edge Update. Always the same as the 2X Clock High AND the X Clock High. DS8 RIGHT MOST CMP CLK Status of the Clock to the PAL 22V10 Comparator Latches. LED "on" --> line is High. Positive Edge Active. Always the same as 2X Clock High AND X Clock High. CONNECTORS ------------ CBUS ------------------------------------------------------------------------- | |. J1 | |. J2 | |. J3 | |. J4 | | | ---------- ---------- ---------- ---------- | | | | | | | | J5,J6 J7,J8 | | | | CH 1 CH 2 CH 3 CH 4 | | ---- ---- ---- ---- | | H E H E H E H E | | D M D M D M D M | | | | +------+ +------+ +------+ +------+ | | |. J9 | |. J10 | |. J11 | |. J12 | | | +------+ +------+ +------+ +------+ | | | | J -------- J J -------- J J -------- J J -------- J J | | 1 | .| 1 1 | .| 1 2 | .| 2 2 | .| 2 1 | | 4 | J15 | 6 7 | J18 | 9 0 | J21 | 2 3 | J24 | 5 3 LED's | ------------------------------------------------------------------------- Front of the Card J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -5.2 V VEE 14 Power -5.2 V VEE 15 Power -5.2 V VEE 16 Power -5.2 V VEE 17 Unused 18 Power -5.2 V VEE 19 Power -5.2 V VEE 20 Power -5.2 V VEE 21 Power -5.2 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 brown CH #1 Total Et Bit #1 Non-inverted 1 33 tan CH #1 Total Et Bit #1 Inverted 2 66 red CH #1 Total Et Bit #2 Non-inverted 3 34 tan CH #1 Total Et Bit #2 Inverted 4 67 orange CH #1 Total Et Bit #3 Non-inverted 5 35 tan CH #1 Total Et Bit #3 Inverted 6 68 yellow CH #1 Total Et Bit #4 Non-inverted 7 36 tan CH #1 Total Et Bit #4 Inverted 8 69 green CH #1 Total Et Bit #5 Non-inverted 9 37 tan CH #1 Total Et Bit #5 Inverted 10 70 blue CH #1 Total Et Bit #6 Non-inverted 11 38 tan CH #1 Total Et Bit #6 Inverted 12 71 violet CH #1 Total Et Bit #7 Non-inverted 13 39 tan CH #1 Total Et Bit #7 Inverted 14 72 grey CH #1 Total Et Bit #8 Non-inverted 15 40 tan CH #1 Total Et Bit #8 Inverted 16 73 white CH #1 Total Et Bit #9 Non-inverted 17 41 tan CH #1 Total Et Bit #9 Inverted 18 74 black CH #2 Total Et Bit #1 Non-inverted 19 42 tan CH #2 Total Et Bit #1 Inverted 20 75 brown CH #2 Total Et Bit #2 Non-inverted 21 43 tan CH #2 Total Et Bit #2 Inverted 22 76 red CH #2 Total Et Bit #3 Non-inverted 23 44 tan CH #2 Total Et Bit #3 Inverted 24 77 orange CH #2 Total Et Bit #4 Non-inverted 25 45 tan CH #2 Total Et Bit #4 Inverted 26 78 yellow CH #2 Total Et Bit #5 Non-inverted 27 46 tan CH #2 Total Et Bit #5 Inverted 28 79 green CH #2 Total Et Bit #6 Non-inverted 29 47 tan CH #2 Total Et Bit #6 Inverted 30 80 blue CH #2 Total Et Bit #7 Non-inverted 31 48 tan CH #2 Total Et Bit #7 Inverted 32 81 violet CH #2 Total Et Bit #8 Non-inverted 33 49 tan CH #2 Total Et Bit #8 Inverted 34 82 grey CH #2 Total Et Bit #9 Non-inverted 35 50 tan CH #2 Total Et Bit #9 Inverted 36 83 white SPARE DRIVER #1 Non-Inverted 37 51 tan SPARE DRIVER #1 Inverted 38 84 black SPARE DRIVER #2 Non-Inverted 39 52 tan SPARE DRIVER #2 Inverted 40 85 CH #1 EM Cluster COMP #4 86 CH #1 EM Cluster COMP #3 87 CH #1 EM Cluster COMP #2 88 CH #1 EM Cluster COMP #1 53 CH #1 TOTAL Et CLUSTER COMP #1 54 CH #1 TOTAL Et CLUSTER COMP #2 55 CH #1 TOTAL Et CLUSTER COMP #3 56 CH #1 TOTAL Et CLUSTER COMP #4 89 CH #2 EM Cluster COMP #4 90 CH #2 EM Cluster COMP #3 91 CH #2 EM Cluster COMP #2 92 CH #2 EM Cluster COMP #1 57 CH #2 TOTAL Et CLUSTER COMP #1 58 CH #2 TOTAL Et CLUSTER COMP #2 59 CH #2 TOTAL Et CLUSTER COMP #3 60 CH #2 TOTAL Et CLUSTER COMP #4 93 Board Total EM Bit #1 Non-inverted 61 Board Total EM Bit #1 Inverted 94 Board Total EM Bit #2 Non-inverted 62 Board Total EM Bit #2 Inverted 95 Board Total EM Bit #3 Non-inverted 63 Board Total EM Bit #3 Inverted 96 Board Total EM Bit #4 Non-inverted 64 Board Total EM Bit #4 Inverted ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Power +5.0 V VCC 12 Unused 13 Power +5.0 V VCC 14 Power +5.0 V VCC 15 Power +5.0 V VCC 16 Power +5.0 V VCC 17 Unused 18 Power +5.0 V VCC 19 Power +5.0 V VCC 20 Power +5.0 V VCC 21 Power +5.0 V VCC 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 Board Total EM Bit #5 Non-inverted 33 Board Total EM Bit #5 Inverted 66 Board Total EM Bit #6 Non-inverted 34 Board Total EM Bit #6 Inverted 67 Board Total EM Bit #7 Non-inverted 35 Board Total EM Bit #7 Inverted 68 Board Total EM Bit #8 Non-inverted 36 Board Total EM Bit #8 Inverted 69 Board Total EM Bit #9 Non-inverted 37 Board Total EM Bit #9 Inverted 70 Board Total EM Bit #10 Non-inverted 38 Board Total EM Bit #10 Inverted 71 Board Total Px Bit #1 Non-inverted 39 Board Total Px Bit #1 Inverted 72 Board Total Px Bit #2 Non-inverted 40 Board Total Px Bit #2 Inverted 73 Board Total Px Bit #3 Non-inverted 41 Board Total Px Bit #3 Inverted 74 Board Total Px Bit #4 Non-inverted 42 Board Total Px Bit #4 Inverted 75 Board Total Px Bit #5 Non-inverted 43 Board Total Px Bit #5 Inverted 76 Board Total Px Bit #6 Non-inverted 44 Board Total Px Bit #6 Inverted 77 Board Total Px Bit #7 Non-inverted 45 Board Total Px Bit #7 Inverted 78 Board Total Px Bit #8 Non-inverted 46 Board Total Px Bit #8 Inverted 79 Board Total Px Bit #9 Non-inverted 47 Board Total Px Bit #9 Inverted 80 Board Total Px Bit #10 Non-inverted 48 Board Total Px Bit #10 Inverted 81 Board Total Py Bit #1 Non-inverted 49 Board Total Py Bit #1 Inverted 82 Board Total Py Bit #2 Non-inverted 50 Board Total Py Bit #2 Inverted 83 Board Total Py Bit #3 Non-inverted 51 Board Total Py Bit #3 Inverted 84 Board Total Py Bit #4 Non-inverted 52 Board Total Py Bit #4 Inverted 85 Board Total Py Bit #5 Non-inverted 53 Board Total Py Bit #5 Inverted 86 Board Total Py Bit #6 Non-inverted 54 Board Total Py Bit #6 Inverted 87 Board Total Py Bit #7 Non-inverted 55 Board Total Py Bit #7 Inverted 88 Board Total Py Bit #8 Non-inverted 56 Board Total Py Bit #8 Inverted 89 Board Total Py Bit #9 Non-inverted 57 Board Total Py Bit #9 Inverted 90 Board Total Py Bit #10 Non-inverted 58 Board Total Py Bit #10 Inverted 91 Board Total HD Bit #1 Non-inverted 59 Board Total HD Bit #1 Inverted 92 Board Total HD Bit #2 Non-inverted 60 Board Total HD Bit #2 Inverted 93 Board Total HD Bit #3 Non-inverted 61 Board Total HD Bit #3 Inverted 94 Board Total HD Bit #4 Non-inverted 62 Board Total HD Bit #4 Inverted 95 Board Total HD Bit #5 Non-inverted 63 Board Total HD Bit #5 Inverted 96 Board Total HD Bit #6 Non-inverted 64 Board Total HD Bit #6 Inverted ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power +5.0 V VCC 13 Power +5.0 V VCC 14 Power +5.0 V VCC 15 Power +5.0 V VCC 16 Unused 17 Power +5.0 V VCC 18 Power +5.0 V VCC 19 Power +5.0 V VCC 20 Power +5.0 V VCC 21 Unused 22 Power +5.0 V VCC 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 Board Total HD Bit #7 Non-inverted 33 Board Total HD Bit #7 Inverted 66 Board Total HD Bit #8 Non-inverted 34 Board Total HD Bit #8 Inverted 67 Board Total HD Bit #9 Non-inverted 35 Board Total HD Bit #9 Inverted 68 Board Total HD Bit #10 Non-inverted 36 Board Total HD Bit #10 Inverted 69 CH #3 EM Cluster COMP #4 70 CH #3 EM Cluster COMP #3 71 CH #3 EM Cluster COMP #2 72 CH #3 EM Cluster COMP #1 37 CH #3 TOTAL Et CLUSTER COMP #1 38 CH #3 TOTAL Et CLUSTER COMP #2 39 CH #3 TOTAL Et CLUSTER COMP #3 40 CH #3 TOTAL Et CLUSTER COMP #4 73 CH #4 EM Cluster COMP #4 74 CH #4 EM Cluster COMP #3 75 CH #4 EM Cluster COMP #2 76 CH #4 EM Cluster COMP #1 41 CH #4 TOTAL Et CLUSTER COMP #1 42 CH #4 TOTAL Et CLUSTER COMP #2 43 CH #4 TOTAL Et CLUSTER COMP #3 44 CH #4 TOTAL Et CLUSTER COMP #4 77 brown CH #3 Total Et Bit #1 Non-inverted 1 45 tan CH #3 Total Et Bit #1 Inverted 2 78 red CH #3 Total Et Bit #2 Non-inverted 3 46 tan CH #3 Total Et Bit #2 Inverted 4 79 orange CH #3 Total Et Bit #3 Non-inverted 5 47 tan CH #3 Total Et Bit #3 Inverted 6 80 yellow CH #3 Total Et Bit #4 Non-inverted 7 48 tan CH #3 Total Et Bit #4 Inverted 8 81 green CH #3 Total Et Bit #5 Non-inverted 9 49 tan CH #3 Total Et Bit #5 Inverted 10 82 blue CH #3 Total Et Bit #6 Non-inverted 11 50 tan CH #3 Total Et Bit #6 Inverted 12 83 violet CH #3 Total Et Bit #7 Non-inverted 13 51 tan CH #3 Total Et Bit #7 Inverted 14 84 grey CH #3 Total Et Bit #8 Non-inverted 15 52 tan CH #3 Total Et Bit #8 Inverted 16 85 white CH #3 Total Et Bit #9 Non-inverted 17 53 tan CH #3 Total Et Bit #9 Inverted 18 86 black CH #4 Total Et Bit #1 Non-inverted 19 54 tan CH #4 Total Et Bit #1 Inverted 20 87 brown CH #4 Total Et Bit #2 Non-inverted 21 55 tan CH #4 Total Et Bit #2 Inverted 22 88 red CH #4 Total Et Bit #3 Non-inverted 23 56 tan CH #4 Total Et Bit #3 Inverted 24 89 orange CH #4 Total Et Bit #4 Non-inverted 25 57 tan CH #4 Total Et Bit #4 Inverted 26 90 yellow CH #4 Total Et Bit #5 Non-inverted 27 58 tan CH #4 Total Et Bit #5 Inverted 28 91 green CH #4 Total Et Bit #6 Non-inverted 29 59 tan CH #4 Total Et Bit #6 Inverted 30 92 blue CH #4 Total Et Bit #7 Non-inverted 31 60 tan CH #4 Total Et Bit #7 Inverted 32 93 violet CH #4 Total Et Bit #8 Non-inverted 33 61 tan CH #4 Total Et Bit #8 Inverted 34 94 grey CH #4 Total Et Bit #9 Non-inverted 35 62 tan CH #4 Total Et Bit #9 Inverted 36 95 white SPARE DRIVER #3 Non-Inverted 37 63 tan SPARE DRIVER #3 Inverted 38 96 black SPARE DRIVER #4 Non-Inverted 39 64 tan SPARE DRIVER #4 Inverted 40 ---------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CON ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -5.2 V VEE 13 Power -5.2 V VEE 14 Power -5.2 V VEE 15 Power -5.2 V VEE 16 Unused 17 Power -5.2 V VEE 18 Power -5.2 V VEE 19 Power -5.2 V VEE 20 Power -5.2 V VEE 21 Unused 22 TSS-J Energy LUM Address A10 Non-Inverted IN NTSJ 23 TSS-J Energy LUM Address A10 Inverted IN ITSJ 24 TSS-K Momentum LUM Addrs A0 Non-Inverted IN NTSK 25 TSS-K Momentum LUM Addrs A0 Inverted IN ITSK 26 TSS-L Momentum LUM Addrs A9 Non-Inverted IN NTSL 27 TSS-L Momentum LUM Addrs A9 Inverted IN ITSL 28 TSS-M Momentum LUM Addrs A10 Non-Inverted IN NTSM 29 TSS-M Momentum LUM Addrs A10 Inverted IN ITSM 30 Ground GND 31 Ground GND 32 Ground GND 65 brown TSS-A SELECT WRITE A/B Non-inverted IN 1 NTSA 33 tan TSS-A SELECT WRITE A/B Inverted IN 2 ITSA 66 red TSS-B LATCH/SHIFT Non-inverted IN 3 NTSB 34 tan TSS-B LATCH/SHIFT Inverted IN 4 ITSB 67 orange TSS-C SELECT READ A/B Non-inverted IN 5 NTSC 35 tan TSS-C SELECT READ A/B Inverted IN 6 ITSC 68 yellow TSS-D Energy LUM Address A8 Non-inverted IN 7 NTSD 36 tan TSS-D Energy LUM Address A8 Inverted IN 8 ITSD 69 green TSS-E Energy LUM Address A9 Non-inverted IN 9 NTSE 37 tan TSS-E Energy LUM Address A9 Inverted IN 10 ITSE 70 blue TSS-F X-CLOCK SIGNAL Non-inverted IN 11 NTSF 38 tan TSS-F X-CLOCK SIGNAL Inverted IN 12 ITSF 71 violet TSS-G 2X-CLOCK SIGNAL Non-inverted IN 13 NACK 39 tan TSS-G 2X-CLOCK SIGNAL Inverted IN 14 IACK 72 grey TSS-H ADC-CLOCK Non-inverted IN 15 NTSH 40 tan TSS-H ADC-CLOCK Inverted IN 16 ITSH 73 white Card Address Bit#1 Non-inverted IN 17 NAC1 41 tan Card Address Bit#1 Inverted IN 18 IAC1 74 black Card Address Bit#2 Non-inverted IN 19 NAC2 42 tan Card Address Bit#2 Inverted IN 20 IAC2 75 brown Card Address Bit#3 Non-inverted IN 21 NAC3 43 tan Card Address Bit#3 Inverted IN 22 IAC3 76 red Card Address Bit#4 Non-inverted IN 23 NAC4 44 tan Card Address Bit#4 Inverted IN 24 IAC4 77 orange Card Address Bit#5 Non-inverted IN 25 NAC5 45 tan Card Address Bit#5 Inverted IN 26 IAC5 78 yellow Card Address Bit#6 Non-inverted IN 27 NAC6 46 tan Card Address Bit#6 Inverted IN 28 IAC6 79 green Function Address Bit#1 Non-inverted IN 29 NAF1 47 tan Function Address Bit#1 Inverted IN 30 IAF1 80 blue Function Address Bit#2 Non-inverted IN 31 NAF2 48 tan Function Address Bit#2 Inverted IN 32 IAF2 81 violet Function Address Bit#3 Non-inverted IN 33 NAF3 49 tan Function Address Bit#3 Inverted IN 34 IAF3 82 grey Function Address Bit#4 Non-inverted IN 35 NAF4 50 tan Function Address Bit#4 Inverted IN 36 IAF4 83 white Function Address Bit#5 Non-inverted IN 37 NAF5 51 tan Function Address Bit#5 Inverted IN 38 IAF5 84 black Function Address Bit#6 Non-inverted IN 39 NAF6 52 tan Function Address Bit#6 Inverted IN 40 IAF6 85 brown Function Address Bit#7 Non-inverted IN 41 NAF7 53 tan Function Address Bit#7 Inverted IN 42 IAF7 86 red Function Address Bit#8 Non-inverted IN 43 NAF8 54 tan Function Address Bit#8 Inverted IN 44 IAF8 87 orange Strobe Non-inverted IN 45 NSTB 55 tan Strobe Inverted IN 46 ISTB 88 yellow Direction Non-inverted IN 47 NDIR 56 tan Direction Inverted IN 48 IDIR 89 green Bidirectional Data Bit#1 Non-inverted 49 NDB1 57 tan Bidirectional Data Bit#1 Inverted 50 IDB1 90 blue Bidirectional Data Bit#2 Non-inverted 51 NDB2 58 tan Bidirectional Data Bit#2 Inverted 52 IDB2 91 violet Bidirectional Data Bit#3 Non-inverted 53 NDB3 59 tan Bidirectional Data Bit#3 Inverted 54 IDB3 92 grey Bidirectional Data Bit#4 Non-inverted 55 NDB4 60 tan Bidirectional Data Bit#4 Inverted 56 IDB4 93 white Bidirectional Data Bit#5 Non-inverted 57 NDB5 61 tan Bidirectional Data Bit#5 Inverted 58 IDB5 94 black Bidirectional Data Bit#6 Non-inverted 59 NDB6 62 tan Bidirectional Data Bit#6 Inverted 60 IDB6 95 brown Bidirectional Data Bit#7 Non-inverted 61 NDB7 63 tan Bidirectional Data Bit#7 Inverted 62 IDB7 96 red Bidirectional Data Bit#8 Non-inverted 63 NDB8 64 tan Bidirectional Data Bit#8 Inverted 64 IDB8 ----------------------------------------------------------------------------- CONNECTOR J5 THE FRONT PANEL ANALOG INPUT CONNECTOR EM-HD PAIR 1 ------------- ------------------------------------------------------------------------------ PIN NUMBER FUNCTION ------------------------------------------------------------------------------ 1 CENTER CONDUCTOR OF COAX POSITIVE INPUT EM CHANNEL 1 2 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 1 3 CENTER CONDUCTOR OF COAX NEGATIVE INPUT EM CHANNEL 1 4 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 3 5 CENTER CONDUCTOR OF COAX POSITIVE INPUT HD CHANNEL 1 6 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 5 7 CENTER CONDUCTOR OF COAX NEGATIVE INPUT HD CHANNEL 1 8 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 7 CONNECTOR J6 THE FRONT PANEL ANALOG INPUT CONNECTOR EM-HD PAIR 2 ------------- ------------------------------------------------------------------------------ PIN NUMBER FUNCTION ------------------------------------------------------------------------------ 1 CENTER CONDUCTOR OF COAX POSITIVE INPUT EM CHANNEL 2 2 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 1 3 CENTER CONDUCTOR OF COAX NEGATIVE INPUT EM CHANNEL 2 4 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 3 5 CENTER CONDUCTOR OF COAX POSITIVE INPUT HD CHANNEL 2 6 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 5 7 CENTER CONDUCTOR OF COAX NEGATIVE INPUT HD CHANNEL 2 8 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 7 CONNECTOR J7 THE FRONT PANEL ANALOG INPUT CONNECTOR EM-HD PAIR 3 ------------- ------------------------------------------------------------------------------ PIN NUMBER FUNCTION ------------------------------------------------------------------------------ 1 CENTER CONDUCTOR OF COAX POSITIVE INPUT EM CHANNEL 3 2 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 1 3 CENTER CONDUCTOR OF COAX NEGATIVE INPUT EM CHANNEL 3 4 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 3 5 CENTER CONDUCTOR OF COAX POSITIVE INPUT HD CHANNEL 3 6 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 5 7 CENTER CONDUCTOR OF COAX NEGATIVE INPUT HD CHANNEL 3 8 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 7 CONNECTOR J8 THE FRONT PANEL ANALOG INPUT CONNECTOR EM-HD PAIR 4 ------------- ------------------------------------------------------------------------------ PIN NUMBER FUNCTION ------------------------------------------------------------------------------ 1 CENTER CONDUCTOR OF COAX POSITIVE INPUT EM CHANNEL 4 2 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 1 3 CENTER CONDUCTOR OF COAX NEGATIVE INPUT EM CHANNEL 4 4 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 3 5 CENTER CONDUCTOR OF COAX POSITIVE INPUT HD CHANNEL 4 6 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 5 7 CENTER CONDUCTOR OF COAX NEGATIVE INPUT HD CHANNEL 4 8 SHIELD OF THE COAX WITH CENTER CONDUCTOR ON PIN 7 DESCRIPTION OF THE CTFE CARD PALS ----------------------------------- There are 4 PAL's on the CTFE card. There is one for each of the 4 channels. The PAL's are used to mix and latch the outputs from the various comparators. The signals from the Total Et Comparators pass straight through this PAL (these signals are just buffered). The signals from the EM Et Comparators are ANDed with the inverted signals form their HD Veto Comparators and the result of these AND's is stored in "D" latches. All 4 of the PAL's are the same except for the pin out of the input signals. U34 U57 U62 U47 PAL PIN CH #1 CH #2 CH #3 CH #4 NUMBER PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL -------- ------------ ------------ ------------ ------------ 1 CMP LTCH CLK CMP LTCH CLK CMP LTCH CLK CMP LTCH CLK 2 HD VETO 2 HD VETO 1 TET CMP 2 TET CMP 2 3 HD VETO 3 HD VETO 2 EM COMP 3 TET CMP 1 4 HD VETO 4 EM COMP 4 EM COMP 2 EM COMP 1 5 EM COMP 4 EM COMP 3 EM COMP 1 EM COMP 2 6 EM COMP 3 HD VETO 3 TET CMP 3 HD VETO 1 7 EM COMP 2 HD VETO 4 HD VETO 1 HD VETO 2 8 EM COMP 1 TET CMP 1 TET CMP 4 HD VETO 3 9 HD VETO 1 TET CMP 2 HD VETO 2 HD VETO 4 10 TET CMP 4 TET CMP 3 HD VETO 3 EM COMP 3 11 TET CMP 3 TET CMP 4 EM COMP 4 EM COMP 4 12 GND GND GND GND 13 OUT ENB OUT ENB OUT ENB OUT ENB 14 TET OUT 4 TET OUT 4 TET OUT 4 TET OUT 4 15 TET OUT 3 TET OUT 3 TET OUT 3 TET OUT 3 16 TET OUT 2 TET OUT 2 TET OUT 2 TET OUT 2 17 TET OUT 1 TET OUT 1 TET OUT 1 TET OUT 1 18 EM OUT 1 EM OUT 1 EM OUT 1 EM OUT 1 19 EM OUT 2 EM OUT 2 EM OUT 2 EM OUT 2 20 EM OUT 3 EM OUT 3 EM OUT 3 EM OUT 3 21 EM OUT 4 EM OUT 4 EM OUT 4 EM OUT 4 22 TET CMP 2 EM COMP 1 TET CMP 1 TET CMP 3 23 TET CMP 1 EM COMP 2 HD VETO 4 TET CMP 4 24 VCC VCC VCC VCC CTFE CARD PROGRAMMABLE DEVICES --------------------------------------------------------------------------- CH #1 CH #2 CH #3 CH #4 DEVICE TYPE ------- ------- ------- ------- --------------- ENERGY EM U214 U217 U226 U229 CY7C245A-25WC ENERGY HD U183 U186 U187 U190 CY7C245A-25WC MOMENTUM Px U131 U133 U135 U137 CY7C291A-35WC MOMENTUM Py U132 U134 U136 U138 CY7C291A-35WC COMPARATOR PAL U34 U57 U62 U47 PALCE22V10H-25PC The Px and Py Momentum look up PROM's may be setup to operate in two different modes. The number of page select address lines and the number of rough Total Et address lines must be configured to fit with the desired mode of Momentum Look Up Memory operation. 1. In this mode, a 9 bit rough Total Et signal is used as the lower 9 bits of the address to the Momentum Look Up Memories. The two highest order address bits are used to select one of 4 pages which provide the Z vertex position correction. Nothing special is required for this mode of operation. U158, U160, U162, and U164 the 74F283's are installed in their sockets unmodified. 2. In this mode, the LSB of the 9 bit rough Total Et signal is dropped thus freeing up a third address line on the Momentum Look Up Memories to be used to select one of 8 pages for vertex Z position correction. To operate in this mode, pin number 4 of the 74F283's must be cut off before they are installed in their sockets at: U158, U160, U162, and U164. Then a jumper wire is run from J5 to pin #4 of the socket at U158, from J6 to pin #4 of the socket at U160, from J7 to pin #4 of the socket at U162, and from J8 to pin #4 of the socket at U164. These jumpers provide the connection of Timing & Sync Signal K to the address pin A0 on the Momentum Look Up Memories. For more details about the Momentum and Energy look up PROM's on the CTFE Revision B Card see the document CTFE_DEV:CTFE_PROM_SPECIFICATIONS.TXT in the trigger account. CTFE Rev B Input Terminator-Attenuators --------------------------------------------------------------------------- Each channel (EM and HD pair) of the CTFE card uses and input terminator- attenuator to scale the energy signal that it receives from the BLS card into an approximate Et signal. The signal from the BLS card is scaled at 1.0 Volt differential equals 32 GeV. These terminator-attenuators are built on 16 pin headers and plug into the CTFE card near the front analog input connectors. Terminator-attenuator units are installed that are appropriate for the eta index coordinate where a particular CTFE card will be operated. HD OP-AMP EM OP-AMP I G G N I G G N N N N O N N N O V D D N V D D N 1 1 1 1 1 1 1 6 5 4 3 2 1 0 9 ------------------------------------------ | X X X X X X X X | | |\___ ___/| |\___ ___/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | \ |R| |R| |R| |R| |R| |R| |R| |R| | / |2| |1| |1| |2| |2| |1| |1| |2| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |O X X X X X X X X | ------------------------------------------ 1 2 3 4 5 6 7 8 G H H G G E E G N D D N N M M N D - + D D - + D INPUT INPUT Typical Resistor Values for the Input Terminator-Attenuators for use with 78 or 80 Ohm Differential Coax Transmission Lines and with the Least Significant Bit from the ADC's of 1/4 GeV Et ----------------------------------------------------------------- Eta Index Attenuator Gain R1 Ohms R2 Ohms --------- --------------- --------- --------- 1 0.5 40 40 7-8 0.25 60 20 Terminator-Attenuator Installation Locations ---------------------------------------------- CH #1 CH #2 CH #3 CH #4 ------- ------- ------- ------- Terminator_Attenuator J9 J10 J11 J12 BOARD HISTORY: REVISION A ---------------------------- BOARD ORDERS HISTORY: 20 Rev. A cards cards ordered on May 4, 1989. ETCH REVISION HISTORY: Rev. A ECO HISTORY: See TRGHARD:CTFE_FIXES_REV_A.TXT CARD SERIAL NUMBERS: 1 through 20 CARD ASSEMBLY INSTRUCTIONS: BOARD HISTORY: REVISION B ---------------------------- BOARD ORDERS HISTORY: 150 Rev. B cards cards ordered on March 1990. ETCH REVISION HISTORY: Rev. B ECO HISTORY: See the Revision B ECO section below CARD SERIAL NUMBERS: 21 through 170 CARD ASSEMBLY INSTRUCTIONS: TRGHARD_REV_B_ASSEMBLY.TXT POWER REQUIREMENTS -------------------------------------------------- VCC +5.0 Volts at 14.9 Amps typ 20.5 Amps max VEE -5.2 Volts at 2.3 Amps typ 2.4 Amps max VTT -2.0 Volts at 1.1 Amps DRAWINGS ------------------------------------------------------- List of all the drawings produced with drawing numbers. List of every paper written about this board. ECO List for the CTFE Revision B Cards ---------------------------------------- 1. The X Clock and the 2X Clock are not mixed correctly on the Rev B card to control the EM Et Comparator Latch in the comparator output PAL's. The description of how this should work in the above text is correct, and the print set timing diagram and its notes are correct. The EM Et Comparator PAL Latch should update when the 2X Clock goes High while the X Clock is High. Both the SCH section of the print set and the Rev B board etch are incorrect. See page number 10 of the Rev B print set. The following steps are needed to make the circuit operate correctly: A. IC U113 a 74AS04 should be installed in a 14 pin 0.3" socket. Pins #1 and #2 should be removed from this IC before it is installed. B. Then do one of the following: Either put a jumper between pins #1 and #2 of the socket at U113, or else solder a jumper between pins #2 and #5 of U92 a 74AS08. 2. The Function Addresses to control the offset DAC's (FA = 0 through FA = 7 at the upper Card Address) also unintentionally appear at Function Address = 8 through 15. At this time this does not cause any problems but, it could be corrected by connecting U259 (a 74ALS138) pin #5 and U234 (a 74HCT238) pin #4 to Function Address signal FA4. See page 12 of the Rev B print set. 3. The Function Addresses to control the Board CSR, the Mux-Latch Clock Control Register, and the Test Data Register (FA = 80, FA = 81, and FA = 82 at the upper Card Address) also unintentionally appear at Function Address = 88, 89, and 90. At this time this does not cause any problems but, it could be corrected by connecting U82 (a 74ALS138) pin #5 and U81 (a 74HCT238) pin #4 to Function Address signal FA4. See page 12 of the Rev B print set. CRITICAL TIMING PATHS in the L1 CALORIMETER TRIGGER --------------------------------------------------------- CTFE Rev. B 30-OCT-1990 Clock the 74F399 ADC Data Latch to Momentum Board Total Sum Driven Off Card DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal B "Latch-Shift" 10H125 2 ns 4 ns Buffer and Invert 74 ALS 540 7 ns 12 ns OR 74 AS 32 4 ns 6 ns Buffer and Invert 74 ALS 540 7 ns 12 ns AND 74 AS 08 4 ns 6 ns Latch Clock to new data on outputs 74 F 399 7 ns 9 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns Memory Access Address to Data CY7C291A-35WC 35 ns 35 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns ADD LSB thru Carry to Carry to Bit out 3x 74 F 283 19 ns 29 ns Drive the Momentum Board Total Sum off card 10 H 124 2 ns 4 ns -------- -------- Totals 113 ns 157 ns CTFE Rev. B 2x Clock to Energy Board Total Sum Driven off Card DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signal G "2x Clock" 10H125 2 ns 4 ns Buffer clock fan-out 74 ALS 541 9 ns 14 ns Registered Memory Clock to new data CY7C245A-25WC 12 ns 12 ns ADD LSB through the Carry to Carry out 2x 74 F 283 13 ns 20 ns ADD LSB thru Carry to Carry to Bit out 3x 74 F 283 19 ns 29 ns Drive the Energy Board Total Sum off card 10 H 124 2 ns 3 ns -------- -------- Totals 57 ns 82 ns CTFE Rev. B 2x and x Clock to the Total Et Comparators Driven off Card DELAY DELAY STEP - FUNCTION TYPICAL MAXIMUM ---------------------------------------------------- ------- ------- Receive Timing & Sync Signals F & G "2x & x" 10H125 2 ns 4 ns AND form the Total Et Latch Clock 74 AS 08 4 ns 6 ns Latch "update" clock to new data out 74 AS 821 8 ns 11 ns Comparator data bits in to P>Q out 74 LS 684 24 ns 30 ns PAL one pass through no latch PALCE22V10-25PC 25 ns 25 ns -------- -------- Totals 63 ns 76 ns GAIN MEASUREMENT vs FREQUENCY of the INPUT STAGE ---------------------------------------------------- From: MSUHEP::GROSS Steve Gross 8-JAN-1991 15:01:06.41 Subj: The gain of the CTFE op-amp circuit is ... The following numbers are from measurements taken on 8-JAN-1991, and clearly demonstrate the fact that the gain of the op-amp at the input of the CTFE is not 2.00, but approximately 1.71. These numbers are similar to those obtained during inital testing of CTFE cards in the summer of 1989, which can be found in Dan's CTFE notebook. CTFE CHANNEL: EM 1 TERM/ATTEN: ETA 1 MEASURED CENTER FREQUENCY 1.15 MHz DESIRED TOTAL GAIN AT CENTER FREQUENCY: 1.000 DESIRED OP-AMP GAIN AT CENTER FREQUENCY: 2.000 MEASURED TOTAL GAIN AT CENTER FREQUENCY: 0.857 COMPUTED OP-AMP GAIN AT CENTER FREQUENCY: 1.714 MEASURED GAIN/DESIRED GAIN AT CENTER FREQUENCY: 0.857 TOTAL OP-AMP FREQUENCY INPUT TEST MEASURED MEASURED (MHz) VOLTAGE POINT GAIN GAIN --------- ------- ----- ---- ------ 0.50 0.88 0.63 0.716 1.432 0.75 0.88 0.70 0.796 1.592 0.88 0.86 0.72 0.837 1.674 1.00 0.85 0.72 0.847 1.694 1.15 0.84 0.72 0.857 1.714 1.32 0.83 0.71 0.855 1.710 1.42 0.83 0.70 0.843 1.686 1.50 0.83 0.68 0.819 1.638 2.00 0.79 0.62 0.785 1.597 -------------------------------------------------------------------------- CTFE CHANNEL: HD 3 TERM/ATTEN: ETA 1 MEASURED CENTER FREQUENCY 1.00 MHz DESIRED TOTAL GAIN AT CENTER FREQUENCY: 1.000 DESIRED OP-AMP GAIN AT CENTER FREQUENCY: 2.000 MEASURED TOTAL GAIN AT CENTER FREQUENCY: 0.859 COMPUTED OP-AMP GAIN AT CENTER FREQUENCY: 1.718 MEASURED GAIN/DESIRED GAIN AT CENTER FREQUENCY: 0.859 TOTAL OP-AMP FREQUENCY INPUT TEST MEASURED MEASURED (MHz) VOLTAGE POINT GAIN GAIN --------- ------- ----- ---- ------ 0.85 0.86 0.72 0.837 1.674 1.00 0.85 0.73 0.859 1.718 1.15 0.84 0.72 0.857 1.714 1.30 0.84 0.71 0.845 1.690 1.45 0.83 0.70 0.843 1.686 -------------------------------------------------------------------------- CTFE CHANNEL: EM 1 TERM/ATTEN: ETA 4 MEASURED CENTER FREQUENCY 1.15 MHz DESIRED TOTAL GAIN AT CENTER FREQUENCY: 0.796 DESIRED OP-AMP GAIN AT CENTER FREQUENCY: 2.000 MEASURED TOTAL GAIN AT CENTER FREQUENCY: 0.679 COMPUTED OP-AMP GAIN AT CENTER FREQUENCY: 1.706 MEASURED GAIN/DESIRED GAIN AT CENTER FREQUENCY: 0.853 (only one measurement taken, summarized above)