+------------------------------------------------------------------+ | | | D0 CALORIMETER TRIGGER MOTHERBOARD DRIVER CARD | | | +------------------------------------------------------------------+ Michigan State University 19-JUN-1990 Add Logic Probe Inputs: 22-JUN-1990 Functions described more fully: 17-AUG-1990 Add ECOs: 29-OCT-1990 Caveats about LEMOs: 14-NOV-1990 Power consumption: 5-JUN-1995 GENERAL DESCRIPTION ------------------- In each Calorimeter Trigger Backplane Cell, the Calorimeter Trigger Mother Board Driver card (CTMBD) receives the Control Computer Bus (CBUS) and the Timing and Synchronization Signal Bus (TSSBUS) from a Bus Buffer Board (BBB) via 2, 32-pair Twist'n'Flat cables. The CTMBD drives the Specific Mother-Board Bus to all Application Cards in the Backplane Cell. The CTMBD provides 3 main functions: i) Mapping subsets of the CBUS and TSSBUS into the Specific Mother-Board Bus ii) Driving the Specific Backplane Bus to the correct state iii) Providing a monitor for the Specific Mother-Board Bus The CTMBD also provides two additional functions, which are not necessarily used on every card: iv) Terminating the CBUS and TSSBUS v) Providing 24 ECL Logic Probe inputs All bits of each bus are differential ECL signals. The driver outputs on the Specific Backplane Bus are pulled down by 56 Ohm resistors connected to VTT ( -2.0 V ). The Data Bit driver outputs on the CBUS to the BBB are pulled down on the BBB in a similar fashion. Every pair of resistors also matches the caracteristic 110 Ohm impedance of the differential line. CREATING THE SPECIFIC MOTHER BOARD BUS The 40 differential signals composing the Specific Mother-Board Bus distributed to the cards plugged into a given backplane are : o The Card Address (6 bits from CBUS) o The Function Address (8 bits from CBUS) o The Bidirectional Data (8 bits from CBUS) o The Strobe Signal (1 bit from CBUS) o The Direction Signal (1 bit from CBUS) o Timing and Synchronization (16 bits from TSSBUS) J5 and J6 are respectively a set of 64 and 32 wire wrap pins. The 16 Timing and Synchronization Signals to be distributed on the mother-board are selected by connecting 32 wires between the pins of J5 and some of the pins of J6. On both sets of pins, the inverted signal of the differential pairs is located on the row closer to the backplane. On J5 the Timing and Synchronization Signal number 1 is located on the two pins closer to the left edge of the board. On J4 the Timing and Synchronization number H is located on the two pins closer to the left edge of the board. DRIVING THE SPECIFIC MOTHER-BOARD BUS The Mother-Board Address present on the CBUS is decoded on the CTMBD. The address of the mother-board is set on an 8 bit switch located on the CTMBD. The least significant bit (LSB) is the one closest to the backplane. An open switch (OFF) sets a bit to one, a closed switch (ON) sets a bit to zero. The CTMBD is said to be "selected" if the MBA on the CBUS is identical to the address set on the 8-pin DIP switch. This means that the Control Computer is attempting to access an Application Card in the Backplane Cell handled by that particular CTMBD. The Specific Mother-Board Bus signals are never allowed to simply "float." They are always driven by either the Mother Board Driver or the selected Application Card (in the case of Data lines during a READ operation). In this way, glitches are avoided. The signals are driven as follows: 1. When the Mother Board Driver is not selected: o Timing and Sync. Signals are transmitted o Card Address is driven to 0 by CTMBD o Function Address is driven to 0 by CTMBD o Data is driven to 0 by CTMBD o Strobe is driven low (inactive) by CTMBD o Direction is driven high (read) by CTMBD (NOTE: never choose Card Address = 0 for any Application Card) 2. When Mother Board Driver is selected and Direction is low (write) o Timing and Sync. Signals are transmitted o Card Address is transmitted o Function Address is transmitted o Data is transmitted o Strobe is transmitted o Direction is transmitted 3. When Mother Board Driver is selected and direction is high (read) o Timing and Sync. Signals are transmitted o Card Address is transmitted o Function Address transmitted o Data is RECEIVED from Application Card. CTMBD drives the Data Lines to the BBB o Strobe is transmitted (remains low) o Direction is transmitted The CTMBD drives all of these lines at all times, with the exception of the Data lines. The Data lines are not driven when the CTMBD is selected AND Direction is high (read). During this time only, the CTMBD does not drive the Data lines and instead receives data from an Application Card. Note that although there are 16 Timing and Syncronization Signals, no Application Card receives more than 8. See the description(s) of the Calorimeter Trigger Backplane(s) for the Timing Signal subsets delivered to each Application Card. MONITORING THE SPECIFIC MOTHER-BOARD BUS All signals on the Specific Mother-Board Bus can be visually monitored using LEDs along the front edge of the CTMBD. Each Timing and Synchronization Signal has differential LEDs, one indicating HIGH and one indicating LOW. In this way, the duty cycle of the TSS can be roughly assessed visually. The Strobe and Direction signals receive the same treatment. Each Card Address bit, Function Address bit, and Data Bit, as well as the WAKEUP signal, has a single LED, which lights when the signal is HIGH. Note that the LEDs are actually NOT reflecting the state of the Specific Mother-Board Bus directly (to minimize interference with the high-speed signals), but instead are driven by and buffered from the CBUS and TSSBUS receivers. Therefore, they reflect the signals provided by the BBB, not the CTMBD. The Card Address, Function Address, Data, Strobe and Strobe Inverted, Direction and Direction Inverted, and Wakeup LEDs are gated by the WAKEUP signal, to appear identical to the signals on the Specific Mother-Board Bus, while the TSS LEDs are not gated. Note that the DIRECTION LED will therefore be off when the CTMBD is not selected, while the DIRECTION line on the Specific Backplane Bus is actually high. This is not an important distinction to make for general use of the CTMBD, but is a fact to remember while troubleshooting a Backplane Cell using these LEDs. Note that the Logic Probe inputs on the card (described later) can be useful to reflect the exact state of the Specific Mother-Board Bus. Each Timing and Sync Signal also has an associated LEMO connector on the front edge of the board. This provides a way to probe the TSS while running 'at speed,' using an oscilloscope. Note that the LEMO is buffered from the high-speed TSS lines with both a 10H101 and a 56 Ohm series resistor. Therefore, the amplitude of the Timing Signal seen on the LEMO is not the same as the amplitude seen on the backplane, but is instead scaled by some factor. For maximum precision in measurements made using these LEMO connectors, the neighboring connectors should be terminated with a LEMO load terminator. This eliminates a crosstalk that exists between the connectors. TERMINATING THE CBUS AND TSSBUS Approximately 4 CTMBD cards are serviced by a single BBB, using two 64-conductor Twist'n'Flat ribbon cables (one each for the CBUS and TSSBUS). The CTMBD at the end of these cables will provide 110-Ohm parallel termination of the cable. This is accomplished by simply installing 110-Ohm DIP resistor packs as necessary, in sockets that will be in all CTMBD boards. LOGIC PROBES Additionally, the CTMBD provides 24 ECL Logic Probe inputs on J3. These drive LEDs along the front edge of the CTMBD. Each LED is lit if its corresponding Logic Probe input is at an ECL 1 state, and is unlit if the Logic Probe input is either at an ECL 0 state, or is unconnected. J1 : CALORIMETER TRIGGER MOTHERBOARD BACKPLANE DRIVER 96 PIN CONNECTOR ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -5.2 V VEE 14 Power -5.2 V VEE 15 Power -5.2 V VEE 16 Power -5.2 V VEE 17 Unused 18 Power -5.2 V VEE 19 Power -5.2 V VEE 20 Power -5.2 V VEE 21 Power -5.2 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 Mother-Board Address Bit#1 Non-inverted IN NMBA1 33 Mother-Board Address Bit#1 Inverted IN IMBA1 66 Mother-Board Address Bit#2 Non-inverted IN NMBA2 34 Mother-Board Address Bit#2 Inverted IN IMBA2 67 Mother-Board Address Bit#3 Non-inverted IN IMBA2 35 Mother-Board Address Bit#3 Inverted IN IMBA3 68 Mother-Board Address Bit#4 Non-inverted IN NMBA4 36 Mother-Board Address Bit#4 Inverted IN IMBA4 69 Mother-Board Address Bit#5 Non-inverted IN NMBA5 37 Mother-Board Address Bit#5 Inverted IN IMBA5 70 Mother-Board Address Bit#6 Non-inverted IN NMBA6 38 Mother-Board Address Bit#6 Inverted IN IMBA6 71 Mother-Board Address Bit#7 Non-inverted IN NMBA7 39 Mother-Board Address Bit#7 Inverted IN IMBA7 72 Mother-Board Address Bit#8 Non-inverted IN NMBA8 40 Mother-Board Address Bit#8 Inverted IN IMBA8 73 Card Address Bit#1 Non-inverted IN NCA1 41 Card Address Bit#1 Inverted IN ICA1 74 Card Address Bit#2 Non-inverted IN NCA2 42 Card Address Bit#2 Inverted IN ICA2 75 Card Address Bit#3 Non-inverted IN NCA3 43 Card Address Bit#3 Inverted IN ICA3 76 Card Address Bit#4 Non-inverted IN NCA4 44 Card Address Bit#4 Inverted IN ICA4 77 Card Address Bit#5 Non-inverted IN NCA5 45 Card Address Bit#5 Inverted IN ICA5 78 Card Address Bit#6 Non-inverted IN NCA6 46 Card Address Bit#6 Inverted IN ICA6 79 Function Address Bit#1 Non-inverted IN NFA1 47 Function Address Bit#1 Inverted IN IFA1 80 Function Address Bit#2 Non-inverted IN NFA2 48 Function Address Bit#2 Inverted IN IFA2 81 Function Address Bit#3 Non-inverted IN NFA3 49 Function Address Bit#3 Inverted IN IFA3 82 Function Address Bit#4 Non-inverted IN NFA4 50 Function Address Bit#4 Inverted IN IFA4 83 Function Address Bit#5 Non-inverted IN NFA5 51 Function Address Bit#5 Inverted IN IFA5 84 Function Address Bit#6 Non-inverted IN NFA6 52 Function Address Bit#6 Inverted IN IFA6 85 Function Address Bit#7 Non-inverted IN NFA7 53 Function Address Bit#7 Inverted IN IFA7 86 Function Address Bit#8 Non-inverted IN NFA8 54 Function Address Bit#8 Inverted IN IFA8 87 Strobe Non-inverted IN NSTB 55 Strobe Inverted IN ISTB 88 Direction Non-inverted IN NDIR 56 Direction Inverted IN IDIR 89 Bidirectional Data Bit#1 Non-inverted I/O NDB1 57 Bidirectional Data Bit#1 Inverted I/O IDB1 90 Bidirectional Data Bit#2 Non-inverted I/O NDB2 58 Bidirectional Data Bit#2 Inverted I/O IDB2 91 Bidirectional Data Bit#3 Non-inverted I/O NDB3 59 Bidirectional Data Bit#3 Inverted I/O IDB3 92 Bidirectional Data Bit#4 Non-inverted I/O NDB4 60 Bidirectional Data Bit#4 Inverted I/O IDB4 93 Bidirectional Data Bit#5 Non-inverted I/O NDB5 61 Bidirectional Data Bit#5 Inverted I/O IDB5 94 Bidirectional Data Bit#6 Non-inverted I/O NDB6 62 Bidirectional Data Bit#6 Inverted I/O IDB6 95 Bidirectional Data Bit#7 Non-inverted I/O NDB7 63 Bidirectional Data Bit#7 Inverted I/O IDB7 96 Bidirectional Data Bit#8 Non-inverted I/O NDB8 64 Bidirectional Data Bit#8 Inverted I/O IDB8 ----------------------------------------------------------------------------- J2 : CALORIMETER TRIGGER MOTHERBOARD BACKPLANE DRIVER 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Ground GND 14 Ground GND 15 Ground GND 16 Ground GND 17 Unused 18 Ground GND 19 Ground GND 20 Ground GND 21 Ground GND 22 Unused 23 Power +5.0 V NOT CONNECTED VCC 24 Power +5.0 V NOT CONNECTED VCC 25 Power +5.0 V NOT CONNECTED VCC 26 Power +5.0 V NOT CONNECTED VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 Timing & Sync. Signal Bit#1 Non-inverted IN NTSS1 33 Timing & Sync. Signal Bit#1 Inverted IN ITSS1 66 Timing & Sync. Signal Bit#2 Non-inverted IN NTSS2 34 Timing & Sync. Signal Bit#2 Inverted IN ITSS2 67 Timing & Sync. Signal Bit#3 Non-inverted IN NTSS3 35 Timing & Sync. Signal Bit#3 Inverted IN ITSS3 68 Timing & Sync. Signal Bit#4 Non-inverted IN NTSS4 36 Timing & Sync. Signal Bit#4 Inverted IN ITSS4 69 Timing & Sync. Signal Bit#5 Non-inverted IN NTSS5 37 Timing & Sync. Signal Bit#5 Inverted IN ITSS5 70 Timing & Sync. Signal Bit#6 Non-inverted IN NTSS6 38 Timing & Sync. Signal Bit#6 Inverted IN ITSS6 71 Timing & Sync. Signal Bit#7 Non-inverted IN NTSS7 39 Timing & Sync. Signal Bit#7 Inverted IN ITSS7 72 Timing & Sync. Signal Bit#8 Non-inverted IN NTSS8 40 Timing & Sync. Signal Bit#8 Inverted IN ITSS8 73 Timing & Sync. Signal Bit#9 Non-inverted IN NTSS9 41 Timing & Sync. Signal Bit#9 Inverted IN ITSS9 74 Timing & Sync. Signal Bit#10 Non-inverted IN NTSS10 42 Timing & Sync. Signal Bit#10 Inverted IN ITSS10 75 Timing & Sync. Signal Bit#11 Non-inverted IN NTSS11 43 Timing & Sync. Signal Bit#11 Inverted IN ITSS11 76 Timing & Sync. Signal Bit#12 Non-inverted IN NTSS12 44 Timing & Sync. Signal Bit#12 Inverted IN ITSS12 77 Timing & Sync. Signal Bit#13 Non-inverted IN NTSS13 45 Timing & Sync. Signal Bit#13 Inverted IN ITSS13 78 Timing & Sync. Signal Bit#14 Non-inverted IN NTSS14 46 Timing & Sync. Signal Bit#14 Inverted IN ITSS14 79 Timing & Sync. Signal Bit#15 Non-inverted IN NTSS15 47 Timing & Sync. Signal Bit#15 Inverted IN ITSS15 80 Timing & Sync. Signal Bit#16 Non-inverted IN NTSS16 48 Timing & Sync. Signal Bit#16 Inverted IN ITSS16 81 Timing & Sync. Signal Bit#17 Non-inverted IN NTSS17 49 Timing & Sync. Signal Bit#17 Inverted IN ITSS17 82 Timing & Sync. Signal Bit#18 Non-inverted IN NTSS18 50 Timing & Sync. Signal Bit#18 Inverted IN ITSS18 83 Timing & Sync. Signal Bit#19 Non-inverted IN NTSS19 51 Timing & Sync. Signal Bit#19 Inverted IN ITSS19 84 Timing & Sync. Signal Bit#20 Non-inverted IN NTSS20 52 Timing & Sync. Signal Bit#20 Inverted IN ITSS20 85 Timing & Sync. Signal Bit#21 Non-inverted IN NTSS21 53 Timing & Sync. Signal Bit#21 Inverted IN ITSS21 86 Timing & Sync. Signal Bit#22 Non-inverted IN NTSS22 54 Timing & Sync. Signal Bit#22 Inverted IN ITSS22 87 Timing & Sync. Signal Bit#23 Non-inverted IN NTSS23 55 Timing & Sync. Signal Bit#23 Inverted IN ITSS23 88 Timing & Sync. Signal Bit#24 Non-inverted IN NTSS24 56 Timing & Sync. Signal Bit#24 Inverted IN ITSS24 89 Timing & Sync. Signal Bit#25 Non-inverted IN NTSS25 57 Timing & Sync. Signal Bit#25 Inverted IN ITSS25 90 Timing & Sync. Signal Bit#26 Non-inverted IN NTSS26 58 Timing & Sync. Signal Bit#26 Inverted IN ITSS26 91 Timing & Sync. Signal Bit#27 Non-inverted IN NTSS27 59 Timing & Sync. Signal Bit#27 Inverted IN ITSS27 92 Timing & Sync. Signal Bit#28 Non-inverted IN NTSS28 60 Timing & Sync. Signal Bit#28 Inverted IN ITSS28 93 Timing & Sync. Signal Bit#29 Non-inverted IN NTSS29 61 Timing & Sync. Signal Bit#29 Inverted IN ITSS29 94 Timing & Sync. Signal Bit#30 Non-inverted IN NTSS30 62 Timing & Sync. Signal Bit#30 Inverted IN ITSS30 95 Timing & Sync. Signal Bit#31 Non-inverted IN NTSS31 63 Timing & Sync. Signal Bit#31 Inverted IN ITSS31 96 Timing & Sync. Signal Bit#32 Non-inverted IN NTSS32 64 Timing & Sync. Signal Bit#32 Inverted IN ITSS32 ----------------------------------------------------------------------------- J3 : CALORIMETER TRIGGER MOTHERBOARD BACKPLANE DRIVER 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic -------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V NOT CONNECTED VCC 8 Power +5.0 V NOT CONNECTED VCC 9 Power +5.0 V NOT CONNECTED VCC 10 Power +5.0 V NOT CONNECTED VCC 11 Unused 12 Ground GND 13 Ground GND 14 Ground GND 15 Ground GND 16 Unused 17 Ground GND 18 Ground GND 19 Ground GND 20 Ground GND 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Logic Probe Bit #1 Non-inverted NLP1 65 Logic Probe Bit #1 Inverted ILP1 34 Logic Probe Bit #2 Non-inverted NLP2 66 Logic Probe Bit #2 Inverted ILP2 35 Logic Probe Bit #3 Non-inverted NLP3 67 Logic Probe Bit #3 Inverted ILP3 36 Logic Probe Bit #4 Non-inverted NLP4 68 Logic Probe Bit #4 Inverted ILP4 37 Logic Probe Bit #5 Non-inverted NLP5 69 Logic Probe Bit #5 Inverted ILP5 38 Logic Probe Bit #6 Non-inverted NLP6 70 Logic Probe Bit #6 Inverted ILP6 39 Logic Probe Bit #7 Non-inverted NLP7 71 Logic Probe Bit #7 Inverted ILP7 40 Logic Probe Bit #8 Non-inverted NLP8 72 Logic Probe Bit #8 Inverted ILP8 41 Logic Probe Bit #9 Non-inverted NLP9 73 Logic Probe Bit #9 Inverted ILP9 42 Logic Probe Bit #10 Non-inverted NLP10 74 Logic Probe Bit #10 Inverted ILP10 43 Logic Probe Bit #11 Non-inverted NLP11 75 Logic Probe Bit #11 Inverted ILP11 44 Logic Probe Bit #12 Non-inverted NLP12 76 Logic Probe Bit #12 Inverted ILP12 45 Logic Probe Bit #13 Non-inverted NLP13 77 Logic Probe Bit #13 Inverted ILP13 46 Logic Probe Bit #14 Non-inverted NLP14 78 Logic Probe Bit #14 Inverted ILP14 47 Logic Probe Bit #15 Non-inverted NLP15 79 Logic Probe Bit #15 Inverted ILP15 48 Logic Probe Bit #16 Non-inverted NLP16 80 Logic Probe Bit #16 Inverted ILP16 49 Logic Probe Bit #17 Non-inverted NLP17 81 Logic Probe Bit #17 Inverted ILP17 50 Logic Probe Bit #18 Non-inverted NLP18 82 Logic Probe Bit #18 Inverted ILP18 51 Logic Probe Bit #19 Non-inverted NLP19 83 Logic Probe Bit #19 Inverted ILP19 52 Logic Probe Bit #20 Non-inverted NLP20 84 Logic Probe Bit #20 Inverted ILP20 53 Logic Probe Bit #21 Non-inverted NLP21 85 Logic Probe Bit #21 Inverted ILP21 54 Logic Probe Bit #22 Non-inverted NLP22 86 Logic Probe Bit #22 Inverted ILP22 55 Logic Probe Bit #23 Non-inverted NLP23 87 Logic Probe Bit #23 Inverted ILP23 56 Logic Probe Bit #24 Non-inverted NLP24 88 Logic Probe Bit #24 Inverted ILP24 89 TSS-J TIMING & SYNC-J Non-inverted OUT NTSSJ 57 TSS-J TIMING & SYNC-J Inverted OUT ITSSJ 90 TSS-K TIMING & SYNC-K Non-inverted OUT NTSSK 58 TSS-K TIMING & SYNC-K Inverted OUT ITSSK 91 TSS-L TIMING & SYNC-L Non-inverted OUT NTSSL 59 TSS-L TIMING & SYNC-L Inverted OUT ITSSL 92 TSS-M TIMING & SYNC-M Non-inverted OUT NTSSM 60 TSS-M TIMING & SYNC-M Inverted OUT ITSSM 93 TSS-N CAT2 TSS-G Non-inverted OUT NTSSN 61 TSS-N CAT2 TSS-G Inverted OUT ITSSN 94 TSS-P CAT2 OPERAND LATCH Non-inverted OUT NTSSP 62 TSS-P CAT2 OPERAND LATCH Inverted OUT ITSSP 95 TSS-R CHTCR INPUT CLOCK Non-inverted OUT NTSSR 63 TSS-R CHTCR INPUT CLOCK Inverted OUT ITSSR 96 TSS-S CHTCR TSS-E Non-inverted OUT NTSSS 64 TSS-S CHTCR TSS-E Inverted OUT ITSSS ---------------------------------------------------------------------------- J4 : CALORIMETER TRIGGER MOTHERBOARD BACKPLANE DRIVER 96 PIN CONNECTOR ------ ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -5.2 V VEE 13 Power -5.2 V VEE 14 Power -5.2 V VEE 15 Power -5.2 V VEE 16 Unused 17 Power -5.2 V VEE 18 Power -5.2 V VEE 19 Power -5.2 V VEE 20 Power -5.2 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 65 TSS-A SELECT WRITE A/B Non-inverted OUT NTSSA 33 TSS-A SELECT WRITE A/B Inverted OUT ITSSA 66 TSS-B LATCH/SHIFT Non-inverted OUT NTSSB 34 TSS-B LATCH/SHIFT Inverted OUT ITSSB 67 TSS-C SELECT READ A/B Non-inverted OUT NTSSC 35 TSS-C SELECT READ A/B Inverted OUT ITSSC 68 TSS-D CTFE MAP SEL. LSB Non-inverted OUT NTSSD 36 TSS-D CTFE MAP SEL. LSB Inverted OUT ITSSD 69 TSS-E CTFE MAP SEL. MSB Non-inverted OUT NTSSE 37 TSS-E CTFE MAP SEL. MSB Inverted OUT ITSSE 70 TSS-F CTFE X CLOCK Non-inverted OUT NTSSF 38 TSS-F CTFE X CLOCK Inverted OUT ITSSF 71 TSS-G CTFE 2X CLOCK Non-inverted OUT NTSSG 39 TSS-G CTFE 2X CLOCK Inverted OUT ITSSG 72 TSS-H CTFE ADC CLOCK Non-inverted OUT NTSSH 40 TSS-H CTFE ADC CLOCK Inverted OUT ITSSH 73 Card Address Bit#1 Non-inverted OUT NCA1 41 Card Address Bit#1 Inverted OUT ICA1 74 Card Address Bit#2 Non-inverted OUT NCA2 42 Card Address Bit#2 Inverted OUT ICA2 75 Card Address Bit#3 Non-inverted OUT NCA3 43 Card Address Bit#3 Inverted OUT ICA3 76 Card Address Bit#4 Non-inverted OUT NCA4 44 Card Address Bit#4 Inverted OUT ICA4 77 Card Address Bit#5 Non-inverted OUT NCA5 45 Card Address Bit#5 Inverted OUT ICA5 78 Card Address Bit#6 Non-inverted OUT NCA6 46 Card Address Bit#6 Inverted OUT ICA6 79 Function Address Bit#1 Non-inverted OUT NFA1 47 Function Address Bit#1 Inverted OUT IFA1 80 Function Address Bit#2 Non-inverted OUT NFA2 48 Function Address Bit#2 Inverted OUT IFA2 81 Function Address Bit#3 Non-inverted OUT NFA3 49 Function Address Bit#3 Inverted OUT IFA3 82 Function Address Bit#4 Non-inverted OUT NFA4 50 Function Address Bit#4 Inverted OUT IFA4 83 Function Address Bit#5 Non-inverted OUT NFA5 51 Function Address Bit#5 Inverted OUT IFA5 84 Function Address Bit#6 Non-inverted OUT NFA6 52 Function Address Bit#6 Inverted OUT IFA6 85 Function Address Bit#7 Non-inverted OUT NFA7 53 Function Address Bit#7 Inverted OUT IFA7 86 Function Address Bit#8 Non-inverted OUT NFA8 54 Function Address Bit#8 Inverted OUT IFA8 87 Strobe Non-inverted OUT NSTB 55 Strobe Inverted OUT ISTB 88 Direction Non-inverted OUT NDIR 56 Direction Inverted OUT IDIR 89 Bidirectional Data Bit#1 Non-inverted I/O NDB1 57 Bidirectional Data Bit#1 Inverted I/O IDB1 90 Bidirectional Data Bit#2 Non-inverted I/O NDB2 58 Bidirectional Data Bit#2 Inverted I/O IDB2 91 Bidirectional Data Bit#3 Non-inverted I/O NDB3 59 Bidirectional Data Bit#3 Inverted I/O IDB3 92 Bidirectional Data Bit#4 Non-inverted I/O NDB4 60 Bidirectional Data Bit#4 Inverted I/O IDB4 93 Bidirectional Data Bit#5 Non-inverted I/O NDB5 61 Bidirectional Data Bit#5 Inverted I/O IDB5 94 Bidirectional Data Bit#6 Non-inverted I/O NDB6 62 Bidirectional Data Bit#6 Inverted I/O IDB6 95 Bidirectional Data Bit#7 Non-inverted I/O NDB7 63 Bidirectional Data Bit#7 Inverted I/O IDB7 96 Bidirectional Data Bit#8 Non-inverted I/O NDB8 64 Bidirectional Data Bit#8 Inverted I/O IDB8 ----------------------------------------------------------------------------- POWER REQUIREMENTS: The DBSC uses VEE (-5.2V) , VTT (-2.0V)and GROUND power supply connections. The calculated power consumption is: VEE: maximum ------- 10KH chips: 2.2 A VEE pulldown 1.9 A LED's 0.3 A ------- 4.4 A VTT: maximum ------- VTT pulldown 0.8 A ------ 0.8 A ECO for Revision A: 1. The silkscreened information in the left front corner of the circuit board is incorrect for the following signals: STB, INV, WRT, RD, CA1-CA8, FA1-FA8, DB1-DB8. For STB, INV, WRT, RD, the LED's display the wrong polarity (e.g. WRT is lit when the direction line is HIGH for read, STB is lit when the strobe line is low). The CA, FA, DB lines all are swapped MSB for LSB, that is, the MSB is displayed on the left, but the silkscreen indicates that the MSB is on the right. FIX: Make a paper plot correction, glue onto the circuit board. 2. The silkscreened information in the left rear corner of the circuit board is incorrect: What the silkscreen claims are Timing Signals A-H are, in fact, the Mother Board Address. FIX: Make a paper plot correction, glue onto the circuit board. 3. The 3 10H101's in the Bidirectional Data Bit Transceiver section of the card (U8, U13, U20) all oscillate, even if all of their inputs are disconnected, and the outputs are only connected to 470-ohm pulldown resistors. FIX: Two-part fix: socket U8, U13, U20, R5, R7, and R12. Use 2.2-kOhm resistors in place of the 470-Ohm resistors R5, R7, R12. Use 10101's instead of 10H101's for U8, U13, U20.