________________________________________________________________ | | | | | CALORIMETER TRIGGER TIER 2 BACKPLANE | | | |______________________________________________________________| 20-MAR-1990 Split Counter Tree Timing Signals, Reorder cards in bp 21-MAR-1990 Add Tapegen documentation 27-MAR-1990 Remove old CTBP Rev. B info. 2-APR-1990 Convert from 7-layer to 8-layer 3-APR-1990 Group Counter Tree cards by eta, not by Ref Set 29-AUG-1990 Add power supply requirements 22-FEB-1991 Add Terminator Resistor Locations 21-MAY-1991 Fix Card Addressing 21-JUN-1991 I. FUNCTIONAL OVERVIEW OF THE CAL TRIGGER TIER 2 BACKPLANE One Calorimeter Trigger Second Tier Crate is involved in the following functions: o 8 Counter Trees: EM Et Reference Sets 1-4, and Total Et Reference Sets 1-4 o 2 Energy Adder Trees: EM and Hadronic o 2 Momentum Adder Trees: Px and Py There are three Second Tier Crates in the Calorimeter Trigger. Each performs the summing of each Tree across one Second Tier Eta Range (A Second Tier Eta Range is one of the three following eta magnitude ranges: 1 <= |eta| <= 8, 9 <= |eta| <= 16, 17 <= |eta| <= 24) Each Second Tier Eta Range is broken into two half-Ranges: the upper half (the four larger eta magnitudes in each Range) and the lower half (the four smaller eta magnitudes). See D0 Note 706 for a comprehensive description of the Calorimeter Trigger. One Calorimeter Trigger Second Tier Crate (Tier 2 Cell) consists of 24 Calorimeter Adder Tree Type 2 (CAT2) Cards and a Calorimeter Trigger Motherboard Driver Board (CTMBD), for a grand total of 25 Application Cards. Sixteen (16) of the CAT2's are used in 8 Counter Trees--4 Total Et Reference Sets, and 4 EM Et Reference Sets. Each Reference Set requires 2 CAT2's--one for the lower half of each Second Tier Eta Range, one for the upper half . Four (4) more CAT2's are used in the EM and Hadronic Adder Trees--2 per Tree, again 1 for the lower half of the Second Tier Eta Range, 1 for the upper half-Range. The final four (4) CAT2's are used in the Px and Py Adder Trees--one each for +Px, -Px, +Py, -Py. See D0 NOTE 706 for a comprehensive description of the 4 Adder Trees and 8 Counter Trees. The two (2) open slots are wired to receive power as CAT2 cards. This is the only reasonable choice: o For expediency, the connectors must be DIN-style. o A CTFE could perform no useful function in a Second Tier Crate. o A CHTCR could perform useful functions, however, it expects TTL inputs, which are not present in the Second Tier Crate. o If we design a new card to do something in the Second Tier Crate, we can power it like a CAT2, even if it uses 10K ECL. CAT2 gets +5.0, -4.5, -2.0, and GROUND. The CAT2 cards receive CBUS from the CTMBD. Those are the only signals that are passed on the backplane. That is, (except for the CBUS) each CAT2 card acts independently on signals that arrive on ribbon cable from up to four (4) Calorimeter Trigger Front End Cells. All of the Timing & Sync Signals on the CBUS are not connected to all of the Application Cards. Although all cards (except the CTBMD) are CAT2's, there are four (4) flavors of these cards. Each flavor requires different Timing & Sync Signals. The flavors are: o EM Et Counter Tree CAT2 (EM Ref Set 1-4) o Tot Et Counter Tree CAT2 (Tot Ref Set 1-4) o Energy Adder Tree CAT2 (EM, HD) o Momentum Adder Tree CAT2 (Px, Py) More Timing & Sync Signal are needed than the CBUS was originally designed for. In addition to the original eight TIMING & SYNC Signals (A,B,C,D,E,F,G,H) on J203 of the Monter Board Driver, more T&SS signals have been added to the adjacent connector of the MOTHER BOARD DRIVER. J202 now has an additional eight TIMING & SYNC Signals (J,K,L,M,N,P,R,S). Mother Board Driver connectors J203 and J204 now carry the following Timing & Sync Signals (all pin numbers in form non-inv,inv): J3 pins 89,57 T&SS J J4 pins 65,33 T&SS A J3 pins 90,58 T&SS K J4 pins 66,34 T&SS B J3 pins 91,59 T&SS L J4 pins 67,35 T&SS C J3 pins 92,60 T&SS M J4 pins 68,36 T&SS D J3 pins 93,61 T&SS N J4 pins 69,37 T&SS E J3 pins 94,62 T&SS P J4 pins 70,38 T&SS F J3 pins 95,63 T&SS R J4 pins 71,39 T&SS G J3 pins 96,64 T&SS S J4 pins 72,40 T&SS H There is, however, one complication: it is not yet entirely decided WHICH boards will be in WHICH locations in the Tier 2 Backplane. Therefore, the decision is to split up the timing signals into small groups on the Backplane, and wire-wrap several in parallel on the CTMBD. See the "ORDER OF CARDS IN THE BACKPLANE" list for the preliminary guesses on this topic, and the choice of timing signals made. These timing signals were chosen to provide maximum flexibility without using an unreasonable number of timing signals. Advantages to this system are: o As long as all 4 Adder Tree CAT2 card pairs are kept contiguous, any pair may occupy any position. o The contiguous block of Adder Tree CAT2 card pairs may occupy either the upper 8 slots, or the lower 8 (above the 2 open) slots. o The open slots will not be blocked by cables exiting UPWARDS. o The CTBMD slot will not be blocked by cables exiting UPWARDS. o The Counter Tree CAT2's, currently grouped by ETA VALUE, could just as easily be grouped by REFERENCE SET. o Each open slot has ITS OWN timing signal. o FOUR (4) Timing Signals are left uncommitted TIMING SIGNAL USAGE BY CARD TYPE ---------------------------------- CAT2 CARD EM Et COUNTER TREE ----------*****------------- EM ENERGY CTT2BP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-H OPRAND LATCH CLOCK 72,40 J? ??,?? TSS-??? ( ) CAT2 CARD TOT Et COUNTER TREE ----------******------------- TOT ENERGY CTT2BP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-H OPRAND LATCH CLOCK 72,40 J? ??,?? TSS-??? ( ) CAT2 CARD ENERGY ADDER TREE ----------******----------- ENERGY CTT2BP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-H OPRAND LATCH CLOCK 72,40 J? ??,?? TSS-??? ( ) CAT2 CARD MOMENTUM ADDER TREE ----------********----------- MOMENTUM CTT2BP CAT2 CTMBD NET CAT2 Card Signal Name Pin No's Pin No's NAME ---------------------------- -------- ----------- ------ TSS-H OPRAND LATCH CLOCK 72,40 J? ??,?? TSS-??? ( ) CALORIMETER TRIGGER MOTHER BOARD DRIVER TIMING SIGNAL OUTPUT'S FRONT VIEW -------------------------------------------------------------------------- CTBMD J K L M N P R S A B C D E F G H T&SS # - - ----------------------------- ---------------------------- - - | | X X X X X X X X | | X X X X X X X X | | - - ----------------------------- ---------------------------- - - J3 J4 Finally, the backplane must supply the required power to each card. As this backplane is composed almost entirely of one type of card, it is a rather straightforward process understand the power and ground planes required. SUPPLY CURRENT HOW DISTRIBUTED ------ ------- --------------- VEE -5.2V app. 3A One set of wires from small PS to BB, wires to BP [only CTMBD] VEE -4.5V app. 500A Foils to backplane, plane on backplane VTT -2.0V app. 225A Foils to backplane, plane on backplane (GND) Foils to backplane, plane on backplane VCC +5.0V app. 3A One set of wires from small PS to BB, plane on backplane MAP OF THE 108 BACKPLANE CONNECTORS VIEWED FROM THE FRONT ----------------------------------------------------------- TOP OF THE CRATE TSS H = CTBMD CBUS TSS # J103 J104 J105 J106 N CAT2 +PY SUM J99 J100 J101 J102 N CAT2 -PY SUM J95 J96 J97 J98 P CAT2 +PX SUM J91 J92 J93 J94 P CAT2 -PX SUM J87 J88 J89 J90 R CAT2 HD SUM J83 J84 J85 J86 R CAT2 HD SUM J79 J80 J81 J82 S CAT2 EM SUM J75 J76 J77 J78 S CAT2 EM SUM J71 J72 J73 J74 A CAT2 TOT Et REF. SET 4 J67 J68 J69 J70 A CAT2 TOT Et REF. SET 3 J63 J64 J65 J66 A CAT2 TOT Et REF. SET 2 J59 J60 J61 J62 A CAT2 TOT Et REF. SET 1 J55 J56 J57 J58 B CAT2 TOT Et REF. SET 4 J200 J201 J202 J203 B CAT2 TOT Et REF. SET 3 J49 J50 J51 J52 B CAT2 TOT Et REF. SET 2 J45 J46 J47 J48 B CAT2 TOT Et REF. SET 1 J41 J42 J43 J44 C CAT2 EM Et REF. SET 4 J37 J38 J39 J40 C CAT2 EM Et REF. SET 3 J33 J34 J35 J36 D CAT2 EM Et REF. SET 2 J29 J30 J31 J32 D CAT2 EM Et REF. SET 1 J25 J26 J27 J28 E CAT2 EM Et REF. SET 4 J21 J22 J23 J24 E CAT2 EM Et REF. SET 3 J17 J18 J19 J20 F CAT2 EM Et REF. SET 2 J13 J14 J15 J16 F CAT2 EM Et REF. SET 1 J9 J10 J11 J12 G open J5 J6 J7 J8 H open J1 J2 J3 J4 CTBMD BOTTOM OF THE CRATE This is the view looking into the crate (i.e. the component side view of the backplane). The location of Terminator Resistors is as follows: SLOT TSS TYPE J4 Pin numbers ---- --- ---- -------------- 27 N Board (ALL) 25 P Single 72, 40 23 R Single 72, 40 21 S Single 72, 40 19 A Single 72, 40 15 B Single 72, 40 11 C Single 72, 40 9 D Single 72, 40 7 E Single 72, 40 5 F Single 72, 40 3 G Single 72, 40 2 H Single 72, 40 Note that the Terminator Board located at slot 27 terminates the CA, FA, STB, DIR, and DATA bits as well as TSS N. II. ARRANGEMENT OF BOARDS IN A CALORIMETER TRIGGER BACKPLANE The example shown is for the lowest Second Tier Eta Range. T C S C A S A L A D S R O R D BOARD JACK D T D R H TYPE NUMBER --- --- - ---------------------------------- ------- 27 58 N CAT2 +PY SUM FOR |eta| 1 to 8 103-106 TOP 26 56 N CAT2 -PY SUM FOR |eta| 1 to 8 99-102 25 54 P CAT2 +PX SUM FOR |eta| 1 to 8 95-98 24 52 P CAT2 -PX SUM FOR |eta| 1 to 8 91-94 23 48 R CAT2 HD SUM FOR |eta| 5 to 8 87-90 22 46 R CAT2 HD SUM FOR |eta| 1 to 4 83-86 21 44 S CAT2 EM SUM FOR |eta| 5 to 8 79-82 20 42 S CAT2 EM SUM FOR |eta| 1 to 4 75-78 19 38 A CAT2 TOT Et REF. SET 4 FOR |eta| 5 to 8 71-74 18 36 A CAT2 TOT Et REF. SET 3 FOR |eta| 5 to 8 67-70 17 34 A CAT2 TOT Et REF. SET 2 FOR |eta| 5 to 8 63-66 16 32 A CAT2 TOT Et REF. SET 1 FOR |eta| 5 to 8 59-62 15 28 B CAT2 TOT Et REF. SET 4 FOR |eta| 1 to 4 55-58 14 26 B CAT2 TOT Et REF. SET 3 FOR |eta| 1 to 4 200-203 13 24 B CAT2 TOT Et REF. SET 2 FOR |eta| 1 to 4 49-52 12 22 B CAT2 TOT Et REF. SET 1 FOR |eta| 1 to 4 45-48 11 18 C CAT2 EM Et REF. SET 4 FOR |eta| 5 to 8 41-44 10 16 C CAT2 EM Et REF. SET 3 FOR |eta| 5 to 8 37-40 9 14 D CAT2 EM Et REF. SET 2 FOR |eta| 5 to 8 33-36 8 12 D CAT2 EM Et REF. SET 1 FOR |eta| 5 to 8 29-32 7 8 E CAT2 EM Et REF. SET 4 FOR |eta| 1 to 4 25-28 6 6 E CAT2 EM Et REF. SET 3 FOR |eta| 1 to 4 21-24 5 4 F CAT2 EM Et REF. SET 2 FOR |eta| 1 to 4 17-20 4 2 F CAT2 EM Et REF. SET 1 FOR |eta| 1 to 4 13-16 3 G open 9-12 2 H open 5-8 1 -- CTBMD MOTHER BOARD ADDRESS = 177 1-4 BOTTOM DETAILS OF THE CTT2BP CIRCUIT BOARD REVISION: A SUMMARY OF THE IEDS LEVELS USED =================================== LEVEL USED FOR PCB LAYER -------------------------------------------------------- 2 = BLIND VIAS LEVEL 5 TO 7 9 = PINS 11 = GROUND PLANE EXTERNAL+INTERNAL (1) top, (4) 12 = VEE PLANE INTERNAL (6) 13 = VTT PLANE INTERNAL (5), (7) 14 = VCC PLANE FOR CBUS LEVEL (2), (3) 15 = GROUND PLANE FOR CBUS LEVEL (2), (3) 16 = CBUS TRACES NON-INVERTED (2) 17 = CBUS TRACES INVERTED (3) 18 = VEE PLANE EXTERNAL (8) bottom 51 = VTT PLANE EXTERNAL (8) bottom 21 = SOLDER MASK 23 = TRIM MARKS 26 = BODY OUTLINE 27 = BOARD OUTLINE 29 = TYPE DESIGNATOR 36 = SILKSCREEN COMPONENT SIDE 40 = SILKSCREEN SOLDER SIDE 41 = PIN 1 DESIGNATOR 44 = TOOL MARKS TAPE GENERATION ROUTINES --------------------------------- FILE NUMBER DESCRIPTION, PCB LAYER LEVELS ON PEN TABLE ------ ------------------------- ----------------- ------------- 1. PERIMETER TEST PHOTOPLOT 23, 27, 44 CTBP_PLT.TBL 2. PCB LAY 1+4: GND PLANE + FOIL ATTACH 9, 11, 23, 44 CTBP_PLT.TBL 3. PCB LAY 2: CBUS NINV, VCC, GND 9, 14, 15, 16, 44 CTBP_PLT.TBL 4. PCB LAY 3: CBUS INV, VCC, GND 9, 14, 15, 17, 44 CTBP_PLT.TBL 5. PCB LAY 5+7: VTT PLANE 9, 13, 44 CTBP_PLT.TBL 6. PCB LAY 6: VEE PLANE 9, 12, 44 CTBP_PLT.TBL 7. PCB LAY 8: VEE, VTTP LANES + FOIL ATTACH 9, 18, 51, 44 CTBP_PLT.TBL 8. SOLDER MASK PLOT 9, 21, 44 CTBP_MSK.TBL 9. COMPONENT SIDE SILKSCREEN PHOTOPLOT 36, 44 CTBP_PLT.TBL 10. SOLDER SIDE SILKSCREEN PHOTOPLOT 40, 44 CTBP_PLT.TBL 11. DRILL FILE NUMBER 1: VIAS TO CONNECT LAYERS 5-7 2 CTBP_DRILL_3.TBL 12. DRILL FILE NUMBER 2: CONNECTOR PIN HOLES 9 CTBP_DRILL_4.TBL 13. DRILL FILE NUMBER 3: MTG HOLES, OUTER 2 ROWS, WT=0 25 CTBP_DRILL_5.TBL 14. DRILL FILE NUMBER 4: MTG HOLES, CENTER ROW, WT=1 25 CTBP_DRILL_6.TBL TIER 2 POWER CONSUMPTION TESTING -------------------------------- Current readings were taken on the power supply lines to a half loaded tier2 backplane (12 CAT2's). The following results were obtained: CURRENT READ APPX. CURRENT VOLTAGE --------------------------------------- 119 A 121 A 4.543 V 136 A 139 A 4.543 V 99.6 A 102 A 2.035 V (The fluke clip-on current meter used was tested and exhibited readings of 2% to 3% less than actual. ) APPX. CURRENT PER BOARD VOLTAGE POWER ------------------------------------------------------ 21.7 A 4.543 V 98.4 W 8.5 A 2.035 V 17.3 W Total power consumption per CAT2 card: 115.7 W APPX. TOTAL CURRENT PER TIER 2 BACKPLANE VOLTAGE ------------------------------------------------------- 510 A 4.543 V 199 A 2.035 V Total power consumption of fully loaded Tier2 backplane: 2,776 W