***************************************** * * * PRELIMINARY CARD DESCRIPTION * * * * D0 CALORIMETER TRIGGER * * FINAL MOMENTUM LOGIC NETWORK * * * ***************************************** 16-MAR-1990 name change: 11-APR-1990 PAL/9 bit info: 7-JUN-1991 parts list: 25-JUL-1991 more implementation details: 26-JUL-1991 Overflow overrule add: 29-AUG-1991 Timing estimate: 10-JAN-1992 Assembly notes, revisions: 4-APR-1992 Assembly notes, revisions: 19-JUN-1992 GENERAL DESCRIPTION ------------------- The Final Momentum Logic Network (FMLN) performs the following function: i) Missing Momentum vs. Threshold Compare for 8 thresholds Other sections of the card provide interconnection with the rest of the system: ii) CBUS INTERFACE allows readout of the card during the Data Block Building Sequence, or data access by the control computer. One FMLN card receives the final Px and Py computed by Px and Py Adder Trees. It performs the logical task of computing: ________________ MPt = / 2 2 \/ (Px) + (Py) and performs the comparison: MPt >= Preset Threshold n (for n = 0..7) As the actual calculation of the value of MPt is expensive, we instead look up the result of the comparisons directly. Since Px and Py are 24-bit signed quantities, this seems to require a 2**48 bit address space. This is clearly impossible. However, if the constraint that MPt must be less than some reasonable value is imposed, implying that only Px and Py less than some reasonable value must be considered, the memory can be reduced to a manageable size. Finally, some form of overflow sensing must be present, to force all Threshold Comparisons HIGH if Px or Py is larger than this reasonable value. Note that no combination of Px, Py, or MPt Threshold values (as long as the MPt Theshold is less than the specified maximum allowable value, which can be guaranteed via software) will produce an incorrect threshold comparison result. INPUTS ------ This card accepts as inputs: Px: 24 bits, signed (2's complement) Py: 24 bits, signed (2's complement) The inputs are latched using 100151 latches. The rising edge of FMLN TSS-H causes the latches to update. These latches could be replaced with 100150 transparent latches to allow ripple operation. These inputs are not directly readable via CBUS. The low order 9 bits of both Px and Py (that is, a total of 18 bits) are passed to the Threshold lookup/compare system. Note that 9 bits of Px or Py covers the range -128..+127.5 GeV. Recall that a threshold is considered met if the energy equals or exceeds the threshold. 127.5 GeV is the largest Px or Py magnitude for which the lookup memory can reliably perform a threshold comparison and respond "0" to indicate that the MPt is strictly less than the threshold, which imposes an upper limit of 128 GeV for a MPt threshold. Recall that, although the maximum MPt possible with 9-bit Px and Py would be ~180 GeV (128^2 + 128^2)^0.5, if either |Px| > 127.5 or |Py| > 127.5 then the output of the lookup memory will be wrong and must be overruled by the overflow-sensing circuitry. Note that MPt is guaranteed to be greater than or equal to the magnitude of both Px and Py, so an overflow on Px or Py guarantees an overflow on MPt. This allows the overflow sensing to be done on Px and Py rather than the (unavailable in any case) MPt. The overflow sensing on Px and Py is done by determining whether Px and Py are within the range -128..+127.5 GeV. This is done by determining whether each 24-bit quantity is really a sign-extended 9-bit quantity. Recall that sign extending an 'm'-bit number to an 'n'-bit number is done by copying the 'm'th bit of the 'm'-bit number to all bits 'm+1' through 'n.' That is, all bits 'm' through 'n' should have the same value, whether 0 or 1, in an 'm'-bit number which has been sign-extended to 'n'-bits. If this condition is not met, the 'n'-bit number is not a sign-extended 'm'-bit number. See the PAL source file for the PXY_OVF PALs for more details. The logic for these PALs follows: /Px_OVF = (Px[9] * Px[10] * ... * Px[24]) + (/Px[9] * /Px[10] * ... * /Px[24]) /Py_OVF = (Py[9] * Py[10] * ... * Py[24]) + (/Py[9] * /Py[10] * ... * /Py[24]) The Overflow condition will then be: /OVF = /Px_OVF * /Py_OVF ( or, equivalently ) OVF = Px_OVF + Py_OVF OUTPUTS ------- The 8 bits of MPt => Threshold information are driven on a backplane connector using differential ECL drivers. An extra copy of these 8 bits is also made available at the backplane. These bits are also driven to LEDs on the front panel. Finally, these bits are available for CBUS Reads. Note that the FMLN is not double-buffered, therefore the First Level Trigger Data Block cannot contain information read directly from an FMLN. Therefore, the 8 bits of MPt >= Threshold information must be transmitted to an IMLRO for Data Block inclusion. The input cable containing the signed Px and Py values continues past the FMLN and terminates in an IMLRO w/terminators, to provide the Px and Py values in the First Level Trigger Data Block. Recall that the Px and Py values cannot be directly read on the FMLN. LOOK-UP MEMORY -------------- The MPt Threshold Lookup Memory is made of 256K x 1, ECL-I/O Static RAMs. One RAM is required per Threshold, therefore 8 RAMs are used to implement the 8 Thresholds on each card. The 18 Address inputs of each RAM are divided equally between Px and Py inputs, as described above. The RAM will be loaded via CBUS, however, only the DATA is provided via CBUS. The ADDRESS is provided through an on-board 18-bit counter, to simplify the CBUS Write Cycle. An 18-bit wide, 2-to-1 MUX is available to select between the on-board address generator and the Px, Py inputs. This MUX can also be used to test the MPt Threshold Lookup. The address generator can count up, count down, and reset either synchronously or asynchronously. The various modes are selected through the Board CSR. In addition to the address generator modes, the source of the clock signal to the address generator is programmable. This allows the counter to increment, decrement, or reset synchronously (depending on the selected mode) on one of several events: o at the end of WRITE RAM DATA cycle only o at the end of READ RAM DATA cycle only o at the end of either WRITE or READ RAM DATA cycle o never To speed up programming of the RAM, the 256K CBUS write cycles necessary to load the RAM can be done in a "fast" mode, in which only the STROBE and DATA lines are updated. That is, the MBA, CA, FA, and DIR lines can all be left static. To speed up reading the RAM, a "fast" read cycle can be used, in which only the DIR line is updated (MBA, CA, FA, STROBE lines all left static, DATA updated by FMLN). Note that the DATA lines must be stable before the STROBE rising edge, as the FMLN loads the RAMs on the RISING EDGE of the STROBE signal. Each RAM is individually Write-Protected, to reduce the probability of accidentally writing the RAM, and to simplify the task of updating a subset of the 8 Thresholds available on the card. This Write-Protection bits are stored in an 8-bit Write-Protect Mask Register. Overflow sensing is done as described above. The Overflow line is OR'ed with each MPt Threshold comparison output, to allow the Overflow condition to overrule the (incorrect) Lookup result, to provide a correct Threshold Comparison output (MPt >= any Threshold by definition in the event of an overflow). For each MPt Threshold comparison, an Overflow Overrule can be activated, allowing the Overflow line to be ignored. This is useful for testing the programming of the RAM Array. The logic needed to perform the Overflow Overrule is contained in the Threshold output PAL. This PAL takes as its inputs the RAM data, the Overflow Overrule data, and the Px and Py overflow data using the following logic. THR_out(n) = /OVF_ovrule(n) * (Px_ovf + py_ovf ) + RAM_data(n) However, inorder for the equation to be PAL programable it must be elongated into this form. THR_out(n) = /OVF_ovrule(n) * Px_ovf + /OVF_ovrule(n) * Py_ovf + RAM_data(n) note: (n) is Threshold 0..7 This equation ensures that the output of the FMLN card is always correct. This means that if an overflow condition has been detected then the output must be true (i.e. MPt >= Threshold). Also if the Overflow Overrule is active then the output of the FMLN card will reflect the data in the RAM. Note that the Address Generator can be used in the READ THRESHOLD RESULTS mode as well, to allow stepping through the RAM address space and reading the RAM data. This is compatible with the address generator incrementation modes described above. PROGRAMMING INFORMATION ----------------------- The FMLN has 4 writable registers, and 6 readable registers. They are as follows: FA Description Read/Write -- ----------- ---------- 0 Board CSR R/W 1 Write Protect Mask R/W 2 Overflow Overrule Mask R/W 3 Write Data to RAM W only 4 Read Threshold Out PAL R only 5 Read RAM Addr LSB R only 6 Read RAM Addr MDB R only 7 Read RAM Addr MSB R only Note that, although FA 3 appears to violate the rule that all writable registers must be readable, in some sense reading the FA 4 (Threshold Comps output PAL) provides a way to check the programming. The bits in the Board CSR (FA=0) are as follows: Bit Description --- ----------- 7 MUX Input Select: 1=Add Gen; 0=Real Px, Py 6 RAM Write Addr Increment Mode: 0=Increment; 1=Don't 5 RAM Read Addr Increment Mode: 0=Increment; 1=Don't 4 S2 to Address Generator: see table below 3 S1 to Address Generator: see table below 2 S0 to Address Generator: see table below 1 Asynch Reset to Address Generator: 1=Reset; 0=Normal 0 /CEP to Address Generator 1=disable; 0=enable The bits in the Write Protect Mask Register (FA=1) are as follows: Bit Description --- ----------- 7 Write Protect Threshold 7: 1=Write Protect 6 Write Protect Threshold 6 5 Write Protect Threshold 5 4 Write Protect Threshold 4 3 Write Protect Threshold 3 2 Write Protect Threshold 2 1 Write Protect Threshold 1 0 Write Protect Threshold 0 The bits in the Overflow Overrule Mask Register (FA=2) are as follows: Bit Description --- ----------- 7 Overflow Overrule Threshold 7: 1=Overflow Overrule 6 Overflow Overrule Threshold 6 5 Overflow Overrule Threshold 5 4 Overflow Overrule Threshold 4 3 Overflow Overrule Threshold 3 2 Overflow Overrule Threshold 2 1 Overflow Overrule Threshold 1 0 Overflow Overrule Threshold 0 The Read RAM Addr LSB (FA=5) contains these bits: Bit Description --- ----------- 5 RAM Address bit 6 4 RAM Address bit 5 3 RAM Address bit 4 2 RAM Address bit 3 1 RAM Address bit 2 0 RAM Address bit 1 The Read RAM Addr MDB (FA=6) contains these bits: Bit Description --- ----------- 5 RAM Address bit 12 4 RAM Address bit 11 3 RAM Address bit 10 2 RAM Address bit 9 1 RAM Address bit 8 0 RAM Address bit 7 The Read RAM Addr MSB (FA=7) contains these bits: Bit Description --- ----------- 5 RAM Address bit 18 4 RAM Address bit 17 3 RAM Address bit 16 2 RAM Address bit 15 1 RAM Address bit 14 0 RAM Address bit 13 NOTES ----- Breakdown of RAM address bits: RAM address bit corresponds to --------------- -------------- 1 through 9 Px bits 1 through 9 10 through 18 Py bits 1 through 9 s0-s2 Breakdown: s0 | s1 | s2 | Function -----+-----+-----+-------------- 0 | 0 | 0 | Parallel load 0 | 0 | 1 | Count Down 0 | 1 | 0 | Shift Left 0 | 1 | 1 | Count Up 1 | 0 | 0 | Complement 1 | 0 | 1 | Clear 1 | 1 | 0 | Shift Right 1 | 1 | 1 | Hold It is expected that only the 'Count Up' mode and possibly the 'Count Down' mode will be used. The CAT3 can do what's necessary to form the Px, Py sums. The -Px, -Py input cables must be POLARITY-INVERTED, then the CAT3 must have the value '3' in the Correction Register (because there are 3 -Px or -Py inputs) in addition to any other corrections that must take place. For example, if a pedestal of 128 had to be removed, the CAT3 correction register would have the value '-125' loaded in its correction register to realize the correct pedestal removal. This card is built "on top of" a Wire-Wrap Prototype Array (WPA) printed circuit board. An intelligent schematic was produced on the Intergraph, which generated the wire list. DESCRIPTION OF THE CONNECTORS ----------------------------------------- J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 MPt >= Threshold 0 Inverted OUT IO1.1 34 MPt >= Threshold 1 Inverted OUT IO1.2 35 MPt >= Threshold 2 Inverted OUT IO1.3 36 MPt >= Threshold 3 Inverted OUT IO1.4 37 MPt >= Threshold 4 Inverted OUT IO1.5 38 MPt >= Threshold 5 Inverted OUT IO1.6 39 MPt >= Threshold 6 Inverted OUT IO1.7 40 MPt >= Threshold 7 Inverted OUT IO1.8 41 UNUSED OUTPUT Inverted OUT IO1.9 42 UNUSED OUTPUT Inverted OUT IO1.10 43 UNUSED OUTPUT Inverted OUT IO1.11 44 UNUSED OUTPUT Inverted OUT IO1.12 45 UNUSED OUTPUT Inverted OUT IO1.13 46 UNUSED OUTPUT Inverted OUT IO1.14 47 UNUSED OUTPUT Inverted OUT IO1.15 48 UNUSED OUTPUT Inverted OUT IO1.16 49 MPt >= Threshold 0 Inverted OUT IO1.17 50 MPt >= Threshold 1 Inverted OUT IO1.18 51 MPt >= Threshold 2 Inverted OUT IO1.19 52 MPt >= Threshold 3 Inverted OUT IO1.20 53 MPt >= Threshold 4 Inverted OUT IO1.21 54 MPt >= Threshold 5 Inverted OUT IO1.22 55 MPt >= Threshold 6 Inverted OUT IO1.23 56 MPt >= Threshold 7 Inverted OUT IO1.24 57 UNUSED OUTPUT Inverted OUT IO1.25 58 UNUSED OUTPUT Inverted OUT IO1.26 59 UNUSED OUTPUT Inverted OUT IO1.27 60 UNUSED OUTPUT Inverted OUT IO1.28 61 UNUSED OUTPUT Inverted OUT IO1.29 62 UNUSED OUTPUT Inverted OUT IO1.30 63 UNUSED OUTPUT Inverted OUT IO1.31 64 UNUSED OUTPUT Inverted OUT IO1.32 65 MPt >= Threshold 0 Non-Inverted OUT NO1.1 66 MPt >= Threshold 1 Non-inverted OUT NO1.2 67 MPt >= Threshold 2 Non-inverted OUT NO1.3 68 MPt >= Threshold 3 Non-inverted OUT NO1.4 69 MPt >= Threshold 4 Non-inverted OUT NO1.5 70 MPt >= Threshold 5 Non-inverted OUT NO1.6 71 MPt >= Threshold 6 Non-inverted OUT NO1.7 72 MPt >= Threshold 7 Non-inverted OUT NO1.8 73 UNUSED OUTPUT Non-inverted OUT NO1.9 74 UNUSED OUTPUT Non-inverted OUT NO1.10 75 UNUSED OUTPUT Non-inverted OUT NO1.11 76 UNUSED OUTPUT Non-inverted OUT NO1.12 77 UNUSED OUTPUT Non-inverted OUT NO1.13 78 UNUSED OUTPUT Non-inverted OUT NO1.14 79 UNUSED OUTPUT Non-inverted OUT NO1.15 80 UNUSED OUTPUT Non-inverted OUT NO1.16 81 MPt >= Threshold 0 Non-Inverted OUT NO1.17 82 MPt >= Threshold 1 Non-inverted OUT NO1.18 83 MPt >= Threshold 2 Non-inverted OUT NO1.19 84 MPt >= Threshold 3 Non-inverted OUT NO1.20 85 MPt >= Threshold 4 Non-inverted OUT NO1.21 86 MPt >= Threshold 5 Non-inverted OUT NO1.22 87 MPt >= Threshold 6 Non-inverted OUT NO1.23 88 MPt >= Threshold 7 Non-inverted OUT NO1.24 89 UNUSED OUTPUT Non-inverted OUT NO1.25 90 UNUSED OUTPUT Non-inverted OUT NO1.26 91 UNUSED OUTPUT Non-inverted OUT NO1.27 92 UNUSED OUTPUT Non-inverted OUT NO1.28 93 UNUSED OUTPUT Non-inverted OUT NO1.29 94 UNUSED OUTPUT Non-inverted OUT NO1.30 95 UNUSED OUTPUT Non-inverted OUT NO1.31 96 UNUSED OUTPUT Non-inverted OUT NO1.32 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Px Input Bit 1 Inverted IN II2.1 34 Px Input Bit 2 Inverted IN II2.2 35 Px Input Bit 3 Inverted IN II2.3 36 Px Input Bit 4 Inverted IN II2.4 37 Px Input Bit 5 Inverted IN II2.5 38 Px Input Bit 6 Inverted IN II2.6 39 Px Input Bit 7 Inverted IN II2.7 40 Px Input Bit 8 Inverted IN II2.8 41 Px Input Bit 9 Inverted IN II2.9 42 Px Input Bit 10 Inverted IN II2.10 43 Px Input Bit 11 Inverted IN II2.11 44 Px Input Bit 12 Inverted IN II2.12 45 Px Input Bit 13 Inverted IN II2.13 46 Px Input Bit 14 Inverted IN II2.14 47 Px Input Bit 15 Inverted IN II2.15 48 Px Input Bit 16 Inverted IN II2.16 49 Px Input Bit 17 Inverted IN II2.17 50 Px Input Bit 18 Inverted IN II2.18 51 Px Input Bit 19 Inverted IN II2.19 52 Px Input Bit 20 Inverted IN II2.20 53 Px Input Bit 21 Inverted IN II2.21 54 Px Input Bit 22 Inverted IN II2.22 55 Px Input Bit 23 Inverted IN II2.23 56 Px Input Bit 24 Inverted IN II2.24 57 UNUSED INPUT Inverted IN II2.25 58 UNUSED INPUT Inverted IN II2.26 59 UNUSED INPUT Inverted IN II2.27 60 UNUSED INPUT Inverted IN II2.28 61 UNUSED INPUT Inverted IN II2.29 62 UNUSED INPUT Inverted IN II2.30 63 UNUSED INPUT Inverted IN II2.31 64 UNUSED INPUT Inverted IN II2.32 65 Px Input Bit 1 Non-inverted IN NI2.1 66 Px Input Bit 2 Non-inverted IN NI2.2 67 Px Input Bit 3 Non-inverted IN NI2.3 68 Px Input Bit 4 Non-inverted IN NI2.4 69 Px Input Bit 5 Non-inverted IN NI2.5 70 Px Input Bit 6 Non-inverted IN NI2.6 71 Px Input Bit 7 Non-inverted IN NI2.7 72 Px Input Bit 8 Non-inverted IN NI2.8 73 Px Input Bit 9 Non-inverted IN NI2.9 74 Px Input Bit 10 Non-inverted IN NI2.10 75 Px Input Bit 11 Non-inverted IN NI2.11 76 Px Input Bit 12 Non-inverted IN NI2.12 77 Px Input Bit 13 Non-inverted IN NI2.13 78 Px Input Bit 14 Non-inverted IN NI2.14 79 Px Input Bit 15 Non-inverted IN NI2.15 80 Px Input Bit 16 Non-inverted IN NI2.16 81 Px Input Bit 17 Non-inverted IN NI2.17 82 Px Input Bit 18 Non-inverted IN NI2.18 83 Px Input Bit 19 Non-inverted IN NI2.19 84 Px Input Bit 20 Non-inverted IN NI2.20 85 Px Input Bit 21 Non-inverted IN NI2.21 86 Px Input Bit 22 Non-inverted IN NI2.22 87 Px Input Bit 23 Non-inverted IN NI2.23 88 Px Input Bit 24 Non-inverted IN NI2.24 89 UNUSED INPUT Non-inverted IN NI2.25 90 UNUSED INPUT Non-inverted IN NI2.26 91 UNUSED INPUT Non-inverted IN NI2.27 92 UNUSED INPUT Non-inverted IN NI2.28 93 UNUSED INPUT Non-inverted IN NI2.29 94 UNUSED INPUT Non-inverted IN NI2.30 95 UNUSED INPUT Non-inverted IN NI2.31 96 UNUSED INPUT Non-inverted IN NI2.32 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Py Input Bit 1 Inverted IN II3.1 34 Py Input Bit 2 Inverted IN II3.2 35 Py Input Bit 3 Inverted IN II3.3 36 Py Input Bit 4 Inverted IN II3.4 37 Py Input Bit 5 Inverted IN II3.5 38 Py Input Bit 6 Inverted IN II3.6 39 Py Input Bit 7 Inverted IN II3.7 40 Py Input Bit 8 Inverted IN II3.8 41 Py Input Bit 9 Inverted IN II3.9 42 Py Input Bit 10 Inverted IN II3.10 43 Py Input Bit 11 Inverted IN II3.11 44 Py Input Bit 12 Inverted IN II3.12 45 Py Input Bit 13 Inverted IN II3.13 46 Py Input Bit 14 Inverted IN II3.14 47 Py Input Bit 15 Inverted IN II3.15 48 Py Input Bit 16 Inverted IN II3.16 49 Py Input Bit 17 Inverted IN II3.17 50 Py Input Bit 18 Inverted IN II3.18 51 Py Input Bit 19 Inverted IN II3.19 52 Py Input Bit 20 Inverted IN II3.20 53 Py Input Bit 21 Inverted IN II3.21 54 Py Input Bit 22 Inverted IN II3.22 55 Py Input Bit 23 Inverted IN II3.23 56 Py Input Bit 24 Inverted IN II3.24 57 UNUSED INPUT Inverted IN II3.25 58 UNUSED INPUT Inverted IN II3.26 59 UNUSED INPUT Inverted IN II3.27 60 UNUSED INPUT Inverted IN II3.28 61 UNUSED INPUT Inverted IN II3.29 62 UNUSED INPUT Inverted IN II3.30 63 UNUSED INPUT Inverted IN II3.31 64 UNUSED INPUT Inverted IN II3.32 65 Py Input Bit 1 Non-inverted IN NI3.1 66 Py Input Bit 2 Non-inverted IN NI3.2 67 Py Input Bit 3 Non-inverted IN NI3.3 68 Py Input Bit 4 Non-inverted IN NI3.4 69 Py Input Bit 5 Non-inverted IN NI3.5 70 Py Input Bit 6 Non-inverted IN NI3.6 71 Py Input Bit 7 Non-inverted IN NI3.7 72 Py Input Bit 8 Non-inverted IN NI3.8 73 Py Input Bit 9 Non-inverted IN NI3.9 74 Py Input Bit 10 Non-inverted IN NI3.10 75 Py Input Bit 11 Non-inverted IN NI3.11 76 Py Input Bit 12 Non-inverted IN NI3.12 77 Py Input Bit 13 Non-inverted IN NI3.13 78 Py Input Bit 14 Non-inverted IN NI3.14 79 Py Input Bit 15 Non-inverted IN NI3.15 80 Py Input Bit 16 Non-inverted IN NI3.16 81 Py Input Bit 17 Non-inverted IN NI3.17 82 Py Input Bit 18 Non-inverted IN NI3.18 83 Py Input Bit 19 Non-inverted IN NI3.19 84 Py Input Bit 20 Non-inverted IN NI3.20 85 Py Input Bit 21 Non-inverted IN NI3.21 86 Py Input Bit 22 Non-inverted IN NI3.22 87 Py Input Bit 23 Non-inverted IN NI3.23 88 Py Input Bit 24 Non-inverted IN NI3.24 89 UNUSED INPUT Non-inverted IN NI3.25 90 UNUSED INPUT Non-inverted IN NI3.26 91 UNUSED INPUT Non-inverted IN NI3.27 92 UNUSED INPUT Non-inverted IN NI3.28 93 UNUSED INPUT Non-inverted IN NI3.29 94 UNUSED INPUT Non-inverted IN NI3.30 95 UNUSED INPUT Non-inverted IN NI3.31 96 UNUSED INPUT Non-inverted IN NI3.32 ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 FMLN Latch Clock (TSS-H) Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 FMLN Latch Clock (TSS-H) Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 TENTATIVE PARTS LIST--FMLN: does not include caps or 68-ohm resistors --------------------------------------------------------------------- By FUNCTION FMLN WPA Function Type Qty Qty -------- ---- --- --- Rear Connectors DIN96 4 *on WPA* Input Operand Bias 110A392 6 *on WPA* 110A562 6 *on WPA* Input Operand Receivers 100114 10 *on WPA* Input Operand Latches 100151 8 Overflow Detect CY100E302 2 Threshold Exceed Mask CY100E302 2 Address Generator 100136 5 Address Generator Glue 100102 1 Real/Generated Data MUX 100155 5 Readback MUX Output 100123 3 Memory Array MBM100C50015C 8 Readback Memory Array 100123 2 Output Threshold Compares 100114 2 *on WPA* LED's 100114 2 *on WPA* LED2001 9 *on WPA* Board CSR 100151 2 Readback Board CSR 100123 2 Write Protect 100151 2 Readback Write Protect 100123 2 Write Protect Mask CY100E301 1 Overflow Overrule 100151 2 Readback Overflow Overrule 100123 2 CBUS Interface 1N914 3 *on WPA* 100101 1 *on WPA* 100114 10 *on WPA* 100123 5 *on WPA* 100166 1 *on WPA* 100170 2 *on WPA* 76PSB08 1 *on WPA* --- --- 49 62 By TYPE FMLN WPA Type Qty Qty Socket ---- --- --- ------ DIN96 4 110A392 6 110A562 6 76PSB08 1 1N914 3 LED2001 9 100101 1 100102 1 24, 0.4" 110114 24 100123 11 5 24, 0.4" 100136 5 24, 0.4" 100151 14 24, 0.4" 100155 5 24, 0.4" 100166 1 100170 2 CY100E301 1 24, 0.3" CY100E302 4 24, 0.3" MBM100C500-15C 8 24, 0.3" ---- ---- 49 62 Expected TIMING through FMLN (on WPA) ------------------------------------- The only critical path on the FMLN is: TSS H rising edge to MPt >= Tn driven off card ---------------------------------------------- MAXIMUM Receive TSS H: 100114 2 ns Latch Px, Py: 100151 3 ns Pass Px, Py through mux: 100155 2 ns Lookup Threshold compare: 100C500 17 ns Apply Overflow Mask: 100E302 4 ns Buffer Threshold compare: 100114 2 ns Drive Threshold compares: 100114 2 ns ----- 32 ns ASSEMBLY NOTES -------------- When building an FMLN on top of a WPA, there are a few important notes: 1. Install all WPA IC's in sockets. 2. Do not install WPA R9, R10, R11, R12, R21 and R22. These are pull-down resistors for TSS signals and decoded FA's. These signals are pulled down at the receiving end (on the FMLN) to minimize reflection problems. Note that R9 also serves J3 input bit 32, but this bit is not used on the FMLN. 3. Do not install WPA R70, R71, R67, R68. These signals are copied to another place (ouput bits 17-24) where they are terminated. 4. Do not install U19, U22, U37, U10. These ICs are not used by the FMLN. 5. WPA IC's U20, U21, U23, and U24 must have pins 14, 16, 19, 20, 22, and 24 bent up and soldered together. This is to allow the 100114 drivers to perform the necessary single-ended to differential translation. 6. TSS-H on the backplane must be routed to both TSS-H and TSS-G on the WPA, to minimize the load on this timing signal. Remove traces on the WPA: WPA J4 pin 71 to WPA U12 pin 16 WPA J4 pin 39 to WPA U12 pin 17 Install white wires on the WPA: WPA U12 pin 20 to WPA U12 pin 16 WPA U12 pin 21 to WPA U12 pin 17 7. All nets containing more than 2 nodes must be wired in a CHAIN, not a TREE. 8. All pull-down resistors must be at the receiving end of a signal, not the sending end. For chains, the resistor must be at the end of the chain. 9. The bi-directional data bus is somewhat exempt from the above rules, due to its bidirectional nature. It has two chains in parallel, using the horizontal troughs of the WPA. The left end of each chain is terminated using the resistor pack locations made available.