L0 to L1 Box Description -------------------------------- Rev. 1-OCT-1991 Add Center Bin Indicator Bit: 4-MAR-1992 Add Copy of Good Bit to Copy of Sym Rgn Outputs: 20-NOV-1992 This file is the description of the L0 to L1 Box. This "box" takes the raw fast L0 vertex data as input and generates the Lookup Map Select signals for the CTFE cards and the Symmetric Region information for the AND-OR network as outputs. The description starts by recalling the definition of the signals that we receive from L0 and the requirements of the Lookup Map Select signals. After this review there is a description of the internal workings of this "box". The L0 to L1 Box -------------------- 1-OCT-1991 L0 Data to L1 Lookup Memory Map Select Address and to Symmetric Region Indicator Revision 1-AUG-1991 -------------------------------------------- Symmetric 5 Bit Number from Region Level 0 Fast Vertex Indicator ------------------- PROM Lookup Memory -------------- Center M L Lookup Map Select Adrs S M ... L Bin Dec- S S Map ---------------- G S ... S Indi- imal B B Selected MSB MDB LSB N B ... B cator ------ ------- ----------- ---------------- -------------- -------- - 15 10001 \ 0 - 14 10010 | 0 - 13 10011 | 0 0 0 0 1 0 0 0 1 0 - 12 10100 | 0 - 11 10101 | -Z Outer 0 - 10 10110 / Region 0 - 9 10111 \ 0 - 8 11000 | 1 0 0 1 1 0 0 1 1 0 - 7 11001 | -Z NT-NT 0 - 6 11010 / Center Region 0 - 5 11011 \ 0 - 4 11100 | 2 0 1 0 1 0 1 1 1 0 - 3 11101 | -Z Next to 0 - 2 11110 / Center Region 0 - 1 11111 \ 0 0 00000 | 3 0 1 1 * 1 1 1 1 1 1 00001 / Center Region 0 2 00010 \ 0 3 00011 | 4 1 0 0 0 0 1 1 1 0 4 00100 | +Z Next to 0 5 00101 / Center Region 0 6 00110 \ 0 7 00111 | 5 1 0 1 0 0 0 1 1 0 8 01000 | +Z NT-NT 0 9 01001 / Center Region 0 10 01010 \ 0 11 01011 | 0 12 01100 | 6 1 1 0 0 0 0 0 1 0 13 01101 | +Z Outer 0 14 01110 | Region 0 15 01111 / 0 - 16 10000 This code is not used. * - If the vertex data equals 11111 then the SIGN bit of the symmetric region will be a '1'. - If the vertex data equals 00000 or 00001 then the SIGN bit of the symmetric region will be a '0'. Note: If the GOOD bit is false, the 1st Energy, 2nd Energy, and Momentum lookup map selects will reflect the middle of the detector(i.e. 011) and the symmetric region output will be all zeros. Notes on the Outputs from the L0 to L1 Box ---------------------------------------------- 1. The Symmetric Region Indicator is a 5 bit signal that is used as 5 Input Terms to the AND-OR Network. These 5 Input Terms allow a Specific Trigger to require events to come from any one of the Z axis regions, or from any one of the expanding sets of symmetric regions centered around Z=0, or from out side the coverage of the L0 system (i.e. L0 "GOOD" signal is low). The mapping from the L0 data to the Symmetric Region Indicator is controlled by one ECL PAL. The source file for this PAL is called SYM_LOOK.PLD When L0 reports a vertex in the center region, the Sign Bit of the Symmetric Region Indicator will be either a 0 or a 1 depending if the vertex was at positive or negative Z. If a hit anywhere in the center region is to be selected the the AND-OR Network should NOT make a test on the Symmetric Region Indicator Sign Bit. An additional 1-bit signal, the Center Bin Indicator, is asserted if the Level 0 vertex is found in bin #0 and the "GOOD" signal is high. 2. The mapping from L0 data to the First Energy Lookup Map Select Address, to the Second Energy Lookup Map Select Address, and to the Momentum Lookup Map Select Address is controlled by 3 ECL PAL's and fits the LSM specification from the fall of 1990 (see D0$LEVEL1$LSMPROG:ETA_1_THRU_8_002.LSM). At this time all three of these ECL PAL hold the same circuitry and the source file to make them is called ENG_LOOK.PLD These PAL's are programmed so that if the "Good Bit" from the L0 system is low (i.e. L0 did not find a good fast Z position) then the Energy and Momentum Map Select Address Lines select all maps at Z=0. The normal mode of operation will probably be to program the Calorimeter Trigger Master timing generator to select the L0 to L1 box as the source of the First Energy Lookup Map Address and the Momentum Lookup Map Address. The Second Energy Lookup Map Address will probably be programmed into the Cal Trigger Master Timing Generator to be either Map page 4 (i.e. Z=0) or else Map page 8 (i.e. one to one). Programming of the L0 to L1 Box ------------------------------- FA= 0 Read-Write of the Board Control Status Register This Function Address reads and writes the Board Control Status Register. CBus Bits #1...#6 are read write bits in this register and CBus bits #7 and #8 have no effect when written and always read Low. Bit #1 is used to enable the positive edge of T&S Signal H to update the L0 Data Path Latch. Setting this bit high enables this. Bit #2 is used to enable the positive edge of the strobe signal on the cable from L0 to update the L0 Data Path Latch. Setting this bit high enables this. Bit #3 is used to force clocking of the L0 Data Path Latch. Setting this bit high forces the L0 Data Path Latch clock line high. Bit #4 is used to control which input of the L0 Data Path Multiplexer is selected. Setting this bit high enables data from the L0 Test Data register to reach the L0 Data Path Latch. Setting this bit low enables data on the cable from L0 to reach the L0 Data Path Latch. Bits #5 and #6 are full read write bits but they have no assigned control functions at this time. Typical Setups of the Board Control Status Register --------------------------------------------------------- CSR Bits 6 5 4 3 2 1 L0 to L1 Box Operation ---------------- ----------------------------------- x x 0 0 1 0 Use the data and clock from the L0 cable. x x 0 0 0 1 Use data from L0 cable, use clock from T&SS. x x 1 0 0 1 Use data from Test Data Reg, use Clk from T&SS. x x 1 0 0 0 \ Use these three steps to manually force load x x 1 1 0 0 | data from the Test Data Register into the L0 x x 1 0 0 0 / Data Path Latch. Logic for the L0 Data Path Latch ------------------------------------ L0 Data Path Latch = (TSS H * TSS Select) + (STROBE * Strobe Select) + Forced Latch Select This logic will be implemented by using and gates. Four gates will be used. FA= 1 Read-Write of the L0 Test Data Register This Function Address reads and writes the L0 Test Data Register. CBus bits #1...#5 are used to simulate L0 Z Position bits LSB...MSB. And CBus bit #6 is used to simulate the L0 Position GOOD bit. These 6 bits are read-write. CBus bits #7 and #8 have no effect when written and always read low. FA= 2 Read the L0 Data coming out of the L0 Data Path Latch This Function Address reads the data that has been latched in the L0 Data Path Latch. Reading the CBus bits #1...#5 gives the L0 Z Position bits LSB...MSB and reading CBus bit # 6 gives the state of the L0 Position GOOD signal. CBus bits #7..#8 always read low. FA= 3 Read the First and Second Energy Lookup Data Reading this Function Address gives the First and the Second Energy Lookup Map Select Address. CBus bits #1...#3 read the First Energy Lookup Map Select Address LSB...MSB. CBus bits #4...#6 read the Second Energy Lookup Map Select Address LSB...MSB. CBus bits #7 and #8 always read low. FA= 4 Read the Momentum Lookup Data Reading this Function Address gives the Momentum Lookup Map Select Address. CBus bits #1...#3 read the Momentum Lookup Map Select Address LSB...MSB. CBus bits #4...#8 always read low. FA= 5 Read the Symmetric Region Lookup Data Reading this Function Address gives the 5 bits of the Symmetric Region Indicator. CBus bits #1 through #4 give the Symmetric Region Indicator LSB...MSB. CBus bit #5 is the Sign Bit for the Symmetric Region Indicator. CBus bit #6 is the Center Bin Indicator bit. Cbus bits 7...#8 always read low. Inputs: L0 Information: 5 Data bits, 1 Good/NoGood bit, Strobe. All signals on a 20 or 34 conductor flat cable. Should be able to terminate the Lines into 110 ohms or else pull out the terminators. Outputs: Energy 1st Lookup: 3 Data bits position encoded Energy 2nd Lookup: 3 Data bits position encoded Momentum Lookup: 3 Data bits position encoded Symmetric Region: 5 Data Bits position decoded These allow the selection in the AND-OR Network of either a symmetric region centered around Z=0 or else any one of the L1 Z Map regions, or else Good and No Good L0 events. Center Bin: 1 Data bit, asserted if Level 0 vertex is in bin #0. Two copies of all the above output signals need to be made. Latched Copy of Input L0 Information: 6 signals 6 pin pairs. In-Out: CBus: All CBus Data lines and one Timing&Sync line. 32 pin pairs. Description of the L0 to L1 Box Data Path --------------------------------------------- 6-AUG-1991 The signals from the L0 are received on connector J3. The differential receiver includes 110 ohm socketed terminator and default logic low spreaders. The received L0 signals are one input to a 2 input Data Path Multiplexer. The other input to the Data Path Multiplexer comes from the Test Data Register. The Data Path Multiplexer is controlled by bit #4 in the Board Control-Status Register. The output from the Data Path Multiplexer is the input to the Data Path Latch. The Data Path Latch is clocked either by the strobe signal on the L0 cable, or else by a timing signal on the T&SS Bus, or else via a bit in the Board Control-Status Register. The source of the Data Path Latch update clock is controlled by other bits in the Board Control-Status Register. The Data Path Latch can be either a "D" latch or else a "transparent" latch. If it is a "D" latch then it should update on the positive going edge. If is a "transparent" latch then it should hold when its clock signal is low and follow when its clock signal is high. The output of the Data Path Latch is feed to the input of 4 ECL PAL's. These PAL's decode the First and Second Energy Lookup Map Addresses, the Momentum Lookup Map Address, and the Symmetric Region Indicators. Each PAL received as input the 5 vertex data lines and the GOOD signal line. The output of the Data Path Latch is also directly driven off card on connector J2. The output of each of the 4 PAL's can individually be read via 3 Function Addresses on the CBus. The output of each of these PAL's is driven off card via 2 drivers. There are two outputs to provide a "spare" copy of these signals. Description of the L0 to L1 Box Connector Pin Out ----------------------------------------------------- 1-OCT-1991 Because there are many cables (each with a small number of signals) connecting to the L0 to L1 card we will use a CAT2 Paddle Board to go from the rear connectors J1, J2, and J3 on the L0 to L1 card to all of its I/O cables. Recall what a CAT2 Paddle card can do. It provides 8 connectors (34 pin) of which the low order 12 bits on each connector are close packed onto the J1, J2, and J3 connectors at the back of an application card. The pin out is the following: 34 pin connector on the CAT2 Paddle card connection to the application card -------------------- ---------------------------------- 1st connector J1 pins 33 through 44 (INV) 65 through 76 (NINV) 2nd connector J1 pins 45 through 56 (INV) 77 through 88 (NINV) 3rd connector J1 pins 57 through 64 + J2 pins 33 through 36(INV) 89 through 96 + J2 pins 65 through 68(NINV) 4th connector J2 pins 37 through 48 (INV) 69 through 80 (NINV) 5th connector J2 pins 49 through 60 (INV) 81 through 92 (NINV) 6th connector J2 pins 61 through 64 + J3 pins 33 through 40(INV) 93 through 96 + J3 pins 65 through 72(NINV) 7th connector J3 pins 41 through 52 (INV) 73 through 84 (NINV) 8th connector J3 pins 53 through 64 (INV) 85 through 96 (NINV) connector pin-out ----------------- pins 1,3,5,7,9,11,13,15,17,19,21,23 (NINV) 2,4,6,8,10,12,14,16,18,20,22,24 (INV) The following is the arrangement of the connections: 1. CAT2 Paddle board connector #1 would carry the Lookup Map Select signals. Specifically: pins 1,3,5 would be the 1st Energy Lookup Map Select (LSB...MSB); pins 7,9,11 would be the 2nd Energy Lookup Map Select (LSB...MSB); and pins 13,15,17 would be the Momentum Lookup Map Select (LSB...MSB). 2. CAT2 Paddle board connector #2 would be a second copy of the Lookup Map Select lines with pinout exactly like connector #1. 3. CAT2 Paddle board connector #3 would carry the Symmetric Region information. As defined now this is 6 bits of information. Specifically pin #1 is the LSB, pin #7 is the MSB, pin #9 is the sign bit, and pin #11 is a Center Bin Indicator bit. Note: CAT2 Paddle board connector #3 spans the application card's connectors J1 and J2 but that all of the signals that we are using on CAT2 Paddle board connector #3 (i.e. pins 1 through 6) come from the part of CAT2 Paddle board connector #3 that is connected to J1 on the L0 to L1 card. 4. CAT2 Paddle board connector #4 is a second copy of the Symmetric Region information. The pinout is the same as for CAT2 Paddle board connector #3 above, with the addition of a copy of the L0 GOOD signal as the seventh bit. Note that this uses J2 on the L0 to L1 card and thus we may use the pre-wired pull down resistors but we will need to have a 100114 driver for these signals in the wire wrap area and we may not install the 100114 in the pre-wired area for these signals. 5. CAT2 Paddle board connector #5 is a copy of the Latched L0 data (i.e. the 5 vertex data bits and the L0 GOOD signal.) The pinout can be the same as for the L0 cable which brings L0 information to this card and is defined above. Note that this uses J2 on the application card and thus we may use the pre-wired pull down resistors but we will need to have a 100114 driver for these signals in the wire wrap area and we may not install the 100114 in the pre-wired area for these signals. 5. This is the input signals from the L0 System as defined above. It will use CAT2 Paddle board connector #7 Description of the L0 to L1 Box Connector Pin Out ----------------------------------------------------- 3-OCT-1991 Z Data From Level 0 ------------------- INPUTS(Backplane) ------------------- PADDLEBOARD J3 pin #'s CONNECTOR #7 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- ------ ----- 73 41 ------- Z DATA 0 ------- 1 2 74 42 ------- Z DATA 1 ------- 3 4 75 43 ------- Z DATA 2 ------- 5 6 76 44 ------- Z DATA 3 ------- 7 8 77 45 ------- Z DATA 4 ------- 9 10 78 46 ------- GOOD ------- 11 12 79 47 ------- STROBE ------- 13 14 INPUTS(WPA) +----------+-------------+-----------------------+ | | | | | | J3 IN BIT # | WRAP64 pin #'s (J102) | | Signal | | | | | NINV | INV | NINV | INV | +----------+------+------+-------+---------------+ | | | | | | | Z DATA 0 | 9 | 9 | 17 | 18 | | Z DATA 1 | 10 | 10 | 19 | 20 | | Z DATA 2 | 11 | 11 | 21 | 22 | | Z DATA 3 | 12 | 12 | 23 | 24 | | Z DATA 4 | 13 | 13 | 25 | 26 | | GOOD | 14 | 14 | 27 | 28 | | STROBE | 15 | 15 | 29 | 30 | | | | | | | +----------+------+------+-------+---------------+ 1st, 2nd, and Momentum Lookup Map --------------------------------- OUTPUTS(Backplane) -------------------- PADDLEBOARD J1 pin #'s CONNECTOR #1 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- ------ ----- 65 33 1st Energy Lookup Map (LSB) 1 2 66 34 1st Energy Lookup Map (...) 3 4 67 35 1st Energy Lookup Map (MSB) 5 6 68 36 2nd Energy Lookup Map (LSB) 7 8 69 37 2nd Energy Lookup Map (...) 9 10 70 38 2nd Energy Lookup Map (MSB) 11 12 71 39 Momentum Lookup Map (LSB) 13 14 72 40 Momentum Lookup Map (...) 15 16 73 41 Momentum Lookup Map (MSB) 17 18 OUTPUTS(WPA) +-----------------------------+-------------+-----------------------+ | | | | | | J1 OUT BIT# | WRAP64 pin #'s (J100) | | Signal | | | | | NINV | INV | NINV | INV | +-----------------------------+------+------+-------+---------------+ | | | | | | | 1st Energy Lookup Map (LSB) | 1 | 1 | 1 | 2 | | 1st Energy Lookup Map (...) | 2 | 2 | 3 | 4 | | 1st Energy Lookup Map (MSB) | 3 | 3 | 5 | 6 | | 2nd Energy Lookup Map (LSB) | 4 | 4 | 7 | 8 | | 2nd Energy Lookup Map (...) | 5 | 5 | 9 | 10 | | 2nd Energy Lookup Map (MSB) | 6 | 6 | 11 | 12 | | Momentum Lookup Map (LSB) | 7 | 7 | 13 | 14 | | Momentum Lookup Map (...) | 8 | 8 | 15 | 16 | | Momentum Lookup Map (MSB) | 9 | 9 | 17 | 18 | | | | | | | +-----------------------------+------+------+-------+---------------+ (copy of) 1st, 2nd, and Momentum Lookup Map ------------------------------------------- OUTPUTS(Backplane) ------------------- PADDLEBOARD J1 pin #'s CONNECTOR #2 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- (Copy of) ------ ----- 77 45 1st Energy Lookup Map (LSB) 1 2 78 46 1st Energy Lookup Map (...) 3 4 79 47 1st Energy Lookup Map (MSB) 5 6 80 48 2nd Energy Lookup Map (LSB) 7 8 81 49 2nd Energy Lookup Map (...) 9 10 82 50 2nd Energy Lookup Map (MSB) 11 12 83 51 Momentum Lookup Map (LSB) 13 14 84 52 Momentum Lookup Map (...) 15 16 85 53 Momentum Lookup Map (MSB) 17 18 OUTPUTS(WPA) +-----------------------------+-------------+-----------------------+ | | | | | | J1 OUT BIT# | WRAP64 pin #'s (J100) | | Signal (Copy of) | | | | | NINV | INV | NINV | INV | +-----------------------------+------+------+-------+---------------+ | | | | | | | 1st Energy Lookup Map (LSB) | 13 | 13 | 25 | 26 | | 1st Energy Lookup Map (...) | 14 | 14 | 27 | 28 | | 1st Energy Lookup Map (MSB) | 15 | 15 | 29 | 30 | | 2nd Energy Lookup Map (LSB) | 16 | 16 | 31 | 32 | | 2nd Energy Lookup Map (...) | 17 | 17 | 33 | 34 | | 2nd Energy Lookup Map (MSB) | 18 | 18 | 35 | 36 | | Momentum Lookup Map (LSB) | 19 | 19 | 37 | 38 | | Momentum Lookup Map (...) | 20 | 20 | 39 | 40 | | Momentum Lookup Map (MSB) | 21 | 21 | 41 | 42 | | | | | | | +-----------------------------+------+------+-------+---------------+ Symmetric Region Data --------------------- OUTPUTS(Backplane) ------------------- PADDLEBOARD J1 pin #'s CONNECTOR #3 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- ------ ----- 89 57 - Symmetric Region (LSB) - 1 2 90 58 - Symmetric Region (...) - 3 4 91 59 - Symmetric Region (...) - 5 6 92 60 - Symmetric Region (MSB) - 7 8 93 61 Symmetric Region Sign bit 9 10 94 62 Center Bin Indicator bit 11 12 OUTPUTS(WPA) +---------------------------+-------------+-----------------------+ | | | | | | J1 OUT BIT# | WRAP64 pin #'s (J100) | | Signal | | | | | NINV | INV | NINV | INV | +---------------------------+------+------+-------+---------------+ | | | | | | | Symmetric Region (LSB) | 25 | 25 | 49 | 50 | | Symmetric Region (...) | 26 | 26 | 51 | 52 | | Symmetric Region (...) | 27 | 27 | 53 | 54 | | Symmetric Region (MSB) | 28 | 28 | 55 | 56 | | Symmetric Region Sign bit | 29 | 29 | 57 | 58 | | Center Bin Indicator bit | 30 | 30 | 59 | 60 | | | | | | | +---------------------------+------+------+-------+---------------+ (Copy of) Symmetric Region Data ------------------------------- OUTPUTS(Backplane) ------------------- PADDLEBOARD J2 pin #'s CONNECTOR #4 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- (Copy of) ------ ----- 69 37 - Symmetric Region (LSB) - 1 2 70 38 - Symmetric Region (...) - 3 4 71 39 - Symmetric Region (...) - 5 6 72 40 - Symmetric Region (MSB) - 7 8 73 41 Symmetric Region Sign bit 9 10 74 42 Center Bin Indicator Bit 11 12 75 43 --- Latched Good Bit --- 13 14 (not S/N 1) OUTPUTS(WPA) +---------------------------+-------------+-------------------------+ | | | | | | J2 OUT BIT# | Resistor and Pin #'s | | Signal (Copy of) | | | | | NINV | INV | NINV | Resistor # | INV | +---------------------------+------+------+------+------------+-----+ | | | | | | | | Symmetric Region (LSB) | 5 | 5 | 12 | R39 | 5 | | Symmetric Region (...) | 6 | 6 | 11 | R39 | 6 | | Symmetric Region (...) | 7 | 7 | 10 | R39 | 7 | | Symmetric Region (MSB) | 8 | 8 | 9 | R39 | 8 | | Symmetric Region Sign bit | 9 | 9 | 16 | R37 | 1 | | Center Bin Indicator bit | 10 | 10 | 15 | R37 | 2 | | Latched Good Bit | 11 | 11 | 14 | R37 | 3 | | (not on S/N 1) | | | | | | +---------------------------+------+------+------+------------+-----+ Latched Z Data -------------- OUTPUTS(Backplane) ------------------- PADDLEBOARD J2 pin #'s CONNECTOR #5 pin #'s ------------ ------------------------ NINV INV NINV INV ------ ----- (Copy of) ------ ----- 81 49 --- Latched Z Data 0 --- 1 2 82 50 --- Latched Z Data 1 --- 3 4 83 51 --- Latched Z Data 2 --- 5 6 84 52 --- Latched Z Data 3 --- 7 8 85 53 --- Latched Z Data 4 --- 9 10 86 54 --- Latched Good Bit --- 11 12 OUTPUTS(WPA) +-------------------+-------------+-------------------------+ | | | | | | J2 OUT BIT# | Resistor and Pin #'s | | Signal (Copy of) | | | | | NINV | INV | NINV | Resistor # | INV | +-------------------+------+------+------+------------+-----+ | | | | | | | | Latched Z Data 0 | 17 | 17 | 16 | R46 | 1 | | Latched Z Data 1 | 18 | 18 | 15 | R46 | 2 | | Latched Z Data 2 | 19 | 19 | 14 | R46 | 3 | | Latched Z Data 3 | 20 | 20 | 13 | R46 | 4 | | Latched Z Data 4 | 21 | 21 | 12 | R46 | 5 | | Latched Good Bit | 22 | 22 | 11 | R46 | 6 | | | | | | | | +-------------------+------+------+------+------------+-----+ Note: 1. The Wrap64 reffers to the 64 pin wire wrap posts on the WPA. The pin numbers corresponds to the actual pin numbers on the WPA. 2. The 'Resistors and Pin numbers' reffer to the 110 ohm spreader Resistors on the WPA. Since these will not be installed the wire wrap posts will be inserted in the via's where the resistor would have been. LED Displays on the L0 t0 L1 Box Card ------------------------------------------------- 1-OCT-1991 Provide LED displays showing the state of the L0 vertex data and the state of the GOOD line. Total of 6 LED's. Provide LED displays showing the Lookup Map Select address for Energy 1st lookup, Energy 2nd lookup, and Momentum lookup. Total of 9 LED's Provide LED display to show which input the Data Path Multiplexer has selected. Total of 1 LED. The WPA will provide the LED displays to show the state of the four symmetric region data bits and the symmetric region sign bit. Note that the LED's will be wired in the active high state (i.e. at this time the silkscreen on the WPA is incorrect and active low wire-wrap post is actually the active high.) LED 1 --- Symmetric Region LSB LED 2 --- Symmetric Region MLB LED 3 --- Symmetric Region MHB LED 4 --- Symmetric Region MSB LED 7 --- Symmetric Region SIGN bit LED 9 --- Center Bin Indicator bit L0 to L1 Box Parts Count 15-OCT-1991 ----------------------------------- +----+-----------------+---------+---------------+------------------------+ | Qty| Description | Type | Part Number | Reference Designators | +----+-----------------+---------+---------------+------------------------+ | 1 | ECL Quint AND/ | 100104 | F_100104_DC | U9 | | | NAND Gate | | | | | | | | | | | 7 | ECL Quint Differ| 100114 | F_100114_DC | U1,U2,U3,U17,U18,U19 | | | Differential | | | U20 | | | Line Recevier | | | | | | | | | | | 3 | ECL Hex D Flip- | 100151 | F_100151_DC | U14,U15,U16 | | | Flop | | | | | | | | | | | 2 | ECL Quad Multi- | 100155 | F_100155_DC | U4,U5 | | | plexer/Latch | | | | | | | | | | | 6 | ECL Hex Bus | 100123 | F_100123_DC | U11,U12,U13,U21,U22 | | | Driver | | | U23 | | | | | | | | 3 | COMBINATORIAL | 100E302 | CY_100E302_DC | U6,U7,U10 | | | ECL 16P4 PAL | | | | | | | | | | | 1 | COMBINATORIAL | 100E301 | CY_300E301_DC | U8 | | | ECL 16P8 PAL | | | | | | | | | | | 17 | LED, Single, 90 | LED2001 | 555-2001__- | D1,D2,D3,D4,D5,D6,D7 | | | Degree Mount | | Dialite | D8,D9,D10,D11,D12,D13 | | | | | | D14,D15,D16,D17 | | | | | | | | 37 | 68 Ohm, 6-pin, | 106A680 | 706A680 | R4,R5,R6,R7,R8 | | | SIP Resistor | | Allen Bradley | R11,R12,R13,R14 | | | (5) Pack | | | R15,R16,R17,R18,R19 | | | | | | R20,R21,R22,R23,R24 | | | | | | R25,R26,R27,R29,R30 | | | | | | R31,R32,R33,R34,R35 | | | | | | R36,R37,R38,R39,R40 | | | | | | R41,R42,R43 | | | | | | | | 1 | 110 Ohm, 16 Pin | 316B111 | 316B111 | R1 | | | DIP Resistor | | | | | | (8) Pack | | | | | | | | | | | 1 | 68 Ohm, 10-pin, | 110A680 | 710A680 | R28 | | | SIP Resistor | | Allen Bradly | | | | (9) Pack | | | | +----+-----------------+---------+---------------+------------------------+ DESCRIPTION OF THE CONNECTORS ----------------------------------------- J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 1st Energy Lookup Map (LSB) Inverted OUT IO1E.1 34 1st Energy Lookup Map (MDB) Inverted OUT IO1E.2 35 1st Energy Lookup Map (MSB) Inverted OUT IO1E.3 36 2nd Energy Lookup Map (LSB) Inverted OUT IO2E.1 37 2nd Energy Lookup Map (MDB) Inverted OUT IO2E.2 38 2nd Energy Lookup Map (MSB) Inverted OUT IO2E.3 39 Momentum Lookup Map (LSB) Inverted OUT IOM.1 40 Momentum Lookup Map (MDB) Inverted OUT IOM.2 41 Momentum Lookup Map (MSB) Inverted OUT IOM.3 42 Unused 43 Unused 44 Unused 45 copy 1st Energy Lookup Map (LSB) Inverted OUT IO1EC.1 46 copy 1st Energy Lookup Map (MDB) Inverted OUT IO1EC.2 47 copy 1st Energy Lookup Map (MSB) Inverted OUT IO1EC.3 48 copy 2nd Energy Lookup Map (LSB) Inverted OUT IO2EC.1 49 copy 2nd Energy Lookup Map (MDB) Inverted OUT IO2EC.2 50 copy 2nd Energy Lookup Map (MSB) Inverted OUT IO2EC.3 51 copy Momentum Lookup Map (LSB) Inverted OUT IOMC.1 52 copy Momentum Lookup Map (MDB) Inverted OUT IOMC.2 53 copy Momentum Lookup Map (MSB) Inverted OUT IOMC.3 54 Unused 55 Unused 56 Unused 57 Symmetric Region (LSB) Inverted OUT IOSR.1 58 Symmetric Region (MLB) Inverted OUT IOSR.2 59 Symmetric Region (MHB) Inverted OUT IOSR.3 60 Symmetric Region (MSB) Inverted OUT IOSR.4 61 Symmetric Region Sign bit Inverted OUT IOSRSB 62 Center Bin Indicator bit Inverted OUT IOBRIB 63 Unused 64 Unused 65 1st Energy Lookup Map (LSB) Non-Inverted OUT NO1E.1 66 1st Energy Lookup Map (MDB) Non-inverted OUT NO1E.2 67 1st Energy Lookup Map (MSB) Non-inverted OUT NO1E.3 68 2nd Energy Lookup Map (LSB) Non-inverted OUT NO2E.1 69 2nd Energy Lookup Map (MDB) Non-inverted OUT NO2E.2 70 2nd Energy Lookup Map (MSB) Non-inverted OUT NO2E.3 71 Momentum Lookup Map (LSB) Non-inverted OUT NOM.1 72 Momentum Lookup Map (MDB) Non-inverted OUT NOM.2 73 Momentum Lookup Map (MSB) Non-inverted OUT NOM.3 74 Unused 75 Unused 76 Unused 77 copy 1st Energy Lookup Map (LSB) Non-inverted OUT NO1EC.1 78 copy 1st Energy Lookup Map (MDB) Non-inverted OUT NO1EC.2 79 copy 1st Energy Lookup Map (MSB) Non-inverted OUT NO1EC.3 80 copy 2nd Energy Lookup Map (LSB) Non-inverted OUT NO2EC.1 81 copy 2nd Energy Lookup Map (MDB) Non-inverted OUT NO2EC.2 82 copy 2nd Energy Lookup Map (MSB) Non-inverted OUT NO2EC.3 83 copy Momentum Lookup Map (LSB) Non-inverted OUT NOMC.1 84 copy Momentum Lookup Map (MDB) Non-inverted OUT NOMC.2 85 copy Momentum lookup Map (MSB) Non-inverted OUT NOMC.3 86 Unused 87 Unused 88 Unused 89 Symmetric Region (LSB) Non-inverted OUT NOSR.1 90 Symmetric Region (MLB) Non-inverted OUT NOSR.2 91 Symmetric Region (MHB) Non-inverted OUT NOSR.3 92 Symmetric Region (MSB) Non-inverted OUT NOSR.4 93 Symmetric Region Sign Bit Non-inverted OUT NOSRSB 94 Center Bin Indicator Bit Non-inverted OUT NOCBIB 95 Unused 96 Unused ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Unused 34 Unused 35 Unused 36 Unused 37 copy Symmetric Region (LSB) Inverted OUT IOSRC.1 38 copy Symmetric Region (MLB) Inverted OUT IOSRC.2 39 copy Symmetric Region (MHB) Inverted OUT IOSRC.3 40 copy Symmetric Region (MSB) Inverted OUT IOSRC.4 41 copy Symmetric Region Sign Bit Inverted OUT IOSRSBC 42 copy Center Bin Indicator Bit Inverted OUT IOCBIBC 43 copy Latched Good Bit Inverted OUT (Not on S/N 1) 44 Unused 45 Unused 46 Unused 47 Unused 48 Unused 49 copy Latched Z Data 0 Inverted OUT IOLZC.1 50 copy Latched Z Data 1 Inverted OUT IOLZC.2 51 copy Latched Z Data 2 Inverted OUT IOLZC.3 52 copy Latched Z Data 3 Inverted OUT IOLZC.4 53 copy Latched Z Data 4 Inverted OUT IOLZC.5 54 copy Latched Good Bit Inverted OUT IOLZGBC 55 Unused 56 Unused 57 Unused 58 Unused 59 Unused 60 Unused 61 Unused 62 Unused 63 Unused 64 Unused 65 Unused 66 Unused 67 Unused 68 Unused 69 copy Symmetric Region (LSB) Non-inverted OUT NOSRC.1 70 copy Symmetric Region (MLB) Non-inverted OUT NOSRC.2 71 copy Symmetric Region (MHB) Non-inverted OUT NOSRC.3 72 copy Symmetric Region (MSB) Non-inverted OUT NOSRC.4 73 copy Symmetric Region Sign Bit Non-inverted OUT NOSRSBC 74 copy Center Bin Indicator Bit Non-inverted OUT NOCBIBC 75 copy Latched Good Bit Non-inverted OUT (Not on S/N 1) 76 Unused 77 Unused 78 Unused 79 Unused 80 Unused 81 copy Latched Z Data 0 Non-inverted OUT NOLZC.1 82 copy Latched Z Data 1 Non-inverted OUT NOLZC.2 83 copy Latched Z Data 2 Non-inverted OUT NOLZC.3 84 copy Latched Z Data 3 Non-inverted OUT NOLZC.4 85 copy Latched Z Data 4 Non-inverted OUT NOLZC.5 86 copy Latched Z Good Bit Non-inverted OUT NOLZGBC 87 Unused 88 Unused 89 Unused 90 Unused 91 Unused 92 Unused 93 Unused 94 Unused 95 Unused 96 Unused ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Unused 34 Unused 35 Unused 36 Unused 37 Unused 38 Unused 39 Unused 40 Unused 41 Z DATA 0 Inverted IN IIZD.1 42 Z DATA 1 Inverted IN IIZD.2 43 Z DATA 2 Inverted IN IIZD.3 44 Z DATA 3 Inverted IN IIZD.4 45 Z DATA 4 Inverted IN IIZD.5 46 GOOD Inverted IN IIGOOD 47 STROBE Inverted IN IISTROBE 48 Unused Unused 49 Unused 50 Unused 51 Unused 52 Unused 53 Unused 54 Unused 55 Unused 56 Unused 57 Unused 58 Unused 59 Unused 60 Unused 61 Unused 62 Unused 63 Unused 64 Unused 65 Unused 66 Unused 67 Unused 68 Unused 69 Unused 70 Unused 71 Unused 72 Unused 73 Z DATA 0 Non-inverted IN NIZD.1 74 Z DATA 1 Non-inverted IN NIZD.2 75 Z DATA 2 Non-inverted IN NIZD.3 76 Z DATA 3 Non-inverted IN NIZD.4 77 Z DATA 4 Non-inverted IN NIZD.5 78 GOOD Non-inverted IN NIGOOD 79 STROBE Non-inverted IN NISTROBE 80 Unused 81 Unused 82 Unused 83 Unused 84 Unused 85 Unused 86 Unused 87 Unused 88 Unused 89 Unused 90 Unused 91 Unused 92 Unused 93 Unused 94 Unused 95 Unused 96 Unused ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 Timing & Sync. Signal H Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 Timing & Sync. Signal H Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 ECO History: ----------- L0-to-L1 card built on WPA S/N-01 had two logic errors: U9 (100104) had pins 10 and 11 swapped in the schematic U4 (100155) had pins 2 and 3 swapped in the schematic The schematic has been re-drawn (4-MAR-1992) correctly. The wire-list and unused SIP pins list in the VAX 4000 directory TRGHARD:[L0TOL1] have also been updated. The already-printed schematics were corrected by hand. Additionally, the signal generated at U8 pin 17, labelled 'SR SPARE BIT' in the schematic and wire-list actually now (4-MAR-1992) contains the Center Bin Indicator bit. The signals labelled 'CSR SPARE BIT AH' and 'CSR SPARE BIT AL' generated at U2 pins 13 and 12 respectively now contain a differential version of the Center Bin Indicator bit. Finally, LED-9 now displays the Center Bin Indicator bit. The schematic and wire-list have not been updated to reflect this change, but the PAL description file MSUTRGROOT:[PROG_DEV.L0_TO_L1.DEV_DATA]SYM_LOOK.PLD does reflect this change, as does the board descriptive text found in TRGHARD:[L0TOL1]. The L0-to-L1 schematic also shows the signals output to the WPA on page 3 using the symbol for input pins. This does not affect the functionality of the card, and the signals are clearly labelled as outputs. Note also that on the WPA, chips U19-U24 and U27 must have pins 24, 22, 20, 19, 16, 14 shorted together (with no pull-down resistor) to allow the single-ended to differential conversion for backplane driving to occur. Additionally, do not install WPA R98 and R99 (near the LED drivers), as these signals are already terminated in another location on the L0-to-L1 box. ECO Performed on L0-L1 S/N #2: ----------------------------- A copy of the Latched Good Bit must be provided with the copy of the Symmetric Region Output bits found on J2. This copy will be on J2 pins 75 and 43 as described in the descriptive text. This ECO is not included in the Wire List, nor has the Intergraph schematic been updated to include this ECO. The plotted schematics have been (will be) updated by hand to include this ECO. The ECO is described below: Remove (do not install) part: ---------------------------- R11 Remove (do not install) wire-wrap wire: -------------------------------------- U3 pin 19 to U3 pin 20 Install wire-wrap wire: ---------------------- U3 pin 16 to U3 pin 20 U3 pin 8 to J370 (WPA R37 position) pin 3 U3 pin 8 to J370 (WPA R37 position) pin 14