---------------------------------- | | | D0 LEVEL 1 CALORIMETER TRIGGER | | LARGE TILE COLLECTION CARD | | | ---------------------------------- Michigan State University - 27-MAY-1993 GENERAL DESCRIPTION The Large Tile Collection Card (LTCC) performs the following two main functions: i) the Second/Third Tiers of the Large Tile Total Et Counter Tree ii) the Large Tile Jet Pattern collection The card also has a CBUS interface to allow CBUS readback of the Large Tile Jet Pattern. Although the same circuit board is used for both the Second and Third Tiers of the Large Tile Total Et Counter Tree, it is configured in different ways for each Tier. The operation of the LTCC in each Tier is described below: Recall that the First Tier of the Large Tile Total Et Counter Tree is composed of the First Tier Px and Py CAT2 cards. The 4 comparators on each of these 2 cards (a total of 8 comparators per Large Tile) are each programmed with a reference transverse energy value. These 8 reference transverse energy values, taken over all 40 Large Tiles, make up the 8 Large Tile Reference Sets. Each Large Tile transverse energy is compared to each of its 8 associated reference transverse energy values to produce 8 single-bit results, denoted as "Large Tile Above Reference Transverse Energy Value for Large Tile Reference Set #n". OPERATION OF THE LTCC IN THE SECOND TIER OF THE LARGE TILE COUNTER TREE At the Second Tier of the Large Tile Counter Tree, a single LTCC services 8 Large Tiles. Therefore a Tier 2 LTCC receives as input: 8 Large Tiles x 8 Large Tile Reference Set comparisons ------ 64 input signals to a T2 LTCC Each input signal corresponds to one Large Tile Reference Set comparison for one Large Tile. The input signal is set to a logic high level if the corresponding Large Tile had transverse energy above the reference transverse energy value for the associated Large Tile Reference Set. Thus the array of input signals is a mask of the Large Tiles above reference transverse energy for each Large Tile Reference Set. These signals arrive on as differential ECL on 4, 34-conductor twist-n-flat cables which mate to a CAT3 paddleboard which is attached to the backplane at the slot corresponding to the LTCC. For cabling convenience, they are grouped by Large Tiles rather than by Large Tile Reference Sets. On the T2 LTCC, they are received and converted into single-ended ECL by 100314 line receivers. They are then re-grouped by Large Tile Reference Set (rather than Large Tile) to allow the subsequent Large Tile Reference Set-based processing. They are then latched and converted into TTL by 100328 ECL-to-TTL converters. These patterns of Large Tiles with transverse energy above the reference value for each of the 8 Large Tile Reference Sets are constantly recorded in double buffered pipeline memories. The information concerning the beam crossing that induced a positive Level 1.0 Trigger Decision is read from these registers by the Data Block Builder. In addition, for each Large Tile Reference Set, a 2-bit partial count of Large Tiles with transverse energy above reference is generated, using fast 2K x 8bit PROMs (one PROM per Large Tile Reference Set). One of the "extra" address lines on each of these 8 PROMs is brought out to a front-panel connector, allowing input of one differential ECL "modifier" bit for each Large Tile Reference Set (8 "modifier" bits total). This bit may be used for example to force the PROM output to some known value (e.g. 0). As part of the termination and biasing network for the modifier bit, 2 pin wire wrap posts have been included which allow a choice between a pull down to VEE or VCC to allow a choice of biasing for the modifier bit signal. The 8 bit output from the 2K x 8bit PROMs is treated as 3 separate quantities: A) a 2-bit count of energetic Large Tiles (mentioned above) B) another identical 2-bit count of energetic Large Tiles C) a 4-bit count of energetic Large Tiles The 2-bit count is programmed to saturate at a count of 3, while the 4-bit count can perform a complete count of the number of energetic Large Tiles. That is, the PROM is programmed as follows: Outputs Output # of Large Tiles above reference A and B C -------------------------------- ------- ------ 0 0 0 1 1 1 2 2 2 3 3 3 4 3 4 5 3 5 6 3 6 7 3 7 8 3 8 All of the outputs are converted from TTL to ECL and driven off-card as differential ECL using 100324 TTL to ECL convertors. The "A" output is re-grouped by bit significance (rather than by Large Tile Reference Set) to provide input for the Tier 3 LTCC. The "B" output is grouped by Large Tile Reference Set (rather than by bit significance) and driven off-card for future upgrades and/or monitoring. The "C" output is grouped by Large Tile Reference Set and driven off-card for future upgrades. OPERATION OF THE LTCC IN THE THIRD TIER OF THE LARGE TILE COUNTER TREE At the Third Tier of the Large Tile Counter Tree, a single T3 LTCC card services 5 T2 LTCC cards. Therefore, a T3 LTCC card receives as input: 5 T2 Large Tile Collection Cards x 8 Large Tile Reference Sets x 2 bit count per Large Tile Reference Set ------ 80 input signals to a T3 LTCC Each input signal corresponds to one bit of the two-bit count of Large Tiles above reference for one Large Tile Reference Set. These signals arrive as differential ECL on 5, 32-conductor twist-n-flat cables. For cabling convenience, they are grouped by bit significance rather than by Large Tile Reference Set. On the T3 LTCC, they are received and converted into single-ended ECL by 100314 line receivers. They are then re-grouped by Large Tile Reference Set (rather than bit significance) to allow the subsequent Large Tile Reference Set-based processing. They are then latched and converted into TTL by 100328 ECL-to-TTL converters. For each Large Tile Reference Set, 3 final count threshold comparisons are applied (>=1, >=2, >=3 Large Tiles above reference). This processing is done in fast 2K x 8bit PROMs (one PROM per Large Tile Reference Set). The final count thresholds are limited to the range 1..3 due to the 2-bit bottleneck introduced in the T2 LTCC. The "extra" address line on each of these 8 PROMs is brought out to a front-panel connector, allowing input of one differential ECL "modifier" bit for each Large Tile Reference Set (8 "modifier" bits total). This bit may be used for example to force the PROM output to some known value (e.g. 0). As part of the termination and biasing network for the modifier bit, 2 pin wire wrap posts have been included which allow a choice between a pull down to VEE or VCC to allow a choice of biasing for the modifier bit signal. These 3 count thresholds for each of the 8 Large Tile Reference Sets are converted from TTL to ECL and driven off-card as differential ECL using 100324 TTL to ECL convertors. THE CONTROL COMPUTER BUS INTERFACE There are no writable registers on either a T2 or a T3 LTCC. The state of the 64 input signals of a T2 LTCC (corresponding to the comparison of Large Tile transverse energy to Large Tile Reference Set reference value) is stored for the current and last 7 beam crossings. This information is also double buffered, and can be read over the Control Computer Bus (CBUS). There are no readable registers on a T3 LTCC. The output of a T2 LTCC (count of Large Tiles above reference for each Large Tile Reference Set) cannot be read by any means. The output of a T3 LTCC (count threshold comparison of the count of Large Tiles above reference for each Large Tile Reference Set) are used as inputs to the And-Or Network and are thus readable and included in the Level 1 Trigger Data Block. LTCC REGISTER ADDRESSES AND CONTENTS ==================================== FUNCTION ADDRESS n=[0..7] BEAM CROSSING (0: oldest -0 = current 7: current) REGISTER CONTENT [***] -7 = oldest -------- ---------------- ------------- 32n + 0 Large Tile Reference Set 0, Bits 1-8 - (7-n) LSB is Comparison Bit # 1, MSB is Bit # 8 32n + 1 Large Tile Reference Set 1, Bits 1-8 - (7-n) 32n + 2 Large Tile Reference Set 2, Bits 1-8 - (7-n) 32n + 3 Large Tile Reference Set 3, Bits 1-8 - (7-n) 32n + 4 Large Tile Reference Set 4, Bits 1-8 - (7-n) 32n + 5 Large Tile Reference Set 5, Bits 1-8 - (7-n) 32n + 6 Large Tile Reference Set 6, Bits 1-8 - (7-n) 32n + 7 Large Tile Reference Set 7, Bits 1-8 - (7-n) TIMING SIGNALS The LTCC card uses only 4 Timing and Synchronization Signals. They are as follows: CBUS Timing and Sync. Signal Function ------------ -------- A Write A/B B Latch/Shift C Read A/B H Input Latch TSS-A, TSS-B, and TSS-C arrive on this card on J3 (via the CAT3 paddleboard) rather than on J4. Recall that a CTT2BP provides only TSS-H to each slot. CRITICAL TIMING PATHS There is only one critical timing path through the LTCC. It is from the falling edge of TSS-H to the stable output. Determinations of the timing delays for the individual components were made from the National Semiconductor F100k ECL Logic Data Book and Design Guide (1990 edition). The values of time delays for the individual components of the critical timing path are given for an operating temperature of 25 degrees Celsius. Function: Component Minimum Maximum ___________________ _______ _______ Input line receiver: 100314 0.6 ns 2.0 ns data in to data out Latch&ECL to TTL: 100328 3.0 ns 7.5 ns latch enable to data out Count energetic Tiles: CY7C291A 35.0 ns 35.0 ns data in to data out TTL to ECL/Drive Output: 100324 0.5 ns 2.9 ns data in to data out ________________________________________________________________ Total Critical Timing Path 39.1 ns 47.4 ns CONNECTOR ASSIGNMENTS ------------------------------------------------------------------------ NOTE: The use of input pins and output pins is somewhat different between the T2 LTCC and the T3 LTCC. The connector assignment table is in a generic format. See the following table for the actual pin usage. Input Connectors: J1, J2, J3 ----------------------------- Generic T2 T3 Notation LTCC LTCC -------- ---- ---- Bit 1 L.T. Relative Index 1 L.T. |ETA| = 1..4 (positive ETA) PHI = 1..32 (relative ETA 1..4) Least Significant Count (PHI 1..8) Bit (bit of value 1) Bit 2 L.T. Relative Index 2 L.T. |ETA| = 1..4 (positive ETA) PHI = 1..32 (relative ETA 1..4) Most Significant Count (PHI 9..16) Bit (bit of value 2) Bit 3 L.T. Relative Index 3 L.T. |ETA| = 5..8 (positive ETA) PHI = 1..32 (relative ETA 1..4) Least Significant Count (PHI 17..24) Bit (bit of value 1) Bit 4 L.T. Relative Index 4 L.T. |ETA| = 5..8 (positive ETA) PHI = 1..32 (relative ETA 1..4) Most Significant Count (PHI 25..32) Bit (bit of value 2) Bit 5 L.T. Relative Index 5 L.T. |ETA| = 9..12 (negative ETA) PHI = 1..32 (relative ETA 1..4) Least Significant Count (PHI 1..8) Bit (bit of value 1) Bit 6 L.T. Relative Index 6 L.T. |ETA| = 9..12 (negative ETA) PHI = 1..32 (relative ETA 1..4) Most Significant Count (PHI 9..16) Bit (bit of value 2) Bit 7 L.T. Relative Index 7 L.T. |ETA| = 13..16 (negative ETA) PHI = 1..32 (relative ETA 1..4) Least Significant Count (PHI 17..24) Bit (bit of value 1) Bit 8 L.T. Relative Index 8 L.T. |ETA| = 13..16 (negative ETA) PHI = 1..32 (relative ETA 1..4) Most Significant Count (PHI 25..32) Bit (bit of value 2) Bit 9 Unused L.T. |ETA| = 17..20 PHI = 1..32 Least Significant Count Bit (bit of value 1) Bit 10 Unused L.T. |ETA| = 17..20 PHI = 1..32 Most Significant Count Bit (bit of value 2) Input Connector: J5 ------------------- This connector does not use generic notation Output Connectors: J6, J7 ------------------------- Generic T2 T3 Notation LTCC LTCC -------- ---- ---- Bit 1 Count Bit of value 1 Unused (LSB) Bit 2 Count Bit of value 2 Unused (MSB) Output Connector: J8 -------------------- Generic T2 T3 Notation LTCC LTCC -------- ---- ---- Bit 1 Count Bit of value 1 >=1 Large Tile with (LSB) transverse energy above reference value Bit 2 Count Bit of value 2 >=2 Large Tiles with transverse energy above reference value Bit 3 Count Bit of value 4 >=3 Large Tiles with transverse energy above reference value Bit 4 Count Bit of value 8 Unused (MSB) J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 L.T. Ref Set 0 Bit 1 Inverted IN ILTRS0.1 34 L.T. Ref Set 1 Bit 1 Inverted IN ILTRS1.1 35 L.T. Ref Set 2 Bit 1 Inverted IN ILTRS2.1 36 L.T. Ref Set 3 Bit 1 Inverted IN ILTRS3.1 37 L.T. Ref Set 4 Bit 1 Inverted IN ILTRS4.1 38 L.T. Ref Set 5 Bit 1 Inverted IN ILTRS5.1 39 L.T. Ref Set 6 Bit 1 Inverted IN ILTRS6.1 40 L.T. Ref Set 7 Bit 1 Inverted IN ILTRS7.1 41 L.T. Ref Set 0 Bit 2 Inverted IN ILTRS0.2 42 L.T. Ref Set 1 Bit 2 Inverted IN ILTRS1.2 43 L.T. Ref Set 2 Bit 2 Inverted IN ILTRS2.2 44 L.T. Ref Set 3 Bit 2 Inverted IN ILTRS3.2 45 L.T. Ref Set 4 Bit 2 Inverted IN ILTRS4.2 46 L.T. Ref Set 5 Bit 2 Inverted IN ILTRS5.2 47 L.T. Ref Set 6 Bit 2 Inverted IN ILTRS6.2 48 L.T. Ref Set 7 Bit 2 Inverted IN ILTRS7.2 49 L.T. Ref Set 0 Bit 3 Inverted IN ILTRS0.3 50 L.T. Ref Set 1 Bit 3 Inverted IN ILTRS1.3 51 L.T. Ref Set 2 Bit 3 Inverted IN ILTRS2.3 52 L.T. Ref Set 3 Bit 3 Inverted IN ILTRS3.3 53 L.T. Ref Set 4 Bit 3 Inverted IN ILTRS4.3 54 L.T. Ref Set 5 Bit 3 Inverted IN ILTRS5.3 55 L.T. Ref Set 6 Bit 3 Inverted IN ILTRS6.3 56 L.T. Ref Set 7 Bit 3 Inverted IN ILTRS7.3 57 L.T. Ref Set 0 Bit 4 Inverted IN ILTRS0.4 58 L.T. Ref Set 1 Bit 4 Inverted IN ILTRS1.4 59 L.T. Ref Set 2 Bit 4 Inverted IN ILTRS2.4 60 L.T. Ref Set 3 Bit 4 Inverted IN ILTRS3.4 61 L.T. Ref Set 4 Bit 4 Inverted IN ILTRS4.4 62 L.T. Ref Set 5 Bit 4 Inverted IN ILTRS5.4 63 L.T. Ref Set 6 Bit 4 Inverted IN ILTRS6.4 64 L.T. Ref Set 7 Bit 4 Inverted IN ILTRS7.4 65 L.T. Ref Set 0 Bit 1 Non-inverted IN NLTRS0.1 66 L.T. Ref Set 1 Bit 1 Non-inverted IN NLTRS1.1 67 L.T. Ref Set 2 Bit 1 Non-inverted IN NLTRS2.1 68 L.T. Ref Set 3 Bit 1 Non-inverted IN NLTRS3.1 69 L.T. Ref Set 4 Bit 1 Non-inverted IN NLTRS4.1 70 L.T. Ref Set 5 Bit 1 Non-inverted IN NLTRS5.1 71 L.T. Ref Set 6 Bit 1 Non-inverted IN NLTRS6.1 72 L.T. Ref Set 7 Bit 1 Non-inverted IN NLTRS7.1 73 L.T. Ref Set 0 Bit 2 Non-inverted IN NLTRS0.2 74 L.T. Ref Set 1 Bit 2 Non-inverted IN NLTRS1.2 75 L.T. Ref Set 2 Bit 2 Non-inverted IN NLTRS2.2 76 L.T. Ref Set 3 Bit 2 Non-inverted IN NLTRS3.2 77 L.T. Ref Set 4 Bit 2 Non-inverted IN NLTRS4.2 78 L.T. Ref Set 5 Bit 2 Non-inverted IN NLTRS5.2 79 L.T. Ref Set 6 Bit 2 Non-inverted IN NLTRS6.2 80 L.T. Ref Set 7 Bit 2 Non-inverted IN NLTRS7.2 81 L.T. Ref Set 0 Bit 3 Non-inverted IN NLTRS0.3 82 L.T. Ref Set 1 Bit 3 Non-inverted IN NLTRS1.3 83 L.T. Ref Set 2 Bit 3 Non-inverted IN NLTRS2.3 84 L.T. Ref Set 3 Bit 3 Non-inverted IN NLTRS3.3 85 L.T. Ref Set 4 Bit 3 Non-inverted IN NLTRS4.3 86 L.T. Ref Set 5 Bit 3 Non-inverted IN NLTRS5.3 87 L.T. Ref Set 6 Bit 3 Non-inverted IN NLTRS6.3 88 L.T. Ref Set 7 Bit 3 Non-inverted IN NLTRS7.3 89 L.T. Ref Set 0 Bit 4 Non-inverted IN NLTRS0.4 90 L.T. Ref Set 1 Bit 4 Non-inverted IN NLTRS1.4 91 L.T. Ref Set 2 Bit 4 Non-inverted IN NLTRS2.4 92 L.T. Ref Set 3 Bit 4 Non-inverted IN NLTRS3.4 93 L.T. Ref Set 4 Bit 4 Non-inverted IN NLTRS4.4 94 L.T. Ref Set 5 Bit 4 Non-inverted IN NLTRS5.4 95 L.T. Ref Set 6 Bit 4 Non-inverted IN NLTRS6.4 96 L.T. Ref Set 7 Bit 4 Non-inverted IN NLTRS7.4 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 L.T. Ref Set 0 Bit 5 Inverted IN ILTRS0.5 34 L.T. Ref Set 1 Bit 5 Inverted IN ILTRS1.5 35 L.T. Ref Set 2 Bit 5 Inverted IN ILTRS2.5 36 L.T. Ref Set 3 Bit 5 Inverted IN ILTRS3.5 37 L.T. Ref Set 4 Bit 5 Inverted IN ILTRS4.5 38 L.T. Ref Set 5 Bit 5 Inverted IN ILTRS5.5 39 L.T. Ref Set 6 Bit 5 Inverted IN ILTRS6.5 40 L.T. Ref Set 7 Bit 5 Inverted IN ILTRS7.5 41 L.T. Ref Set 0 Bit 6 Inverted IN ILTRS0.6 42 L.T. Ref Set 1 Bit 6 Inverted IN ILTRS1.6 43 L.T. Ref Set 2 Bit 6 Inverted IN ILTRS2.6 44 L.T. Ref Set 3 Bit 6 Inverted IN ILTRS3.6 45 L.T. Ref Set 4 Bit 6 Inverted IN ILTRS4.6 46 L.T. Ref Set 5 Bit 6 Inverted IN ILTRS5.6 47 L.T. Ref Set 6 Bit 6 Inverted IN ILTRS6.6 48 L.T. Ref Set 7 Bit 6 Inverted IN ILTRS7.6 49 L.T. Ref Set 0 Bit 7 Inverted IN ILTRS0.7 50 L.T. Ref Set 1 Bit 7 Inverted IN ILTRS1.7 51 L.T. Ref Set 2 Bit 7 Inverted IN ILTRS2.7 52 L.T. Ref Set 3 Bit 7 Inverted IN ILTRS3.7 53 L.T. Ref Set 4 Bit 7 Inverted IN ILTRS4.7 54 L.T. Ref Set 5 Bit 7 Inverted IN ILTRS5.7 55 L.T. Ref Set 6 Bit 7 Inverted IN ILTRS6.7 56 L.T. Ref Set 7 Bit 7 Inverted IN ILTRS7.7 57 L.T. Ref Set 0 Bit 8 Inverted IN ILTRS0.8 58 L.T. Ref Set 1 Bit 8 Inverted IN ILTRS1.8 59 L.T. Ref Set 2 Bit 8 Inverted IN ILTRS2.8 60 L.T. Ref Set 3 Bit 8 Inverted IN ILTRS3.8 61 L.T. Ref Set 4 Bit 8 Inverted IN ILTRS4.8 62 L.T. Ref Set 5 Bit 8 Inverted IN ILTRS5.8 63 L.T. Ref Set 6 Bit 8 Inverted IN ILTRS6.8 64 L.T. Ref Set 7 Bit 8 Inverted IN ILTRS7.8 65 L.T. Ref Set 0 Bit 5 Non-inverted IN NLTRS0.5 66 L.T. Ref Set 1 Bit 5 Non-inverted IN NLTRS1.5 67 L.T. Ref Set 2 Bit 5 Non-inverted IN NLTRS2.5 68 L.T. Ref Set 3 Bit 5 Non-inverted IN NLTRS3.5 69 L.T. Ref Set 4 Bit 5 Non-inverted IN NLTRS4.5 70 L.T. Ref Set 5 Bit 5 Non-inverted IN NLTRS5.5 71 L.T. Ref Set 6 Bit 5 Non-inverted IN NLTRS6.5 72 L.T. Ref Set 7 Bit 5 Non-inverted IN NLTRS7.5 73 L.T. Ref Set 0 Bit 6 Non-inverted IN NLTRS0.6 74 L.T. Ref Set 1 Bit 6 Non-inverted IN NLTRS1.6 75 L.T. Ref Set 2 Bit 6 Non-inverted IN NLTRS2.6 76 L.T. Ref Set 3 Bit 6 Non-inverted IN NLTRS3.6 77 L.T. Ref Set 4 Bit 6 Non-inverted IN NLTRS4.6 78 L.T. Ref Set 5 Bit 6 Non-inverted IN NLTRS5.6 79 L.T. Ref Set 6 Bit 6 Non-inverted IN NLTRS6.6 80 L.T. Ref Set 7 Bit 6 Non-inverted IN NLTRS7.6 81 L.T. Ref Set 0 Bit 7 Non-inverted IN NLTRS0.7 82 L.T. Ref Set 1 Bit 7 Non-inverted IN NLTRS1.7 83 L.T. Ref Set 2 Bit 7 Non-inverted IN NLTRS2.7 84 L.T. Ref Set 3 Bit 7 Non-inverted IN NLTRS3.7 85 L.T. Ref Set 4 Bit 7 Non-inverted IN NLTRS4.7 86 L.T. Ref Set 5 Bit 7 Non-inverted IN NLTRS5.7 87 L.T. Ref Set 6 Bit 7 Non-inverted IN NLTRS6.7 88 L.T. Ref Set 7 Bit 7 Non-inverted IN NLTRS7.7 89 L.T. Ref Set 0 Bit 8 Non-inverted IN NLTRS0.8 90 L.T. Ref Set 1 Bit 8 Non-inverted IN NLTRS1.8 91 L.T. Ref Set 2 Bit 8 Non-inverted IN NLTRS2.8 92 L.T. Ref Set 3 Bit 8 Non-inverted IN NLTRS3.8 93 L.T. Ref Set 4 Bit 8 Non-inverted IN NLTRS4.8 94 L.T. Ref Set 5 Bit 8 Non-inverted IN NLTRS5.8 95 L.T. Ref Set 6 Bit 8 Non-inverted IN NLTRS6.8 96 L.T. Ref Set 7 Bit 8 Non-inverted IN NLTRS7.8 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 L.T. Ref Set 0 Bit 9 Inverted IN ILTRS0.9 34 L.T. Ref Set 1 Bit 9 Inverted IN ILTRS1.9 35 L.T. Ref Set 2 Bit 9 Inverted IN ILTRS2.9 36 L.T. Ref Set 3 Bit 9 Inverted IN ILTRS3.9 37 L.T. Ref Set 4 Bit 9 Inverted IN ILTRS4.9 38 L.T. Ref Set 5 Bit 9 Inverted IN ILTRS5.9 39 L.T. Ref Set 6 Bit 9 Inverted IN ILTRS6.9 40 L.T. Ref Set 7 Bit 9 Inverted IN ILTRS7.9 41 L.T. Ref Set 0 Bit 10 Inverted IN ILTRS0.10 42 L.T. Ref Set 1 Bit 10 Inverted IN ILTRS1.10 43 L.T. Ref Set 2 Bit 10 Inverted IN ILTRS2.10 44 L.T. Ref Set 3 Bit 10 Inverted IN ILTRS3.10 45 L.T. Ref Set 4 Bit 10 Inverted IN ILTRS4.10 46 L.T. Ref Set 5 Bit 10 Inverted IN ILTRS5.10 47 L.T. Ref Set 6 Bit 10 Inverted IN ILTRS6.10 48 L.T. Ref Set 7 Bit 10 Inverted IN ILTRS7.10 49 Unused 50 Unused 51 Unused 52 Unused 53 Unused 54 Unused 55 Unused 56 Unused 57 Unused 58 Unused 59 Unused 60 Unused 61 Unused 62 TSS A Write A/B Inverted IN ITSA 63 TSS B Latch Shift Inverted IN ITSB 64 TSS C Read A/B Inverted IN ITSC 65 L.T. Ref Set 0 Bit 9 Non-inverted IN NLTRS0.9 66 L.T. Ref Set 1 Bit 9 Non-inverted IN NLTRS1.9 67 L.T. Ref Set 2 Bit 9 Non-inverted IN NLTRS2.9 68 L.T. Ref Set 3 Bit 9 Non-inverted IN NLTRS3.9 69 L.T. Ref Set 4 Bit 9 Non-inverted IN NLTRS4.9 70 L.T. Ref Set 5 Bit 9 Non-inverted IN NLTRS5.9 71 L.T. Ref Set 6 Bit 9 Non-inverted IN NLTRS6.9 72 L.T. Ref Set 7 Bit 9 Non-inverted IN NLTRS7.9 73 L.T. Ref Set 0 Bit 10 Non-inverted IN NLTRS0.10 74 L.T. Ref Set 1 Bit 10 Non-inverted IN NLTRS1.10 75 L.T. Ref Set 2 Bit 10 Non-inverted IN NLTRS2.10 76 L.T. Ref Set 3 Bit 10 Non-inverted IN NLTRS3.10 77 L.T. Ref Set 4 Bit 10 Non-inverted IN NLTRS4.10 78 L.T. Ref Set 5 Bit 10 Non-inverted IN NLTRS5.10 79 L.T. Ref Set 6 Bit 10 Non-inverted IN NLTRS6.10 80 L.T. Ref Set 7 Bit 10 Non-inverted IN NLTRS7.10 81 Unused 82 Unused 83 Unused 84 Unused 85 Unused 86 Unused 87 Unused 88 Unused 89 Unused 90 Unused 91 Unused 92 Unused 93 Unused 94 TSS A Write A/B Non-inverted IN NTSA 95 TSS B Latch Shift Non-inverted IN NTSB 96 TSS C Read A/B Non-inverted IN NTSC ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Unused 34 Unused 35 Unused 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 TSS H Operand Latch Clk Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Unused 66 Unused 67 Unused 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 TSS H Operand Latch Clk Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8 ----------------------------------------------------------------------------- J5 : LARGE TILE MODIFIER BIT INPUT FRONT CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 L.T. Ref Set 0 Modifier Non-inverted NLTRS0.M 2 L.T. Ref Set 0 Modifier Inverted ILTRS0.M 3 L.T. Ref Set 1 Modifier Non-inverted NLTRS1.M 4 L.T. Ref Set 1 Modifier Inverted ILTRS1.M 5 L.T. Ref Set 2 Modifier Non-inverted NLTRS2.M 6 L.T. Ref Set 2 Modifier Inverted ILTRS2.M 7 L.T. Ref Set 3 Modifier Non-inverted NLTRS3.M 8 L.T. Ref Set 3 Modifier Inverted ILTRS3.M 9 L.T. Ref Set 4 Modifier Non-inverted NLTRS4.M 10 L.T. Ref Set 4 Modifier Inverted ILTRS4.M 11 L.T. Ref Set 5 Modifier Non-inverted NLTRS5.M 12 L.T. Ref Set 5 Modifier Inverted ILTRS5.M 13 L.T. Ref Set 6 Modifier Non-inverted NLTRS6.M 14 L.T. Ref Set 6 Modifier Inverted ILTRS6.M 15 L.T. Ref Set 7 Modifier Non-inverted NLTRS7.M 16 L.T. Ref Set 7 Modifier Inverted ILTRS7.M ----------------------------------------------------------------------------- J6 : LARGE TILE TOTAL ET SECOND TIER MIXED COUNT FRONT CONNECTOR (PROM OUTPUT "A") ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 L.T. Ref Set 0 Bit 1 Non-inverted NOALTRS0.1 2 L.T. Ref Set 0 Bit 1 Inverted IOALTRS0.1 3 L.T. Ref Set 1 Bit 1 Non-inverted NOALTRS1.1 4 L.T. Ref Set 1 Bit 1 Inverted IOALTRS1.1 5 L.T. Ref Set 2 Bit 1 Non-inverted NOALTRS2.1 6 L.T. Ref Set 2 Bit 1 Inverted IOALTRS2.1 7 L.T. Ref Set 3 Bit 1 Non-inverted NOALTRS3.1 8 L.T. Ref Set 3 Bit 1 Inverted IOALTRS3.1 9 L.T. Ref Set 4 Bit 1 Non-inverted NOALTRS4.1 10 L.T. Ref Set 4 Bit 1 Inverted IOALTRS4.1 11 L.T. Ref Set 5 Bit 1 Non-inverted NOALTRS5.1 12 L.T. Ref Set 5 Bit 1 Inverted IOALTRS5.1 13 L.T. Ref Set 6 Bit 1 Non-inverted NOALTRS6.1 14 L.T. Ref Set 6 Bit 1 Inverted IOALTRS6.1 15 L.T. Ref Set 7 Bit 1 Non-inverted NOALTRS7.1 16 L.T. Ref Set 7 Bit 1 Inverted IOALTRS7.1 17 L.T. Ref Set 0 Bit 2 Non-inverted NOALTRS0.2 18 L.T. Ref Set 0 Bit 2 Inverted IOALTRS0.2 19 L.T. Ref Set 1 Bit 2 Non-inverted NOALTRS1.2 20 L.T. Ref Set 1 Bit 2 Inverted IOALTRS1.2 21 L.T. Ref Set 2 Bit 2 Non-inverted NOALTRS2.2 22 L.T. Ref Set 2 Bit 2 Inverted IOALTRS2.2 23 L.T. Ref Set 3 Bit 2 Non-inverted NOALTRS3.2 24 L.T. Ref Set 3 Bit 2 Inverted IOALTRS3.2 25 L.T. Ref Set 4 Bit 2 Non-inverted NOALTRS4.2 26 L.T. Ref Set 4 Bit 2 Inverted IOALTRS4.2 27 L.T. Ref Set 5 Bit 2 Non-inverted NOALTRS5.2 28 L.T. Ref Set 5 Bit 2 Inverted IOALTRS5.2 29 L.T. Ref Set 6 Bit 2 Non-inverted NOALTRS6.2 30 L.T. Ref Set 6 Bit 2 Inverted IOALTRS6.2 31 L.T. Ref Set 7 Bit 2 Non-inverted NOALTRS7.2 32 L.T. Ref Set 7 Bit 2 Inverted IOALTRS7.2 33 Unused 34 Unused ----------------------------------------------------------------------------- J7 : LARGE TILE TOTAL ET SECOND TIER UNMIXED COUNT FRONT CONNECTOR (PROM OUTPUT "B") ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 L.T. Ref Set 0 Bit 1 Non-inverted NOBLTRS0.1 2 L.T. Ref Set 0 Bit 1 Inverted IOBLTRS0.1 3 L.T. Ref Set 0 Bit 2 Non-inverted NOBLTRS0.2 4 L.T. Ref Set 0 Bit 2 Inverted IOBLTRS0.2 5 L.T. Ref Set 1 Bit 1 Non-inverted NOBLTRS1.1 6 L.T. Ref Set 1 Bit 1 Inverted IOBLTRS1.1 7 L.T. Ref Set 1 Bit 2 Non-inverted NOBLTRS1.2 8 L.T. Ref Set 1 Bit 2 Inverted IOBLTRS1.2 9 L.T. Ref Set 2 Bit 1 Non-inverted NOBLTRS2.1 10 L.T. Ref Set 2 Bit 1 Inverted IOBLTRS2.1 11 L.T. Ref Set 2 Bit 2 Non-inverted NOBLTRS2.2 12 L.T. Ref Set 2 Bit 2 Inverted IOBLTRS2.2 13 L.T. Ref Set 3 Bit 1 Non-inverted NOBLTRS3.1 14 L.T. Ref Set 3 Bit 1 Inverted IOBLTRS3.1 15 L.T. Ref Set 3 Bit 2 Non-inverted NOBLTRS3.2 16 L.T. Ref Set 3 Bit 2 Inverted IOBLTRS3.2 17 L.T. Ref Set 4 Bit 1 Non-inverted NOBLTRS4.1 18 L.T. Ref Set 4 Bit 1 Inverted IOBLTRS4.1 19 L.T. Ref Set 4 Bit 2 Non-inverted NOBLTRS4.2 20 L.T. Ref Set 4 Bit 2 Inverted IOBLTRS4.2 21 L.T. Ref Set 5 Bit 1 Non-inverted NOBLTRS5.1 22 L.T. Ref Set 5 Bit 1 Inverted IOBLTRS5.1 23 L.T. Ref Set 5 Bit 2 Non-inverted NOBLTRS5.2 24 L.T. Ref Set 5 Bit 2 Inverted IOBLTRS5.2 25 L.T. Ref Set 6 Bit 1 Non-inverted NOBLTRS6.1 26 L.T. Ref Set 6 Bit 1 Inverted IOBLTRS6.1 27 L.T. Ref Set 6 Bit 2 Non-inverted NOBLTRS6.2 28 L.T. Ref Set 6 Bit 2 Inverted IOBLTRS6.2 29 L.T. Ref Set 7 Bit 1 Non-inverted NOBLTRS7.1 30 L.T. Ref Set 7 Bit 1 Inverted IOBLTRS7.1 31 L.T. Ref Set 7 Bit 2 Non-inverted NOBLTRS7.2 32 L.T. Ref Set 7 Bit 2 Inverted IOBLTRS7.2 33 Unused 34 Unused ----------------------------------------------------------------------------- J8 : LARGE TILE TOTAL ET THIRD TIER COUNT FRONT CONNECTOR LARGE TILE SECOND TIER UPGRADE EXPANSION CONNECTOR (PROM OUTPUT "C") ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 L.T. Ref Set 0 Bit 1 Non-inverted NOCLTRS0.1 2 L.T. Ref Set 0 Bit 1 Inverted IOCLTRS0.1 3 L.T. Ref Set 0 Bit 2 Non-inverted NOCLTRS0.2 4 L.T. Ref Set 0 Bit 2 Inverted IOCLTRS0.2 5 L.T. Ref Set 0 Bit 3 Non-inverted NOCLTRS0.3 6 L.T. Ref Set 0 Bit 3 Inverted IOCLTRS0.3 7 L.T. Ref Set 0 Bit 4 Non-inverted NOCLTRS0.4 8 L.T. Ref Set 0 Bit 4 Inverted IOCLTRS0.4 9 L.T. Ref Set 1 Bit 1 Non-inverted NOCLTRS1.1 10 L.T. Ref Set 1 Bit 1 Inverted IOCLTRS1.1 11 L.T. Ref Set 1 Bit 2 Non-inverted NOCLTRS1.2 12 L.T. Ref Set 1 Bit 2 Inverted IOCLTRS1.2 13 L.T. Ref Set 1 Bit 3 Non-inverted NOCLTRS1.3 14 L.T. Ref Set 1 Bit 3 Inverted IOCLTRS1.3 15 L.T. Ref Set 1 Bit 4 Non-inverted NOCLTRS1.4 16 L.T. Ref Set 1 Bit 4 Inverted IOCLTRS1.4 17 L.T. Ref Set 2 Bit 1 Non-inverted NOCLTRS2.1 18 L.T. Ref Set 2 Bit 1 Inverted IOCLTRS2.1 19 L.T. Ref Set 2 Bit 2 Non-inverted NOCLTRS2.2 20 L.T. Ref Set 2 Bit 2 Inverted IOCLTRS2.2 21 L.T. Ref Set 2 Bit 3 Non-inverted NOCLTRS2.3 22 L.T. Ref Set 2 Bit 3 Inverted IOCLTRS2.3 23 L.T. Ref Set 2 Bit 4 Non-inverted NOCLTRS2.4 24 L.T. Ref Set 2 Bit 4 Inverted IOCLTRS2.4 25 L.T. Ref Set 3 Bit 1 Non-inverted NOCLTRS3.1 26 L.T. Ref Set 3 Bit 1 Inverted IOCLTRS3.1 27 L.T. Ref Set 3 Bit 2 Non-inverted NOCLTRS3.2 28 L.T. Ref Set 3 Bit 2 Inverted IOCLTRS3.2 29 L.T. Ref Set 3 Bit 3 Non-inverted NOCLTRS3.3 30 L.T. Ref Set 3 Bit 3 Inverted IOCLTRS3.3 31 L.T. Ref Set 3 Bit 4 Non-inverted NOCLTRS3.4 32 L.T. Ref Set 3 Bit 4 Inverted IOCLTRS3.4 33 L.T. Ref Set 4 Bit 1 Non-inverted NOCLTRS4.1 34 L.T. Ref Set 4 Bit 1 Inverted IOCLTRS4.1 35 L.T. Ref Set 4 Bit 2 Non-inverted NOCLTRS4.2 36 L.T. Ref Set 4 Bit 2 Inverted IOCLTRS4.2 37 L.T. Ref Set 4 Bit 3 Non-inverted NOCLTRS4.3 38 L.T. Ref Set 4 Bit 3 Inverted IOCLTRS4.3 39 L.T. Ref Set 4 Bit 4 Non-inverted NOCLTRS4.4 40 L.T. Ref Set 4 Bit 4 Inverted IOCLTRS4.4 41 L.T. Ref Set 5 Bit 1 Non-inverted NOCLTRS5.1 42 L.T. Ref Set 5 Bit 1 Inverted IOCLTRS5.1 43 L.T. Ref Set 5 Bit 2 Non-inverted NOCLTRS5.2 44 L.T. Ref Set 5 Bit 2 Inverted IOCLTRS5.2 45 L.T. Ref Set 5 Bit 3 Non-inverted NOCLTRS5.3 46 L.T. Ref Set 5 Bit 3 Inverted IOCLTRS5.3 47 L.T. Ref Set 5 Bit 4 Non-inverted NOCLTRS5.4 48 L.T. Ref Set 5 Bit 4 Inverted IOCLTRS5.4 49 L.T. Ref Set 6 Bit 1 Non-inverted NOCLTRS6.1 50 L.T. Ref Set 6 Bit 1 Inverted IOCLTRS6.1 51 L.T. Ref Set 6 Bit 2 Non-inverted NOCLTRS6.2 52 L.T. Ref Set 6 Bit 2 Inverted IOCLTRS6.2 53 L.T. Ref Set 6 Bit 3 Non-inverted NOCLTRS6.3 54 L.T. Ref Set 6 Bit 3 Inverted IOCLTRS6.3 55 L.T. Ref Set 6 Bit 4 Non-inverted NOCLTRS6.4 56 L.T. Ref Set 6 Bit 4 Inverted IOCLTRS6.4 57 L.T. Ref Set 7 Bit 1 Non-inverted NOCLTRS7.1 58 L.T. Ref Set 7 Bit 1 Inverted IOCLTRS7.1 59 L.T. Ref Set 7 Bit 2 Non-inverted NOCLTRS7.2 60 L.T. Ref Set 7 Bit 2 Inverted IOCLTRS7.2 61 L.T. Ref Set 7 Bit 3 Non-inverted NOCLTRS7.3 62 L.T. Ref Set 7 Bit 3 Inverted IOCLTRS7.3 63 L.T. Ref Set 7 Bit 4 Non-inverted NOCLTRS7.4 64 L.T. Ref Set 7 Bit 4 Inverted IOCLTRS7.4