+-----------------------------------------------------------+ | | | D0 CALORIMETER TRIGGER | | WIRE-WRAP PROTOTYPE ARRAY | | | +-----------------------------------------------------------+ 13-AUG-1991 GENERAL DESCRIPTION ------------------- The Wire-wrap Prototype Array (WPA) Board is a circuit board that contains: i) A 100K ECL CBUS interface, which implements the FULL CBUS interface specification, specifically it receives ALL 8 Timing and Sync Signals available, and provides FA decoding for 8 Read and 8 Write FA's ii) 100K receivers or drivers tied to each input pin on the 4 rear panel 96 pin DIN connectors (32 differential ECL signals per connector) iii) the center area of the card is a structured array of vias on a .1" x .1" grid. Power is distributed through this area iv) the right side of this board is an array of vias on a .1" x .1" grid. Power is available along the perimeter of this area v) Along the front panel, there will be two rows of vias, .1" apart, with .1" spacing along each row, suitable for installing right-angle connectors to allow signals to be distributed off-card. PURPOSE OF THE CARD ------------------- This card is intended to be a general-purpose prototype card, allowing us to build various "one-off" circuit boards. There are currently several circuit boards that we wish to own that could be built on this prototype platform: FMLN ECL-TTL converter TTL-ECL converter TRD "4-into-1" card (including ECL-TTL conversion) L0-to-L1 box any number of "test" cards for e.g. upgrade, Level 1.5... Individually, the CAD and manufacturing time of each of these cards would be rather large when compared to the number of cards required (1 or 2 in most cases). Having a common platform allows a large part of the design and manufacturing time to be "amortized" across several flavors of cards. STRUCTURE OF THE PROTOTYPING AREA --------------------------------- This card must be able to support a wide range of functionality built on a single platform. It must not make assumptions about the technology, chip size, or distribution of chips on the card. That tends to rule out the AUGAT-style "socket card" approach, with dedicated locations for e.g. 100K ECL chips, pre-wired with power and ground. Since 4 power supplies are required, it is not feasible to provide regularly-spaced full columns of each power supply. A reasonable compromise is to have regularly-spaced columns which contain, in alternating rows, all power supply voltages, as follows: T T <+-----+> v G+---+G v <+---+C <| |> v <| |> v <| |> <| |> v <| |> v <| |> <| |> v <| |> v <| |> <| |> v <| |> v <| |> G| |> v <| |> v <| |> G| |E v <| |> v <| |> <| |> v E+---+> v G+---+> <| |> v v G+---+> <| |> 10K G+---+> <| |> <| |> <+-----+> (16 pin) G+---+> 100K TTL (24 pin) (16, 18, 20, 24 pin) o-o-o T o-o-o-o T o-o-o T o-o-o-o T o = signal o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C N = GND o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N E = VEE o-o-o N o-o-o-o C o-o-o N o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N C = VCC o-o-o N o-o-o-o E o-o-o N o-o-o-o E o-o-o E o-o-o-o C o-o-o E o-o-o-o C T = VTT o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N - = connection o-o-o C o-o-o-o E o-o-o C o-o-o-o E o-o-o C o-o-o-o N o-o-o C o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N o-o-o N o-o-o-o C o-o-o N o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o E o-o-o N o-o-o-o E o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o C o-o-o-o E o-o-o C o-o-o-o E o-o-o C o-o-o-o N o-o-o C o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N o-o-o N o-o-o-o C o-o-o N o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o E o-o-o N o-o-o-o E o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o C o-o-o-o E o-o-o C o-o-o-o E o-o-o C o-o-o-o N o-o-o C o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N o-o-o N o-o-o-o C o-o-o N o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o E o-o-o N o-o-o-o E o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o C o-o-o-o E o-o-o C o-o-o-o E o-o-o C o-o-o-o N o-o-o C o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N o-o-o N o-o-o-o C o-o-o N o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o E o-o-o N o-o-o-o E o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o C o-o-o-o E o-o-o C o-o-o-o E o-o-o C o-o-o-o N o-o-o C o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o T o-o-o-o T o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o C o-o-o E o-o-o-o C o-o-o N o-o-o-o N o-o-o N o-o-o-o N o-o-o E o-o-o-o N o-o-o E o-o-o-o N . . . . The horizontal spacing is chosen to allow chips of common widths (0.3", 0.4", 0.6") to fit in almost arbitrary positions on the circuit board. No power supply pin is more than 0.2" from a ground pin, and no power supply pin is more than 0.4" away from a pin connected to the same supply, allowing for monolithic bypass caps to be placed near each chip with minimal difficulty. Bulk bypass caps can be placed in any unused area of the board. The vertical spacing is chosen to allow 2, 24-pin chips (including resistor packs) to fit in one contiguous area, while still allowing room for extractor tools to grab chips. The vertical spacing on the group of vias nearest the back of the PCB can support 3, 24-pin chips (including resistor packs) per column. The "open" columns contain silkscreen to describe the voltage available on the flanking pins. Additionally, a small section of this board is devoted to a PGA or analog circuitry area. Power is distributed around the perimeter of this area. Approximately 70 100K ECL chips with resistor packs can fit in the structured wire-wrap area. STRUCTURE OF THE REST OF THE CARD --------------------------------- The card has a FULL CBUS interface, implemented in 100K ECL. Note that this card receives ALL 8 Timing and Sync Signals, which are routed in etch to Wire-Wrap posts, and be pulled down in etch. Additionally, 8 Read and 8 Write Function Addresses are decoded . Separate Read and Write FA decoded lines are desired, for a total of 16 decoded FA lines. These decoded FA lines can be either active-high or active-low, selectable by jumper. The decoded Function Address lines are 1, 2, and either 3 or 8, selectable. Decoding FA 8 allows use of 29520s and allows data in both halves of the Data Block. These lines terminate in Wire-Wrap posts, and are pulled down in etch. A wake-up LED is provided in etch, along with 9 other unallocated LEDs with drivers. Each LED can be turned on with either an active-high or active-low signal, selectable by jumper. The LED driver inputs are brought to wire-wrap pins. Eight horizontal traces, suitable for use as Bidirectional Data Bits, are routed through the card. Rear panel connectors J3 and J2 have 100K ECL receivers (100114) in etch, including pull-down resistors. Rear panel connector J1 has 100K ECL drivers (100114) in etch, including pull-down resistors. Connectors J1 - J3 also have sockets for 110 Ohm Parallel Terminator resistors, and Spreader resistors. Power to the Spreaders is selectable on a per-connecter basis. The area allocated for front panel connections has traces brought to an array of vias appropriately spaced for wire wrapping. The front panel connector area has its via area far enough back to allow for Front Support Bar mounting holes, and there are extra mounting holes (total of 10) to allow for flexible connector allocation. ADDITIONAL NOTES ---------------- To be useful, the card must be powered like a CAT2/CAT3, simply because that is the power available in a Tier 2/3 Backplane. The card could be used in a Framework Backplane, if we build the Framework Backplane-to-Cal Trig Card Paddleboard, a project which has been discussed as a way to use a CTMBD as a FWMBD (which has advantages in its own right). Power distribution of +5V is limited to 16 amps, this is derived from the conservative rating of 2 amps/pin. Height of card: recall that most wire wrap sockets have long legs, therefore solder tail sockets will be used along with pin-up wire-wrap pins. This solution avoids the problem of wire-wrap posts extending down onto the card below. All wire-wrap work will be done on the top of the card. How long would it take to make? (my guess: 3-4 weeks, mostly student time) DESCRIPTION OF THE CONNECTORS ----------------------------------------- J1 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Ground GND 8 Ground GND 9 Ground GND 10 Ground GND 11 Ground GND 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Power -2.0 V VTT 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 J1 Output Bit 1 Inverted OUT IO1.1 34 J1 Output Bit 2 Inverted OUT IO1.2 35 J1 Output Bit 3 Inverted OUT IO1.3 36 J1 Output Bit 4 Inverted OUT IO1.4 37 J1 Output Bit 5 Inverted OUT IO1.5 38 J1 Output Bit 6 Inverted OUT IO1.6 39 J1 Output Bit 7 Inverted OUT IO1.7 40 J1 Output Bit 8 Inverted OUT IO1.8 41 J1 Output Bit 9 Inverted OUT IO1.9 42 J1 Output Bit 10 Inverted OUT IO1.10 43 J1 Output Bit 11 Inverted OUT IO1.11 44 J1 Output Bit 12 Inverted OUT IO1.12 45 J1 Output Bit 13 Inverted OUT IO1.13 46 J1 Output Bit 14 Inverted OUT IO1.14 47 J1 Output Bit 15 Inverted OUT IO1.15 48 J1 Output Bit 16 Inverted OUT IO1.16 49 J1 Output Bit 17 Inverted OUT IO1.17 50 J1 Output Bit 18 Inverted OUT IO1.18 51 J1 Output Bit 19 Inverted OUT IO1.19 52 J1 Output Bit 20 Inverted OUT IO1.20 53 J1 Output Bit 21 Inverted OUT IO1.21 54 J1 Output Bit 22 Inverted OUT IO1.22 55 J1 Output Bit 23 Inverted OUT IO1.23 56 J1 Output Bit 24 Inverted OUT IO1.24 57 J1 Output Bit 25 Inverted OUT IO1.25 58 J1 Output Bit 26 Inverted OUT IO1.26 59 J1 Output Bit 27 Inverted OUT IO1.27 60 J1 Output Bit 28 Inverted OUT IO1.28 61 J1 Output Bit 29 Inverted OUT IO1.29 62 J1 Output Bit 30 Inverted OUT IO1.30 63 J1 Output Bit 31 Inverted OUT IO1.31 64 J1 Output Bit 32 Inverted OUT IO1.32 65 J1 Output Bit 1 Non-Inverted OUT NO1.1 66 J1 Output Bit 2 Non-inverted OUT NO1.2 67 J1 Output Bit 3 Non-inverted OUT NO1.3 68 J1 Output Bit 4 Non-inverted OUT NO1.4 69 J1 Output Bit 5 Non-inverted OUT NO1.5 70 J1 Output Bit 6 Non-inverted OUT NO1.6 71 J1 Output Bit 7 Non-inverted OUT NO1.7 72 J1 Output Bit 8 Non-inverted OUT NO1.8 73 J1 Output Bit 9 Non-inverted OUT NO1.9 74 J1 Output Bit 10 Non-inverted OUT NO1.10 75 J1 Output Bit 11 Non-inverted OUT NO1.11 76 J1 Output Bit 12 Non-inverted OUT NO1.12 77 J1 Output Bit 13 Non-inverted OUT NO1.13 78 J1 Output Bit 14 Non-inverted OUT NO1.14 79 J1 Output Bit 15 Non-inverted OUT NO1.15 80 J1 Output Bit 16 Non-inverted OUT NO1.16 81 J1 Output Bit 17 Non-inverted OUT NO1.17 82 J1 Output Bit 18 Non-inverted OUT NO1.18 83 J1 Output Bit 19 Non-inverted OUT NO1.19 84 J1 Output Bit 20 Non-inverted OUT NO1.20 85 J1 Output Bit 21 Non-inverted OUT NO1.21 86 J1 Output Bit 22 Non-inverted OUT NO1.22 87 J1 Output Bit 23 Non-inverted OUT NO1.23 88 J1 Output Bit 24 Non-inverted OUT NO1.24 89 J1 Output Bit 25 Non-inverted OUT NO1.25 90 J1 Output Bit 26 Non-inverted OUT NO1.26 91 J1 Output Bit 27 Non-inverted OUT NO1.27 92 J1 Output Bit 28 Non-inverted OUT NO1.28 93 J1 Output Bit 29 Non-inverted OUT NO1.29 94 J1 Output Bit 30 Non-inverted OUT NO1.30 95 J1 Output Bit 31 Non-inverted OUT NO1.31 96 J1 Output Bit 32 Non-inverted OUT NO1.32 ----------------------------------------------------------------------------- J2 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Ground GND 7 Unused 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Power -2.0 V VTT 12 Unused 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Power -4.5 V VEE 17 Unused 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Power -4.5 V VEE 22 Unused 23 Power +5.0 V VCC 24 Power +5.0 V VCC 25 Power +5.0 V VCC 26 Power +5.0 V VCC 27 Unused 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 J2 Input Bit 1 Inverted IN II2.1 34 J2 Input Bit 2 Inverted IN II2.2 35 J2 Input Bit 3 Inverted IN II2.3 36 J2 Input Bit 4 Inverted IN II2.4 37 J2 Input Bit 5 Inverted IN II2.5 38 J2 Input Bit 6 Inverted IN II2.6 39 J2 Input Bit 7 Inverted IN II2.7 40 J2 Input Bit 8 Inverted IN II2.8 41 J2 Input Bit 9 Inverted IN II2.9 42 J2 Input Bit 10 Inverted IN II2.10 43 J2 Input Bit 11 Inverted IN II2.11 44 J2 Input Bit 12 Inverted IN II2.12 45 J2 Input Bit 13 Inverted IN II2.13 46 J2 Input Bit 14 Inverted IN II2.14 47 J2 Input Bit 15 Inverted IN II2.15 48 J2 Input Bit 16 Inverted IN II2.16 49 J2 Input Bit 17 Inverted IN II2.17 50 J2 Input Bit 18 Inverted IN II2.18 51 J2 Input Bit 19 Inverted IN II2.19 52 J2 Input Bit 20 Inverted IN II2.20 53 J2 Input Bit 21 Inverted IN II2.21 54 J2 Input Bit 22 Inverted IN II2.22 55 J2 Input Bit 23 Inverted IN II2.23 56 J2 Input Bit 24 Inverted IN II2.24 57 J2 Input Bit 25 Inverted IN II2.25 58 J2 Input Bit 26 Inverted IN II2.26 59 J2 Input Bit 27 Inverted IN II2.27 60 J2 Input Bit 28 Inverted IN II2.28 61 J2 Input Bit 29 Inverted IN II2.29 62 J2 Input Bit 30 Inverted IN II2.30 63 J2 Input Bit 31 Inverted IN II2.31 64 J2 Input Bit 32 Inverted IN II2.32 65 J2 Input Bit 1 Non-inverted IN NI2.1 66 J2 Input Bit 2 Non-inverted IN NI2.2 67 J2 Input Bit 3 Non-inverted IN NI2.3 68 J2 Input Bit 4 Non-inverted IN NI2.4 69 J2 Input Bit 5 Non-inverted IN NI2.5 70 J2 Input Bit 6 Non-inverted IN NI2.6 71 J2 Input Bit 7 Non-inverted IN NI2.7 72 J2 Input Bit 8 Non-inverted IN NI2.8 73 J2 Input Bit 9 Non-inverted IN NI2.9 74 J2 Input Bit 10 Non-inverted IN NI2.10 75 J2 Input Bit 11 Non-inverted IN NI2.11 76 J2 Input Bit 12 Non-inverted IN NI2.12 77 J2 Input Bit 13 Non-inverted IN NI2.13 78 J2 Input Bit 14 Non-inverted IN NI2.14 79 J2 Input Bit 15 Non-inverted IN NI2.15 80 J2 Input Bit 16 Non-inverted IN NI2.16 81 J2 Input Bit 17 Non-inverted IN NI2.17 82 J2 Input Bit 18 Non-inverted IN NI2.18 83 J2 Input Bit 19 Non-inverted IN NI2.19 84 J2 Input Bit 20 Non-inverted IN NI2.20 85 J2 Input Bit 21 Non-inverted IN NI2.21 86 J2 Input Bit 22 Non-inverted IN NI2.22 87 J2 Input Bit 23 Non-inverted IN NI2.23 88 J2 Input Bit 24 Non-inverted IN NI2.24 89 J2 Input Bit 25 Non-inverted IN NI2.25 90 J2 Input Bit 26 Non-inverted IN NI2.26 91 J2 Input Bit 27 Non-inverted IN NI2.27 92 J2 Input Bit 28 Non-inverted IN NI2.28 93 J2 Input Bit 29 Non-inverted IN NI2.29 94 J2 Input Bit 30 Non-inverted IN NI2.30 95 J2 Input Bit 31 Non-inverted IN NI2.31 96 J2 Input Bit 32 Non-inverted IN NI2.32 ----------------------------------------------------------------------------- J3 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power +5.0 V VCC 8 Power +5.0 V VCC 9 Power +5.0 V VCC 10 Power +5.0 V VCC 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Power -2.0 V VTT 23 Power -2.0 V VTT 24 Power -2.0 V VTT 25 Power -2.0 V VTT 26 Unused 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 J3 Input Bit 1 Inverted IN II3.1 34 J3 Input Bit 2 Inverted IN II3.2 35 J3 Input Bit 3 Inverted IN II3.3 36 J3 Input Bit 4 Inverted IN II3.4 37 J3 Input Bit 5 Inverted IN II3.5 38 J3 Input Bit 6 Inverted IN II3.6 39 J3 Input Bit 7 Inverted IN II3.7 40 J3 Input Bit 8 Inverted IN II3.8 41 J3 Input Bit 9 Inverted IN II3.9 42 J3 Input Bit 10 Inverted IN II3.10 43 J3 Input Bit 11 Inverted IN II3.11 44 J3 Input Bit 12 Inverted IN II3.12 45 J3 Input Bit 13 Inverted IN II3.13 46 J3 Input Bit 14 Inverted IN II3.14 47 J3 Input Bit 15 Inverted IN II3.15 48 J3 Input Bit 16 Inverted IN II3.16 49 J3 Input Bit 17 Inverted IN II3.17 50 J3 Input Bit 18 Inverted IN II3.18 51 J3 Input Bit 19 Inverted IN II3.19 52 J3 Input Bit 20 Inverted IN II3.20 53 J3 Input Bit 21 Inverted IN II3.21 54 J3 Input Bit 22 Inverted IN II3.22 55 J3 Input Bit 23 Inverted IN II3.23 56 J3 Input Bit 24 Inverted IN II3.24 57 J3 Input Bit 25 Inverted IN II3.25 58 J3 Input Bit 26 Inverted IN II3.26 59 J3 Input Bit 27 Inverted IN II3.27 60 J3 Input Bit 28 Inverted IN II3.28 61 J3 Input Bit 29 Inverted IN II3.29 62 J3 Input Bit 30 Inverted IN II3.30 63 J3 Input Bit 31 Inverted IN II3.31 64 J3 Input Bit 32 Inverted IN II3.32 65 J3 Input Bit 1 Non-inverted IN NI3.1 66 J3 Input Bit 2 Non-inverted IN NI3.2 67 J3 Input Bit 3 Non-inverted IN NI3.3 68 J3 Input Bit 4 Non-inverted IN NI3.4 69 J3 Input Bit 5 Non-inverted IN NI3.5 70 J3 Input Bit 6 Non-inverted IN NI3.6 71 J3 Input Bit 7 Non-inverted IN NI3.7 72 J3 Input Bit 8 Non-inverted IN NI3.8 73 J3 Input Bit 9 Non-inverted IN NI3.9 74 J3 Input Bit 10 Non-inverted IN NI3.10 75 J3 Input Bit 11 Non-inverted IN NI3.11 76 J3 Input Bit 12 Non-inverted IN NI3.12 77 J3 Input Bit 13 Non-inverted IN NI3.13 78 J3 Input Bit 14 Non-inverted IN NI3.14 79 J3 Input Bit 15 Non-inverted IN NI3.15 80 J3 Input Bit 16 Non-inverted IN NI3.16 81 J3 Input Bit 17 Non-inverted IN NI3.17 82 J3 Input Bit 18 Non-inverted IN NI3.18 83 J3 Input Bit 19 Non-inverted IN NI3.19 84 J3 Input Bit 20 Non-inverted IN NI3.20 85 J3 Input Bit 21 Non-inverted IN NI3.21 86 J3 Input Bit 22 Non-inverted IN NI3.22 87 J3 Input Bit 23 Non-inverted IN NI3.23 88 J3 Input Bit 24 Non-inverted IN NI3.24 89 J3 Input Bit 25 Non-inverted IN NI3.25 90 J3 Input Bit 26 Non-inverted IN NI3.26 91 J3 Input Bit 27 Non-inverted IN NI3.27 92 J3 Input Bit 28 Non-inverted IN NI3.28 93 J3 Input Bit 29 Non-inverted IN NI3.29 94 J3 Input Bit 30 Non-inverted IN NI3.30 95 J3 Input Bit 31 Non-inverted IN NI3.31 96 J3 Input Bit 32 Non-inverted IN NI3.32 ----------------------------------------------------------------------------- J4 : FIRST LEVEL CALORIMETER TRIGGER BACKPLANE 96 PIN CONNECTOR ----------------------------------------------------------------------------- Pin Function Mnemonic ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Ground GND 4 Ground GND 5 Ground GND 6 Unused 7 Power -2.0 V VTT 8 Power -2.0 V VTT 9 Power -2.0 V VTT 10 Power -2.0 V VTT 11 Unused 12 Power -4.5 V VEE 13 Power -4.5 V VEE 14 Power -4.5 V VEE 15 Power -4.5 V VEE 16 Unused 17 Power -4.5 V VEE 18 Power -4.5 V VEE 19 Power -4.5 V VEE 20 Power -4.5 V VEE 21 Unused 22 Ground GND 23 Ground GND 24 Ground GND 25 Ground GND 26 Ground GND 27 Ground GND 28 Ground GND 29 Ground GND 30 Ground GND 31 Ground GND 32 Ground GND 33 Timing & Sync. Signal A Inverted IN ITSA 34 Timing & Sync. Signal B Inverted IN ITSB 35 Timing & Sync. Signal C Inverted IN ITSC 36 Timing & Sync. Signal D Inverted IN ITSD 37 Timing & Sync. Signal E Inverted IN ITSE 38 Timing & Sync. Signal F Inverted IN ITSF 39 Timing & Sync. Signal G Inverted IN ITSG 40 Timing & Sync. Signal H Inverted IN ITSH 41 Card Address Bit#1 Inverted IN IAC1 42 Card Address Bit#2 Inverted IN IAC2 43 Card Address Bit#3 Inverted IN IAC3 44 Card Address Bit#4 Inverted IN IAC4 45 Card Address Bit#5 Inverted IN IAC5 46 Card Address Bit#6 Inverted IN IAC6 47 Function Address Bit#1 Inverted IN IAF1 48 Function Address Bit#2 Inverted IN IAF2 49 Function Address Bit#3 Inverted IN IAF3 50 Function Address Bit#4 Inverted IN IAF4 51 Function Address Bit#5 Inverted IN IAF5 52 Function Address Bit#6 Inverted IN IAF6 53 Function Address Bit#7 Inverted IN IAF7 54 Function Address Bit#8 Inverted IN IAF8 55 Strobe Inverted IN ISTS 56 Direction Inverted IN IDIR 57 Bidirectional Data Bit#1 Inverted IDB1 58 Bidirectional Data Bit#2 Inverted IDB2 59 Bidirectional Data Bit#3 Inverted IDB3 60 Bidirectional Data Bit#4 Inverted IDB4 61 Bidirectional Data Bit#5 Inverted IDB5 62 Bidirectional Data Bit#6 Inverted IDB6 63 Bidirectional Data Bit#7 Inverted IDB7 64 Bidirectional Data Bit#8 Inverted IDB8 65 Timing & Sync. Signal A Non-inverted IN NTSA 66 Timing & Sync. Signal B Non-inverted IN NTSB 67 Timing & Sync. Signal C Non-inverted IN NTSC 68 Timing & Sync. Signal D Non-inverted IN NTSD 69 Timing & Sync. Signal E Non-inverted IN NTSE 70 Timing & Sync. Signal F Non-inverted IN NTSF 71 Timing & Sync. Signal G Non-inverted IN NTSG 72 Timing & Sync. Signal H Non-inverted IN NTSH 73 Card Address Bit#1 Non-inverted IN NAC1 74 Card Address Bit#2 Non-inverted IN NAC2 75 Card Address Bit#3 Non-inverted IN NAC3 76 Card Address Bit#4 Non-inverted IN NAC4 77 Card Address Bit#5 Non-inverted IN NAC5 78 Card Address Bit#6 Non-inverted IN NAC6 79 Function Address Bit#1 Non-inverted IN NAF1 80 Function Address Bit#2 Non-inverted IN NAF2 81 Function Address Bit#3 Non-inverted IN NAF3 82 Function Address Bit#4 Non-inverted IN NAF4 83 Function Address Bit#5 Non-inverted IN NAF5 84 Function Address Bit#6 Non-inverted IN NAF6 85 Function Address Bit#7 Non-inverted IN NAF7 86 Function Address Bit#8 Non-inverted IN NAF8 87 Strobe Non-inverted IN NSTB 88 Direction Non-inverted IN NDIR 89 Bidirectional Data Bit#1 Non-inverted NDB1 90 Bidirectional Data Bit#2 Non-inverted NDB2 91 Bidirectional Data Bit#3 Non-inverted NDB3 92 Bidirectional Data Bit#4 Non-inverted NDB4 93 Bidirectional Data Bit#5 Non-inverted NDB5 94 Bidirectional Data Bit#6 Non-inverted NDB6 95 Bidirectional Data Bit#7 Non-inverted NDB7 96 Bidirectional Data Bit#8 Non-inverted NDB8