M101 PATCH PANEL SPECIFICATIONS ------------------------------- The purpose of this file is to fully document the M101 Patch Panel, so that it can be recreated with minor changes in the future.There are several signals that make use of the M101 Patch Panel. They are: 1. Front-End Busy Input 2. Start Digitize Command 3. Hold Transfer Command 4. Trigger Number 5. All Nodes in Queue Busy (2nd Level Disable) 6. Front-End Busy Specific Trigger Disable 7. Auxiliary Timing MTG 8. Auxiliary Data IMLROs Front-End Busy Input -------------------- The Front-End Busy input arrives at the M101 Patch Panel via a 64-conductor twist-and-flat cable to a 64-pin connector. This cable is in proper polarity but reverse bit order (Front-End Busy number 1 is on pin pair 63-64).It is then mapped into two 64-pin connectors in a configuration suitable for input to an MTG card, as listed below: PIN PIN NUMBERS FRONT-END NUMBERS ON MTG BUSY ON BUSY CH# 1-16 NUMBER CABLE CABLE -------- ------- --------- 1 63-64 61-62 2 61-62 59-60 3 59-60 53-54 4 57-58 51-52 5 55-56 45-46 6 53-54 43-44 7 51-52 37-38 8 49-50 35-36 9 47-48 29-30 10 45-46 27-28 11 43-44 21-22 12 41-42 19-20 13 39-40 13-14 14 37-38 11-12 15 35-36 5-6 16 33-34 3-4 PIN PIN NUMBERS FRONT-END NUMBERS ON MTG BUSY ON BUSY CH# 17-32 NUMBER CABLE CABLE -------- ------- --------- 17 31-32 61-62 18 29-30 59-60 19 27-28 53-54 20 25-26 51-52 21 23-24 45-46 22 21-22 43-44 23 19-20 37-38 24 17-18 35-36 25 15-16 29-30 26 13-14 27-28 27 11-12 21-22 28 9-10 19-20 29 7-8 13-14 30 5-6 11-12 31 3-4 5-6 32 1-2 3-4 This mapping is to be done with two "octopus" cables. Each cable should have a 34-contact header on the Front-End Busy input end, mapping to eight 4-contact headers on the MTG end as shown above. The cable for Front-End Busy 1-16 should be made from 3 1/2" long twisted pairs, and the cable for Front-End Busy 17-32 should be made from 4 7/8" long twisted pairs. No inversions take place. After the Front-End Busy inputs pass through the Front-End Busy Controller MTG, they again enter the M101 Patch Panel via a 64-pin connector. They enter the rear of this connector in normal order. From the front of this connector comes a 64-conductor twist-and-flat cable (in reverse order) which connects to the Front-End Busy to Specific Trigger Disable TLM. Start Digitize and Hold Transfer Commands ----------------------------------------- The Start Digitize signal comes from the Start Digitize TLM in M102. It sends signals via a 64-conductor twist-and-flat cable to a 64-pin connector in the M101 Patch Panel. From this connector, four 64-pin connectors are driven, using the map given above. Note, however, that the Start Digize cable enters in normal order, while the Front-End Busy cable entered in reverse order. This causes Start Digitize #1 to appear on pins 1-2 of the lower connector (where Front-End Busy #32 appeared). This mapping is done with the same type of octopus cable feeding one pair of headers, and then wire-wrapping the other pair in parallel. In a future revision of the Patch Panel, this mapping will be done as two distinct mappings (both like the Front-End Busy mapping). Note also that another 64-conductor cable comes from this TLM, passes through the M101 Patch Panel, and is fed to the Auxiliary Data IMLRO Channel 1. Trigger Number -------------- The Trigger Number is generated in a DBSC in M101. It enters the M101 Patch Panel via a 64-conductor twist-and-flat cable to a 64-pin connector. Note that it is in normal order and polarity. From the reverse side of this 64-pin connector comes another 64-conductor twist-and-flat cable, which goes to the Trigger Number TLM's in M102 (in reverse order). All Nodes in Queue Busy ----------------------- All Nodes in Queue Busy Cables 1 and 2 enter the M101 Patch Panel on two 34-pin headers (in normal order and polarity). The 2nd Level Disable signals are sent to the FSTDs from the reverse side of this connector by twisted-pair cables. Also, pins 1 through 32 of both cables are wire-wrapped in normal order to one 64-pin connector to be sent to the Auxiliary Data IMLRO Channel 3. IMPORTANT NOTE: there is a logical inversion in the wire-wrap wires, AND the cable to the Aux Data IMLRO must be put on this connector from the back and upside down. This causes the input to the IMLRO to be in normal order, normal polarity. Front-End Busy Specific Trigger Disable --------------------------------------- The Front-End Busy Specific Trigger Disable signals enter the M101 Patch Panel via 32 twisted-pair cables to a 64-pin connector. They simply pass through this connector to the FSTDs. Also, another 64-pin connector is wire-wrapped in parallel (no inversions) to this one to feed the Aux Data IMLRO Channel 2. Auxiliary Timing MTG -------------------- The Auxiliary Timing MTG is connected to a 64-pin connector in the M101 Patch Panel. Note that an "in-line" bit order inversion is required between the Aux Timing MTG and the M101 Patch Panel to make the timing signals available in normal order at the Patch Panel connector Second Auxiliary Data IMLRO --------------------------- One channel of the second Auxiliary Data IMLRO is connected to a 64-pin connector in the M101 Patch Panel. Note that an "in-line" bit order inversion is required between the second Aux Data IMLRO and the Patch Panel to allow normal-order input of data at the Patch Panel connector.