WIRING OF THE SIGNALS FOR THE TRIGGER ACQUISITION SYNCHRONIZATION CABLES ======================================================================== 23-MAY-88 Each of the 32 Trigger Acquisition Synchronization Cables will carry 4 different types of signals: 1. The 16 Bit Trigger Number Count (common to all 32 cables). 2. A Start Digitization Signal (a unique signal per cable). 3. A Hold Transfer Signal (old clear most recent trigger). 4. A Busy Signal (a unique signal per cable). 5. one spare differential signal pair. SOURCE OF THESE SIGNALS ----------------------- The 16 Bit Trigger Number Count ------------------------------- The Trigger Number Count is made by a DBSC scaler card. The DBSC card that is used for this is in Rack M101 Top Backplane, slot number 13, Card Address 43. In earlier versions this was to be a beam crossing number, but was changed to Trigger Number because it would still be "unique" but would roll over less often. A full 40 Beam Crossing Number is still part of the First Level Trigger Data Block. The required 32 "copies" of the 16 Bit Trigger Number are made in the following way. A 16 bit long signal is taken from the output of the DBSC and "double connected" to the inputs of 4 TLM's (the Trigger Number Driver TLM's). That is, the 16 bits from the DBSC are connected to bits 1 through 16 and also connected to bits 17 through 32 at the input of the 4 TLM's. This "double connection" is done by using two of the 64 pin patch pannel connectors, by connecting from the "input" patch panel connector to the "output patch panel connector with wire wrap wires. Thus, a standard 32 signal cable enters the "input" connector on the front of patch panel, wire wrap wires connect pins 1-32 on the input connector to pins 1-32 and 33-64 on the "output" connector, and a standard 32 signal flat cable goes from this patch panel "output" connector to the input connectors of the 4 Trigger Number Driver TLM's. It is understood that this will not invert the differential signals in the Trigger Number because of passing through the patch panel twice. This patch panel is located in rack M101. Each of the 4 TLM's makes 8 "copies" of the 16 Bit Trigger Number. These "copies" are available on the backplane connectors. A 64 pin cable header is connected to each of the 4 outputs on each TLM card and it carries two copies of the 16 Bit Trigger Number. The 64 conductor flat cable coming from each 64 pin cable header splits into two 32 conductor flat cables each one of which carries a "copy" of the 16 Bit Trigger Number. These 32 conductor flat cables are fitted with standard 34 pin cable headers and the 32 conductor cable is offset so that it uses pins 3 through 34 of the 34 pin cable header. The mapping of the Trigger Number from the TLM to the Trigger Acquisition Synchronization Patch Panel is selected to simplify the physical routing of these 64 conductor flat cables by minimizing the horizontal displacement each cable must undergo. The following table specifies this mapping. Trigger Acquisition Synchronization Cable TLM Slot Connector Bits ------------------------------------------------------------------------------- 1 15 J1-lower 1-16 2 15 J1-lower 17-32 3 16 J1-lower 1-16 4 16 J1-lower 17-32 5 17 J1-lower 1-16 6 17 J1-lower 17-32 7 18 J1-lower 1-16 8 18 J1-lower 17-32 9 15 J1-upper 1-16 10 15 J1-upper 17-32 11 16 J1-upper 1-16 12 16 J1-upper 17-32 13 17 J1-upper 1-16 14 17 J1-upper 17-32 15 18 J1-upper 1-16 16 18 J1-upper 17-32 17 15 J2-lower 1-16 18 15 J2-lower 17-32 19 16 J2-lower 1-16 20 16 J2-lower 17-32 21 17 J2-lower 1-16 22 17 J2-lower 17-32 23 18 J2-lower 1-16 24 18 J2-lower 17-32 25 15 J2-upper 1-16 26 15 J2-upper 17-32 27 16 J2-upper 1-16 28 16 J2-upper 17-32 29 17 J2-upper 1-16 30 17 J2-upper 17-32 31 18 J2-upper 1-16 32 18 J2-upper 17-32 Note, that between the front input connector of the TLM and the backplane output connectors there is an "inversion" in the order of the signals (i.e. the signal from the first pair of pins on the input front connector is sent to backplane signal 31, 63, 95 and 127 ). This is not a problem because there will also be an "inversion" when the signals pass through the following 40 pin straight through header in the Trigger Acquisition Synchronization Patch Panel. Note also that the front panel output of the TLM card does not suffer this inversion. Each one of these 34 pin cable headers is connected to a 40 pin straight through header on the Trigger Acquisition Synchronization Patch Panel. The cable header is connected offset so that pins 1 and 2 of the cable header make no connection. Pins 3,4 of the cable header connect to pins 1,2 of the straight through header.... pins 33,34 of the cable header connect to pins 31,32 of the straight through header. Note, this is the second inversion of the 16 Bit Trigger Number. Pins 33 through 40 of the straight through header are bent at an angle (less than 0.1" displacement) to make clearance for the side of the 34 pin cable header which carries the 16 Bit Trigger Number. This is easy to do because there are 0.6" wire wrap pins on the straight through header. Connections to pins 33 through 38 of the straight through header will be made with AMP 2 contact housings so there is enough space to make the above bend and make good connections to these pins. Start Digitization Signals -------------------------- There are 32 seperate Start Digitize Signals. These signals come from the 8 DIGIMEM cards that map Specific Trigger Fired Signals into Start Digitize Signals. There is a cable harness that gathers these signals from the DIGIMEM cards and connects them to the input of a TLM card (the Start Digitize Signal Driver TLM). This harness is made from 32 standard twisted-pair cables. The TLM end of this harness uses 2 AMP 34 Contact Housings and is wired in the normal way (i.e. red on top). The 8 DIGIMEM ends of this harness use 8 AMP 34 Contact Housings. At the Digimem end care must be taken to connect the cables in the harness to the proper pins (27-34) and to invert the normal color code. Because the output of the DIGIMEM is LOW active the housings should be loaded with black on top. The signal from the DIGIMEM for Start Digitization Signal Number 1 is connected to the pins 63-64 end of the input connector on the Start Digitization Signal Driver TLM. Two outputs of the Start Digitization Signal Driver TLM are used. One of the Start Digitization Signal Driver TLM outputs is used for supplying the Start Digitization signals to two MTG s that will supply both the Start Digitize and the Hold Transfer signals to the Trigger Acquisition and Synchronization Cables. This connection is made via a twisted-pair ribbon cable. This cable runs from a backplane TLM output to a front panel header on the M101 Patch Panel. On the other side of the header are 32 twisted-pair jumpers, which deliver the Start Digitize Signals to two 64 pin headers, in a proper orientation for input to an MTG card, in normal polarity. It is understood that we see no inversion due to this signal passing through the patch panel twice pin straight through headers on the Trigger Acquisition Synchronization Patch Panel. The MTGs are used to control the Start Digitize and Hold Transfer signals. Their backplane outputs will be connected to the Trigger Acquisition and Synchronization Patch Panel. These outputs will be in reverse order due to passing through the MTG card, which is the order that the patch panel expects to see. The other output from the Start Digitize Signal Driver TLM is connected via a standard 32 signal flat cable to the Auxiliary Data IMLRO card in rack M101. This connection to the Auxiliary Data IMLRO card is to provide a path via which the computer can read the status of the Start Digitize signals. It is taken from the front panel connector of the TLM on the flat cable, with the bits in reverse order (Start Digitize 1 is on pins 63, 64) and passed to the M101 patch panel. It passes through that patch panel, returning to normal order, and then goes to the first section (bits 1-32) of the Auxiliary Data IMLRO. Busy Signals ------------ 32 separate Busy Signals are received in the Trigger Framework via the Trigger Acquisition Synchronization Cables. The signals arrive in the Framework on pins 35 and 36 of the 40 straight through headers in the Trigger Acquisition Synchronization Patch Panel. They are collected and placed on a 64 pin header on the Trigger Acquisition Synchronization Patch Panel using 32 twisted-pair cables. They appear on this header in reverse order. They then go to the Patch Panel in M101, and are mapped into 2 64 pin headers in a proper configuration to be used as input to an MTG card. Due to passing through this patch panel twice, we see no inversion in this signal. The MTG card can provide simulated busy signals to the TLM card that drives the Busy Signal DIGIMEM Backplane. The output of the MTG is fed to a 64 pin straight through header on the M101 Patch Panel by a twisted-pair ribbon cable. Another twisted-pair ribbon cable takes the Busy Signals from that header to the input of the TLM card. It is understood that an inversion takes place due to passing through the MTG card, and another inversion takes place due to passing through the Patch Panel. Therefore, the Busy Signals are in reverse order at the input to the TLM, which is correct. Hold Transfer Signals --------------------- The Hold Transfer Signals will be controlled by an MTG card, as discussed in the Start Digitize Signals paragraph. THIS SECTION IS ABOUT THE ROUTING OF THE FRONT-END BUSY SIGNALS THROUGH A MTG CARD ON THEIR WAY TO THE TLM THAT DRIVES THE BUSY DIGIMEM'S ------------------------------------------------------------------------- 8-July-1988 The MTG board that handles the BUSY Signals is in rack M101 in the TOP Backplane in Slot number 20. This MTG board has Card Address = 41. The Busy Signals arrive on the Trigger-Acquisition-Synchronization Cables and are collected into one 32 signal flat cable by the patch panel in Rack M102. This flat cable has the 32 signals in the proper polarity but in reverse order (the Busy Signal for Specific Trigger #32 is on pins 1 and 2 of this cable). This flat cable carries the 32 Busy Signals to the patch panel in Rack M101 where these signals are divided into two groups (Specific Triggers 1 through 16, and Specific Triggers 17 through 32). Then these two groups of Busy Signals are connected to the MTG that "controls" the Busy Signals before they are feed to the TLM that drives the Busy DIGIMEM. The "Busy Signal controller MTG" can be programed. via the CBUS, to control each Busy Signal individually in the following ways: 1). A Busy Signal from the Trigger-Acquisition-Synchronization Cable can be allowed to flow unchanged into the TLM. To select this option load a 10 at the Function Address of the control register of the desired MTG channel. 2). A Busy Signal from the Trigger-Acquisition-Synchronization Cable can be blocked from flowing to the TLM and instead that channel of the TLM can be driven LOW. To select this option load a 0 at the Function Address of the control register of the desired MTG channel. 3). A Busy Signal from the Trigger-Acquisition-Synchronization Cable can be blocked from flowing to the TLM and instead that channel of the TLM can be driven High. To select this option load a 25 at the Function Address of the control register of the desired MTG channel. ORGANIZATION OF THE SIGNALS FOR THE "BUSY SIGNAL CONTROLLER MTG" ---------------------------------------------------------------- PIN PIN NUMBERS SPECIFIC NUMBERS ON MTG MTG MTG TRIGGER ON BUSY CH# 1-16 CHANNEL FUNCTION NUMBER CABLE CABLE NUMBER ADDRESS -------- ------- --------- ------- -------- 1 63-64 61-62 1 0 2 61-62 59-60 2 1 3 59-60 53-54 3 2 4 57-58 51-52 4 3 5 55-56 45-46 5 4 6 53-54 43-44 6 5 7 51-52 37-38 7 6 8 49-50 35-36 8 7 9 47-48 29-30 9 8 10 45-46 27-28 10 9 11 43-44 21-22 11 10 12 41-42 19-20 12 11 13 39-40 13-14 13 12 14 37-38 11-12 14 13 15 35-36 5-6 15 14 16 33-34 3-4 16 15 PIN PIN NUMBERS SPECIFIC NUMBERS ON MTG MTG MTG TRIGGER ON BUSY CH# 17-32 CHANNEL FUNCTION NUMBER CABLE CABLE NUMBER ADDRESS -------- ------- --------- ------- -------- 17 31-32 61-62 17 16 18 29-30 59-60 18 17 19 27-28 53-54 19 18 20 25-26 51-52 20 19 21 23-24 45-46 21 20 22 21-22 43-44 22 21 23 19-20 37-38 23 22 24 17-18 35-36 24 23 25 15-16 29-30 25 24 26 13-14 27-28 26 25 27 11-12 21-22 27 26 28 9-10 19-20 28 27 29 7-8 13-14 29 28 30 5-6 11-12 30 29 31 3-4 5-6 31 30 32 1-2 3-4 32 31 In addition to the above mentioned Function Addresses the following two Function Addresses should be programmed before using the MTG: FA 37 should be loaded with a 0, FA 38 should be loaded with a 0. One can also use the MTG to read the state of the signal that is being sent to the TLM. This is done be reading the same registers that are used for controlling the 32 channels of the MTG. The state of the output signal is held in a latch, so to get the current state of this signal one must first "update" the latch by reloading the same control bits that were originally used to program this channel of the MTG. In the following example assume that we are using MTG channel #15 (Function Address 14) and that we are using it to feed the BUSY Signal from the Trigger-Acquisition- Synchronization Cable to the TLM unchanged (the MTG channel is programmed with a 10). Then each time that you want to read the state of the signal being sent to the TLM do the following steps: 1). LOAD (RELOAD) A 10 INTO THE REGISTER AT FUNCTION ADDRESS 14. 2). READ FROM FUNCTION ADDRESS 14. 3). MASK THE RETURNED DATA TO EXTRACT ONLY BIT# 6 (BIT VALUE 32). 4). IF THIS BIT IS SET (HIGH) THEN THE OUTPUT FROM THIS CHANNEL OF THE MTG IS HIGH. ELSE, IF THIS BIT IS LOW THEN THE MTG OUTPUT IS LOW. The order of the Busy Signals as they leave the MTG is not the desired order for these signals at the input of the TLM. The order of these signals at the output of the MTG is the following; Specific Trigger number 1 Busy Signal is on MTG channel number 1 which is on pins 1 and 2 of the MTG output connector. At the TLM input we want Specific Trigger number 1 Busy Signal to be on pins 63 and 64 (i.e. we want reverse order). This "ordering" problem is taken care of when the signals from the output of the MTG pass through a straight pin feed through connector on their way to the TLM input.