DO FIRST LEVEL TRIGGER SYSTEM ------------------------------- TRIGGER SYSTEM CONTROL COMPUTER BUS, TIMING AND SYNCHRONIZATION BUS, SPECIFIC MOTHER BOARD BACKPLANE BUS, and SPECIFIC MOTHER BOARD FRONT CABLE BUS SPECIFICATIONS ---------------------------------------------------------- 1. Bus Locations: SPECIFIC MOTHER BOARD COMMUNICATION CONTROL FRONT APPLICATION INTERFACE CARD COMPUTER CABLE CARD BUS BUS FRONT BUS BUFFER MOTHER CONNECTOR BOARD BOARD DRIVER REAR CONNECTOR TIMING SPECIFIC MASTER TIMING AND MOTHER APPLICATION GENERATOR SYNCHRONIZATION BOARD CARD CARD BUS BACKPLANE BUS 2. All signals are positive true logic. That is, a signal is in TRUE, ACTIVE, LOGICAL 1 state when it is at the higher voltage level. A signal should be at the higher voltage level when it's non-inverted line is positive with respect to it's inverted line. 3. All signals are diferential pairs of lines on the bus. An ODD numbered pin is the non-inverted line of a signal with the next higher EVEN numbered pin the inverted line of the same signal. 4. The following is the definition of the DIRECTION SIGNAL. Logical 1 implies that the computer is going to READ Logical 0 implies that the computer is going to WRITE 5. When a Mother Board Driver Card is not selected then its output lines assume the following states: DATA, FUNCTION ADDRESS, CARD ADDRESS, and STROBE all go to a Logical 0 state. DIRECTION SIGNAL goes to a Logical 1 state. TIMING & SYNC SIGNALS all continue to pass through the Mother Board Driver Card in the normal way. 6. The STROBE Signal When the computer WRITES to the Trigger System then the logic on a Trigger System application card should latch the Data on the falling edge (trailing edge) of the STROBE signal. When the computer READS from the Trigger System the STROBE signal will remain in the Logical 0 state throughout the READ cycle. This is true for both FAST READ and SLOW READ cycles. It is suggested, but not required, that the application cards verify (require) that the STROBE signal be in the Logical 0 state when responding to a READ cycle. During all READ cycles the Communication Interface Card will read (and latch) the data on the DATA lines before (or at the time that) the address lines begin to change for the next cycle. 7. There are three major types of bus cycles: the WRITE cycle, the SLOW READ cycle, and the FAST READ cycle. The WRITE cycle is used to load all registers in the Trigger System. It is a slow cycle and has set up, strobe, and hold times that are long enough for any registers in the system. The set up, strobe, and hold times each last for 1 mircosecond or more. The SLOW READ cycle can be used to read any register in the Trigger System. It has set up, and hold times that are long enough for any register in the system. The set up, and hold times each last for 1 microsecond or more. The FAST READ is used to read the registers that are part of the First Level Trigger Data Block. All of these registers can be read with the FAST READ cycle. Not all of the registers in the system can be read with the FAST READ cycle. The FAST READ cycle time is about 200 nanoseconds. The Communication Interface Card will output valid Address, Direction, and Strobe signals for the duration of the cycle. At the end of the cycle immediately before starting to change the Address signals for the next bus cycle the Communication Interface Card will read the data on the Data lines. For all READ cycles an application card should begin to output data as soon as it receives valid Address, Direction, and (Strobe) signals and it should stop outputing data (and disable its output buffers) as soon as any of the Address, Direction, or (Strobe) signals become invalid. TIMING and SYNCHRONIZATION BUS SIGNALS -------------------------------------- 1. All signals are positive true logic. That is, a signal is in TRUE, ACTIVE, LOGICAL 1 state when it is at the higher voltage level. A signal should be at the higher voltage level when it's non-inverted line is positive with respect to it's inverted line. 2. All signal are diferential pairs of lines on the bus. An ODD numbered pin is the non-inverted line of a signal with the next higher EVEN numbered pin the inverted line of the same signal. 3. TIMING & SYNC SIGNAL NUMBER 32 - TIMING & SYNC SIGNAL number H This signal is used to turn ON all of the LED's on the Bus Buffer Boards and to turn OFF all of the LED's on the application cards in the Trigger System. This Timing & Sync Signal is carried on the following buses: Timing and Synchronization Bus as Timing & Sync Signal number 32 on cable connector pins 63 and 64. Specific Mother Board Backplane Bus as Timing & Sync Signal number H on backplane connector pins 89 and 90. Specific Mother Board Front Cable Bus as Timing & Sync Signal number H on cable connector pins 49 and 50. On the Mother Board Driver Card the Timing and Synchronization Bus Timing Sync Signal number 32 is INVERTED and then sent out on the Specific Mother Board Backplane Bus Timing & Sync Signal number H and on the Specific Mother Board Front Cable Bus Timing & Sync Signal number H. Because this Timing & Sync Signal is inverted on the Mother Board Driver Card it has a different definition on the Specific Mother Board Buses than on the Timing and Synchronization Bus. When programming the First Level Trigger Control Computer or examining the Timing and Synchronization Bus use the following definition: Timing & Sync Signal number 32 Logical 0 => all LED's on the application cards are forced OFF and all LED's on the Bus Buffer Boards are forced ON. Timing & Sync Signal number 32 Logical 1 => all LED's work normally When examining the Specific Mother Board Buses or designing (or examining) an application card then use the following definition: Timing & Sync Signal number H Logical 0 => all LED's work normally Timing & Sync Signal number H Logical 1 => all LED's on the application cards are forced OFF. 27-FEB-1986