D0 FIRST LEVEL TRIGGER SYSTEM COMMUNICATION INTERFACE TO THE CONTROL COMPUTER Michigan State University - January 1986 Revised - December 1989 add connections for rev B with ECO 18-JUN-1992: Explain Clear Most Recent (SG) 5-JUN-1995: Power consumption GENERAL : ======= The Communication Interface Card performs three different functions : - The PROGRAMMING INTERFACE Function. The Communication Interface Card allows the First Level Trigger Control Computer to write and read back any programmable register of the First Level Trigger System. - The DATA BLOCK BUILDER Function. After a Level One Trigger decision or after a Start Data Block Command from the Control Computer, the Communication Interface Card quickly (less than a millisecond) reads a fixed set of registers of the First Level Trigger System. The block of data built from the content of these registers is called the First Level Trigger Data Block. The Communication Interface Card sends the Data Block to the VMX Driver Card which will write every word of the Data Block in a dual port VME/VMX memory module (MVME214) using the VMX bus. The Data Block may be aborted in case of a negative level 1.5 decision but a successfull Data Block is recorded all at once, in a single Data Block Cycle. It will be read from the Dual Port Memory Card by the Dual Outout Buffer Card using the VME bus. The Data Cable Sequencer and the Communication Interface exchange synchronization signals in order to synchronize the reading and writting of the Dual Port VME Memory. - The DATA BLOCK SPY Function. The Data Block Spy Function allows the Control Computer to access upon request a copy of a Data Block. The Data Block Spy records a whole Data Block while it is being built whithout disturbing the Data Block Builder and does not affect the Data Block Cycle time. The copy of the Data Block recorded can be slowly read by the control computer via the DRV11J card. ENVIRONMENT : =========== The Communication Interface is connected to : - The First Level Trigger Control Computer via a DRV11-J Card. The First Level Trigger Communication Interface links the First Level Trigger Control Bus to a Digital Equipment DRV11-J Card which is used as a parallel input/output interface to the MicroVAX First Level Trigger Control Computer. The DRV11-J Card provides 64 TTL input/output data lines to communicate with a Q-bus. The First Level Trigger Communication Interface is connected to the DRV11-J card via two 50 wire flat cables plugged into J3 and J4. - A VME Dual Port Memory Module via the VMX Driver Card. The First Level Trigger Communication Interface also connects the First Level Trigger Control Bus to the VMX Driver Card. This VMX Driver Card resides in a VME crate which is part of the Data Acquisition System. It multiplexes data and addresses sent by the Communication Interface in order to match the VMX specifications and record the Data block into the Dual Port VME Memory Module via the VMX bus. The Dual Port VME Memory Module will then be read by the Dual Vme Output Buffer via the VME Bus. - The First Level Trigger System via the two Control Buses CBUS1 and CBUS2. The First Level Trigger Control Computer Bus is the unique means of communication to program or read the First Level Trigger System. It is split into two 32 pair twisted flat cable. They are called First Level Trigger Control Computer Bus Cable CBUS1 and CBUS2. Each one of these two cables distributes the bus to one half of the Trigger System. In each rack of the Trigger System the Control Computer Bus is received by the Bus Buffer Card of the rack. Each signal is driven on a differential ECL line. The Communication Interface Card provides the pairs of 56 Ohm termination resistors connected to -2V. Both cables of the Control Computer Bus need to be terminated by 110 Ohm resistors across each differential pair. The Communication Interface also receives from the Trigger System one of the 8 Start Digitizing Cables and the Timing and Synchronization Bus distributed by the Master Timing Generator Card. FIRST LEVEL TRIGGER CONTROL BUS ARBITRATION : =========================================== In general, the Control Computer Bus is left available for the Data Block Builder to immediately answer a request for a new Data Block. But any time the Control Computer needs to use the bus, it may generate a Bus Control Request to the Data Block Builder Function. When such a request is received, the Data Block Builder will disable itself from sending a new Data Block, but will always complete a current Data Block Cycle in progress. The Control Computer has no way to stop the completion of a Data Block Cycle. During a programming sequence, the Control Bus Cables CBUS1 and CBUS2 are alternatively used. The Control Computer selects one function at a time and uses only the cable serving this function. During a Data Block Cycle, the two cables are utilized in parallel. The Data Block Builder synchronously drives the two cables and simultaneously sends two different addresses on the cables. Two different registers in the Trigger System are addressed at the same time. Whenever any one of the two cables is unused, every line on the cable except the direction line is maintained in a low differential ECL state. This default state selects : - The Mother-Board Address 0. - The Card Address 0. - The Function Address 0. - The Read Direction. - A low (inactive) Strobe Signal. THE FIRST LEVEL TRIGGER DATA BLOCK : ================================== The Data Block is a fixed format 8 kbyte block of data. The Data Block Builder reads a fixed sequence of registers in the Trigger System and copy the content of these registers inthe VME memory module. A new Data Block Cycle is started when a Start Digitization Command is generated by the First Level Trigger System on the Trigger-Acquisition Synchronization Cable allocated to the Data Block Builder. When the Data Block Builder finishes its cycle it sends a Data Block Completed Signal to the Dual VME Output Buffer. When a new Data Block Cycle is initiated two different addresses are generated on the board from two sets of PROMs and sent in parallel on both First Level Trigger Control Buses. The Communication Interface assumes that each cable receives the 8 bits of data corresponding to the contents of the addressed registers within 200 nanoseconds. Every 16 bit word obtained by concatenating the two bytes of data is latched and sent to the Dual Port VME Memory module while two new addresses are sent on the cables. Building the 4k x 16 bit word Data Block takes approximately 800 microseconds for an internal cycle time of 200 nanoseconds. When the Data Block Spy Function is activated by the Control Computer, the data are also simultaneously written into an on board RAM. A Spy Next Data Block Command will activate the Data Block Spy Function for only one complete Data Block. A request occurring during a Data Block Builder Cycle will be memorised and the record will automatically be synchronized with the beginning of the next Data Block Cycle. If a Data Block being recorded by the Data Block Spy is aborted before completion the Data Block Spy will automatically reset and enable itself for the next cycle untill it has been abble to record a full Data Block. The Data Block Builder looks to the First Level Trigger exactly as any other Detector System. And receives its own Trigger-Acquisition Synchronization Cable. The First Level Trigger Data Block Builder does not require a special type of Dual VME Output Buffer. The Data Block Builder looks to the Data Cable #0 Sequencer exactely as any other Detector System (except that only one device is connected to this Data Sequencer). TESTING THE FIRST LEVEL TRIGGER SYSTEM ====================================== For testing purpose, the Control Computer can initiate a new Data Block Cycle. This Start New Data Block Command is sent through the DRV11-J card directely to the Data Block Builder. This command does not require the Control Computer Bus. A Data Block Cycle already in progress will not be affected. When such a request occurs during a Data Block Cycle the request will be memorised in the same way as an external Start Digitizing Command, and the Front-End Busy Signal will be asserted. In the case of a Data Block Cycle initiated by the Control Computer it is important to note that the rest of the Acquisition System did not receive any Specific Trigger Fired Signal or Any Start Digitizing Command from the Trigger Framework but that it will receive a Data Block Completed Signal from the Communicataion Interface Card. The Control Computer can also stop the communication of any data to the Dual Port VME Memory Module. When the Disable Data Block Sendout Signal is active, the 16 data lines, the 12 address lines and the accompanying clock signal going to the VME memory module are left in a high impedance electrical state. However, a Data Block Completed Signal will be sent to the Dual VME Output Buffer. The Disable Data Block Sendout Signal is not synchronized with the beginning of a Data Block and must be carefully used. At any time the Control Computer can instantaneously stop the First Level Trigger System from any further triggering by forcing the Front-End Busy Signal issued by the Data Block Builder to an asserted state. The Control Computer can stop the activity of the Data Block Builder. When the Disable Data Block Builder line is asserted, no Start Digitizing Command coming from the Trigger-Acquisition Synchronization Cable will be serviced or even memorized. The Data Block Builder will however respond to a Start New Data Block Command coming from the Communication Interface Card PROGRAMMING THE FIRST LEVEL TRIGGER SYSTEM : ========================================== Before a run the First Level Control Compter has the ability to initialize, program and test the whole Trigger System. The programming operation is slow, and the Cycle Time is chosen according to the "slowest" function to be proggrammed in the system. The registers are first written by the Control Computer via programmed I/O through the DRV11-J interface. They are then all read back and compared to their expected value. During a run the Control Computer needs sometimes to communicate with the Trigger System (e.g. upon request from the Second Level Supervisor Computer to enable an automatically disabled Specific Trigger). To become master of the Control Bus, the Control Computer first sends a Bus Control Request to the Communication Interface Card and then waits for the Control Bus Freed Signal to be asserted before starting to use the bus. The Control Computer Bus can also mask the corresponding interrupt and read the Control Bus Freed status line untill it gets asserted, and then use the Control Bus. The Data Block sendout can be delayed when the Control Computer uses the Control Bus. A Data Block Cycle takes approximately 800 microseconds. After a Level One Trigger Decision, the corresponding half of the double buffered registers is expected to be cleared within 1 millisecond. It clearly means that, during a run, the Control Computer should never use the Control Bus longer than 200 microseconds without checking that no new Data Block Cycle is waiting to be serviced. 200 microseconds should be more than sufficient for any maintenance and control sequence needed during a run. A Start Digitization Command received on the Trigger-Acquistion Cable during this period of time will always be memorised and serviced as soon as the Data Block Builder recovers the control of the bus. If one (or two) Sart Digitization Command is (are) waiting to be serviced by the Data Block Builder then the New Data Block Cycle Requested status line is in an asserted state. Of course, this time restriction does not apply when the whole Trigger System is taken down for a complete initialization or programming sequence. CONTROL AND SYNCHRONIZATION LINES : ================================= The First Level Trigger Communication Interface supports a number of control and status signals to synchronize and oversee the operation of the First Level Trigger Data Block Builder,the First Level Trigger Data Block Spy and the Programming Interface Functions. WITH THE FIRST LEVEL TRIGGER THROUGH THE TRIGGER-ACQUISITION CABLE ------------------------------------------------------------------ All the lines listed here are differential ECL lines. START DIGITIZATION COMMAND (INPUT COMMAND) After any First Level Trigger decision, the Trigger System generates a Start Digitization Command on the Trigger-Acquisition Cable allocated to the Data Block Builder. A new Data Block Cycle will be initiated by a rising edge occuring on this line. If a Data Block Cycle is still in progress, the command will be memorised to be serviced later. FRONT-END CRATE BUSY (OUTPUT STATUS) When a Start Digitizing Command occurs while the last Data Block Cycle is not completed, then both halves of the double buffered registers of the Trigger System contain data to be saved from overwriting. The Communication Interface Card will then generate a high state on the Front-End Busy line of its Trigger-Acquisition Synchronization cable. In response, the whole Trigger System is expected to stop sending any Start Digitization Command untill this line is negated. CLEAR MOST RECENT TRIGGER (INPUT COMMAND) Resulting from a negative Level 1.5 decision, the First Level Trigger System may send a Clear Most Recent Trigger Command occuring 20 microseconds after a Start Digitizing Command. In response, the Data Block Builder will abort the corresponding Data Block Cycle, reset the address counter and no Data Block Completed Signal will be sent out to the Dual VME Output Buffer. In fact, several different cases may occur. See the table below: Number Number in Waiting Process Action ------- --------- ------ 0 0 Clear both waiting requests (actually there are no waiting requests) 1 0 Clear the waiting request 2 0 Clear only one waiting request (it does not matter which one is cleared) 0 1 Clear the granted request 1 1 Clear the UNGRANTED REQUEST See the file TRGHARD:[COMINT]CLEAR_MOST_RECENT.TXT for more information about the Clear Most Recent Trigger Logic. WITH THE MASTER TIMING GENERATOR OF THE FIRST LEVEL TRIGGER SYSTEM ------------------------------------------------------------------ The lines listed here are differential ECL lines. _ A/B HALF OF THE DOUBLE BUFFER READ (OUTPUT COMMAND) When a Data Block Cycle is Completed, the Data Block Builder toggles the state of this line. The First Level Trigger Master Timing Generator will receive and copy this signal on the Timing and Synchronization Signal # 03 which synchronizes for the whole First Level Trigger System the half of the double buffered registers (Am29520's) to be read during the next Data Block Cycle. _ A/B HALF OF THE DOUBLE BUFFER WRITTEN (OUTPUT COMMAND) The COMINT card passes both the Start Digitization and the Clear Most Recent Trigger signals to the First Level Trigger Master Timing Generator. The MTG toggles the state of the TSS #05 (Write A/B) upon receipt of either of these signals. WITH THE DRV11-J AS AN OUTPUT INTERFACE TO THE CONTROL COMPUTER --------------------------------------------------------------- All the lines listed here are open TTL lines. START NEW DATA BLOCK (INPUT COMMAND) This command will start a new Data Block Cycle. It will be memorized if a cycle is already in progress. Since no Start Digitization is simultaneously sent to the rest of the acquisition system it should only be used for testing purpose. BUS CONTROL REQUEST (INPUT COMMAND) When the First Level Control Computer needs the First Level Trigger Control Bus, it first generates a low level on the Bus Control Request Command line. This Command will never interrrupt a Data Block Cycle in progress but will disable the Data Block Builder from begining a new cycle. The Control Computer should then wait for a Control Bus Freed Interrupt command or for the Control Bus Freed Status line to be asserted before using the Control Bus. In a normal configuration, the Control Computer should not use the Control Bus longer than 200 microseconds. Furthermore, the Control Computer must always assert the Bus Control Request line once it stops using the Control Bus. DISABLE DATA BLOCK SENDOUT (INPUT COMMAND) This command stops the communication with the Dual Port VME Memory Module. The 12 address lines, 16 data lines and the clock signal are left in a high impedance state. A Data Block Completed Signal will still be sent to the Dual VME Output Buffer. This command is not synchronized with the begining of a Data Block Cycle and all precautions must be taken if one want to use it during the normal functionment of the First Level Trigger System. SPY NEXT DATA BLOCK (INPUT COMMAND) If the First Level Control Computer wants a copy of a Data Block it should first assert the Spy Next Data Block line. A Data Block Cycle already in progress will not be affected nor be recorded. But during the next Data Block Cycle the collected datas will be recorded on an on-board RAM without disturbing the progress of the normal cycle. Only one Data Block will be recorded in response to a raising edge occuring on this line. In case of a negative level 1.5 trigger decision, the Data Block Spy will stay active in order to record the next Data Block. Only a successfull Data Block Cycle will generate a Data Block Spy Full Signal. READING DATA BLOCK SPY (INPUT COMMAND) The control Computer must assert the Read Data Block Spy line before beginning to read the on-board RAM. This line must stay in a high state during the reading period. A transition from a high to a low state on this line will reset the address counter driving the RAM, it will also clear the Data Block Spy Full line. The Data Block Spy Function will then be ready to service any new Spy Next Data Block Command or to be read again starting at address zero. It is not required from the Control Computer to read the whole copy of the Data Block. If for any reason the Control Computer does not read the requested Data Block it must at least send a pulse on the Read Data Block Spy line before any new Data Block can be further recorded. TOGGLE HALF DOUBLE BUFFER READ (INPUT COMMAND) During an initialization sequence, the Control Computer checks that the half of the double buffer ready to be read by the Data Block Builder matches the half ready to be written in the Trigger System. The rising edge of a pulse occuring on this line will toggle the half that will be read next. DISABLE FURTHER TRIGGER (INPUT COMMAND) A high level on this line forces the Front-End Busy signal in a high state. It will prohibit any further First Level Trigger decision. ENABLE DATA BLOCK BUILDER (INPUT COMMAND) A low level on this line will stop any Start Digitizing Command arriving to the Data Block Builder. The Data Block Builder will not even memorise the Start Digitizing Command and will not send any Data Block Completed Signal nor any Front-End Busy Signal. INITIALIZE & INITIALIZE BAR (INPUT INITIALIZATION COMMANDS) When the Initialize line is asserted and the Initialize Bar line is negated the Communication Interface Card is forced to a known state. All Start Data Block and Spy Data Block requests are cleared. The Data Block Spy Full and Data Block Requested are cleared. The A/B Half Double Buffer Read is forced low. WITH THE DRV11-J AS AN INPUT INTERFACE TO THE CONTROL COMPUTER -------------------------------------------------------------- All the lines listed here are open TTL lines. DATA BLOCK BUILDER BUSY (OUTPUT STATUS) This line is asserted during every Data Block Cycle. DOUBLE BUFFER FULL (OUTPUT STATUS) This line is asserted if two Start Digitization Commands are waiting to be serviced or if a Data Block Cycle is in progress and one other Start Digitization Command is waiting to be serviced. It duplicates the Front-End Busy Signal sent to the First Level Trigger System when the Disable Further Trigger line is not asserted. DATA BLOCK SPY FULL (OUTPUT STATUS AND INTERRUPT COMMAND) When a Data Block has been recorded by the Data Block Spy, this line is asserted and will be negated when the Control Computer negates the Read Data Block line or when the spy-RAM address counter reaches 4096 during a Read Data Block Spy sequence. CONTROL BUS FREED (OUTPUT STATUS AND INTERRUPT COMMAND) This line is asserted after the Control Computer asserts the Bus Control Request line and as soon as the Data Block Builder Busy line is negated. It generates an interrupt on the Control Computer through the User Ready A line of the DRV11-J Card. HALF DOUBLE BUFFER READ (OUTPUT STATUS) This line duplicates the state of the Timing and Synchronization Signal # 03. This signal selects for the whole Trigger System which half of the double buffered registers is ready to be read by the Data Block Builder. HALF DOUBLE BUFFER WRITTEN (OUTPUT STATUS) This line duplicates the state of the Timing and Synchronization Signal # 05. This signal selects for the whole Trigger System which half of the double buffered registers is ready to be written during the next beam crossing for which the Trigger is enabled. TIMING & SYNCHRONIZATION SIGNAL #06 (OUTPUT STATUS) This line duplicates the state of the Timing and Synchronization Signal #06 SO FAR NOT ALLOCATED. NEW DATA BLOCK CYCLE REQUESTED (OUTPUT STATUS) If one (or two) Sart Digitization Command is waiting to be serviced by the Data Block Builder then the New Data Block Cycle Requested status line is in an asserted state. BUFFER OVERWRITING ERROR (INTERRUPT COMMAND) An overwriting error is detected when at the same time: the Data Block Builder Function is active, the half of the double buffered registers read is also the one enabled to be written to and a write signal is sent to the double buffered registers. if these conditions are met, a rising edge will be generated on this line and will interrupt the Control Computer signaling that the registers currently read by the DAta Block Builder are overwritten. The Control Computer will then notify the Host and eventualy resynchronize the First Level Trigger System and send error messages to the host and/or to the Second Level Supervisor. WITH THE DUAL VME OUTPUT BUFFER ------------------------------- All the lines listed here are differential ECL. DATA BLOCK COMPLETED (OUTPUT STATUS) The Data Block Builder generates a pulse on this line at the end of every Data Block Cycle. This pulse gives the start signal to the Dual VME Output Buffer which should then read the Dual Port VME Module. MEMORY MODULE AVAILABLE (INPUT STATUS) The Dual VME Output Buffer negates this line in response to a Data Block completed pulse issued by the Communication Card and keeps it low while it reads the Dual Port VME Module. The Data Block Builder will try to overwrite the Dual Port VME module untill this line is asserted to a low state. WITH THE DUAL PORT VME MODULE THROUGH THE OUTPUT BUFFER ------------------------------------------------------- All the lines listed here are single ended TTL. They may be disabled (high impedance state) by the Control Computer with a Disable Data Block Send out Command. DATA BLOCK BUILDER ADDRESS 1 TO 12 The 12 bits of address are valid on these lines 30 nanoseconds after every rising edge occuring on the Clock line. DATA BLOCK BUILDER DATA 1 TO 16 The 16 bits of data are valid on these lines 30 nanoseconds after every rising edge occuring on the Clock line. DATA BLOCK BUILDER INACTIVE This line is negated during every Data Block Cycle. CLOCK This line remains in a high state when the data block builder is not active. A rising edge on the Clock line occurs 30 nanoseconds before a new address and a new data are presented. CYCLE DIAGRAMS : ============== oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo PROGRAMMING SEQUENCE -------------------- CONTROL COMPUTER COMMUNICATION VIA DRV11-J CARD INTERFACE ------- ------- - Asserts CONTROL BUS REQUEST. - Completes a current Data Block Cycle. - Asserts CONTROL BUS FREED (INTERRUPT). - Waits and does not begin any new Data Block Cycle. - Uses the Control Bus to talk to the Trigger System. - Negates CONTROL BUS REQUEST when through. - Resumes its activity and answers a START DIGITIZING COMMAND waiting to be serviced. oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo DATA BLOCK BUILDING CYCLE ------------------------- FIRST LEVEL COMMUNICATION DUAL VME TRIGGER SYSTEM INTERFACE OUTPUT BUFFER ------ ----- ------ - Sends a pulse on the START DIGITIZING line. - Memorises the command. - Asserts FRONT-END BUSY if a Data Block Cycle is already in progress. - As soon as DATA BLOCK BUILDER BUSY BUS CONTROL REQUEST MEMORY MODULE BUSY are negated, asserts DATA BLOCK BUILDER BUSY. - Sends the first addresses on the address lines of both Control Bus Cables. - 200 nanoseconds later latches the data on the data lines of both Control Bus Cables and sends the next addresses. - Sends the 16 bits of data with the corresponding address and a STROBE signal to the Dual Port VME Memory Module. - Repeats the last two operations for the 4-kword of data. - When the whole Data Block has been sent to the memory module, clears the memorised Start Digitizing Command. - Negates FRONT-END BUSY if it was previously asserted. - Sends a pulse on the DATA BLOCK COMPLETED line to the Dual VME Output Buffer. - Receives the DATA BLOCK COMPLETED signal. - Asserts MEMORY MODULE BUSY. - Transfers the Data Block from the Dual Port VME Module to one of its output buffers. - Negates MEMORY MODULE BUSY. oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo DATA BLOCK SPY CYCLE -------------------- CONTROL COMPUTER COMMUNICATION VIA THE DRV11-J INTERFACE ----- ---- - Asserts SPY NEXT DATA BLOCK. - Completes a Ddata Block Cycle. - Enables the Data Block Spy for recording the next Data Block. - Records word by word the whole Data Block. - disables itself from recording an other Data Block. - Generates DATA BLOCK SPY FULL INTERRUPT. - Negates SPY NEXT DATA BLOCK. - Asserts READING DATA BLOCK SPY. - Re-enables its Data Block Spy Function. - Reads the first word of the Data Block recorded on port B. - Increments the counter generating the addresses on the RAM. - repeats this operation for the whole Data Block or Stops in the middle or does not even read a word. - Negates READING DATA BLOCK SPY. - Resets the counter generating the addresses on the RAM. - The Data Block Spy is ready to service a new SPY NEXT DATA BLOCK. J1: 140 PIN CONNECTOR ------------------------------------------------------------------------------ Plug & Pin Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 brown Mother-Board Address Bit#1 Non-inverted CBUS1 1 NMBA1 4 tan Mother-Board Address Bit#1 inverted CBUS1 2 IMBA1 5 red Mother-Board Address Bit#2 Non-inverted CBUS1 3 NMBA2 6 tan Mother-Board Address Bit#2 inverted CBUS1 4 IMBA2 7 orange Mother-Board Address Bit#3 Non-inverted CBUS1 5 IMBA2 8 tan Mother-Board Address Bit#3 inverted CBUS1 6 IMBA3 9 yellow Mother-Board Address Bit#4 Non-inverted CBUS1 7 NMBA4 10 tan Mother-Board Address Bit#4 inverted CBUS1 8 IMBA4 11 green Mother-Board Address Bit#5 Non-inverted CBUS1 9 NMBA5 12 tan Mother-Board Address Bit#5 inverted CBUS1 10 IMBA5 13 blue Mother-Board Address Bit#6 Non-inverted CBUS1 11 NMBA6 14 tan Mother-Board Address Bit#6 inverted CBUS1 12 IMBA6 15 violet Mother-Board Address Bit#7 Non-inverted CBUS1 13 NMBA7 16 tan Mother-Board Address Bit#7 inverted CBUS1 14 IMBA7 17 grey Mother-Board Address Bit#8 Non-inverted CBUS1 15 NMBA8 18 tan Mother-Board Address Bit#8 inverted CBUS1 16 IMBA8 19 white Card Address Bit#1 Non-inverted CBUS1 17 NCA1 20 tan Card Address Bit#1 inverted CBUS1 18 ICA1 21 black Card Address Bit#2 Non-inverted CBUS1 19 NCA2 22 tan Card Address Bit#2 inverted CBUS1 20 ICA2 23 brown Card Address Bit#3 Non-inverted CBUS1 21 NCA3 24 tan Card Address Bit#3 inverted CBUS1 22 ICA3 25 red Card Address Bit#4 Non-inverted CBUS1 23 NCA4 26 tan Card Address Bit#4 inverted CBUS1 24 ICA4 27 orange Card Address Bit#5 Non-inverted CBUS1 25 NCA5 28 tan Card Address Bit#5 inverted CBUS1 26 ICA5 29 yellow Card Address Bit#6 Non-inverted CBUS1 27 NCA6 30 tan Card Address Bit#6 inverted CBUS1 28 ICA6 31 green Function Address Bit#1 Non-inverted CBUS1 29 NFA1 32 tan Function Address Bit#1 inverted CBUS1 30 IFA1 33 blue Function Address Bit#2 Non-inverted CBUS1 31 NFA2 34 tan Function Address Bit#2 inverted CBUS1 32 IFA2 35 violet Function Address Bit#3 Non-inverted CBUS1 33 NFA3 36 tan Function Address Bit#3 inverted CBUS1 34 IFA3 37 grey Function Address Bit#4 Non-inverted CBUS1 35 NFA4 38 tan Function Address Bit#4 inverted CBUS1 36 IFA4 39 white Function Address Bit#5 Non-inverted CBUS1 37 NFA5 40 tan Function Address Bit#5 inverted CBUS1 38 IFA5 41 black Function Address Bit#6 Non-inverted CBUS1 39 NFA6 42 tan Function Address Bit#6 inverted CBUS1 40 IFA6 43 brown Function Address Bit#7 Non-inverted CBUS1 41 NFA7 44 tan Function Address Bit#7 inverted CBUS1 42 IFA7 45 red Function Address Bit#8 Non-inverted CBUS1 43 NFA8 46 tan Function Address Bit#8 inverted CBUS1 44 IFA8 47 orange Strobe Non-inverted CBUS1 45 NSTB 48 tan Strobe inverted CBUS1 46 ISTB 49 yellow Direction Non-inverted CBUS1 47 NDIR 50 tan Direction inverted CBUS1 48 IDIR 51 green Bidirectional Data Bit#1 Non-inverted CBUS1 49 NDB1 52 tan Bidirectional Data Bit#1 inverted CBUS1 50 IDB1 53 blue Bidirectional Data Bit#2 Non-inverted CBUS1 51 NDB2 54 tan Bidirectional Data Bit#2 inverted CBUS1 52 IDB2 55 violet Bidirectional Data Bit#3 Non-inverted CBUS1 53 NDB3 56 tan Bidirectional Data Bit#3 inverted CBUS1 54 IDB3 57 grey Bidirectional Data Bit#4 Non-inverted CBUS1 55 NDB4 58 tan Bidirectional Data Bit#4 inverted CBUS1 56 IDB4 59 white Bidirectional Data Bit#5 Non-inverted CBUS1 57 NDB5 60 tan Bidirectional Data Bit#5 inverted CBUS1 58 IDB5 61 black Bidirectional Data Bit#6 Non-inverted CBUS1 59 NDB6 62 tan Bidirectional Data Bit#6 inverted CBUS1 60 IDB6 63 brown Bidirectional Data Bit#7 Non-inverted CBUS1 61 NDB7 64 tan Bidirectional Data Bit#7 inverted CBUS1 62 IDB7 65 red Bidirectional Data Bit#8 Non-inverted CBUS1 63 NDB8 66 tan Bidirectional Data Bit#8 inverted CBUS1 64 IDB8 67 Ground GND 68 Ground GND 69 Power +5.0 V 70 Power +5.0 V 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown Timing & Sync. Signal Bit#1 Non-Inverted 1 NTS1 76 tan Timing & Sync. Signal Bit#1 Inverted 2 ITS1 77 red Timing & Sync. Signal Bit#2 Non-Inverted 3 NTS2 78 tan Timing & Sync. Signal Bit#2 Inverted 4 ITS2 79 orange Timing & Sync. Signal Bit#3 Non-Inverted 5 NTS3 80 tan Timing & Sync. Signal Bit#3 Inverted 6 ITS3 81 yellow Timing & Sync. Signal Bit#4 Non-Inverted 7 NTS4 82 tan Timing & Sync. Signal Bit#4 Inverted 8 ITS4 83 green Timing & Sync. Signal Bit#5 Non-Inverted 9 NTS5 84 tan Timing & Sync. Signal Bit#5 Inverted 10 ITS5 85 blue Timing & Sync. Signal Bit#6 Non-Inverted 11 NTS6 86 tan Timing & Sync. Signal Bit#6 Inverted 12 ITS6 87 violet Timing & Sync. Signal Bit#7 Non-Inverted 13 NTS7 88 tan Timing & Sync. Signal Bit#7 Inverted 14 ITS7 89 grey Timing & Sync. Signal Bit#8 Non-Inverted 15 NTS8 90 tan Timing & Sync. Signal Bit#8 Inverted 16 ITS8 91 white Timing & Sync. Signal Bit#9 Non-Inverted 17 NTS9 92 tan Timing & Sync. Signal Bit#9 Inverted 18 ITS9 93 black Timing & Sync. Signal Bit#10 Non-Inverted 19 NTS10 94 tan Timing & Sync. Signal Bit#10 Inverted 20 ITS10 95 brown Timing & Sync. Signal Bit#11 Non-Inverted 21 NTS11 96 tan Timing & Sync. Signal Bit#11 Inverted 22 ITS11 97 red Timing & Sync. Signal Bit#12 Non-Inverted 23 NTS12 98 tan Timing & Sync. Signal Bit#12 Inverted 24 ITS12 99 orange Timing & Sync. Signal Bit#13 Non-Inverted 25 NTS13 100 tan Timing & Sync. Signal Bit#13 Inverted 26 ITS13 101 yellow Timing & Sync. Signal Bit#14 Non-Inverted 27 NTS14 102 tan Timing & Sync. Signal Bit#14 Inverted 28 ITS14 103 green Timing & Sync. Signal Bit#15 Non-Inverted 29 NTS15 104 tan Timing & Sync. Signal Bit#15 Inverted 30 ITS15 105 blue Timing & Sync. Signal Bit#16 Non-Inverted 31 NTS16 106 tan Timing & Sync. Signal Bit#16 Inverted 32 ITS16 107 violet Timing & Sync. Signal Bit#17 Non-Inverted 33 NTS17 108 tan Timing & Sync. Signal Bit#17 Inverted 34 ITS17 109 grey Timing & Sync. Signal Bit#18 Non-Inverted 35 NTS18 110 tan Timing & Sync. Signal Bit#18 Inverted 36 ITS18 111 white Timing & Sync. Signal Bit#19 Non-Inverted 37 NTS19 112 tan Timing & Sync. Signal Bit#19 Inverted 38 ITS19 113 black Timing & Sync. Signal Bit#20 Non-Inverted 39 NTS20 114 tan Timing & Sync. Signal Bit#20 Inverted 40 ITS20 115 brown Timing & Sync. Signal Bit#21 Non-Inverted 41 NTS21 116 tan Timing & Sync. Signal Bit#21 Inverted 42 ITS21 117 red Timing & Sync. Signal Bit#22 Non-Inverted 43 NTS22 118 tan Timing & Sync. Signal Bit#22 Inverted 44 ITS22 119 orange Timing & Sync. Signal Bit#23 Non-Inverted 45 NTS23 120 tan Timing & Sync. Signal Bit#23 Inverted 46 ITS23 121 yellow Timing & Sync. Signal Bit#24 Non-Inverted 47 NTS24 122 tan Timing & Sync. Signal Bit#24 Inverted 48 ITS24 123 green Timing & Sync. Signal Bit#25 Non-Inverted 49 NTS25 124 tan Timing & Sync. Signal Bit#25 Inverted 50 ITS25 125 blue Timing & Sync. Signal Bit#26 Non-Inverted 51 NTS26 126 tan Timing & Sync. Signal Bit#26 Inverted 52 ITS26 127 violet Timing & Sync. Signal Bit#27 Non-Inverted 53 NTS27 128 tan Timing & Sync. Signal Bit#27 Inverted 54 ITS27 129 grey Timing & Sync. Signal Bit#28 Non-Inverted 55 NTS28 130 tan Timing & Sync. Signal Bit#28 Inverted 56 ITS28 131 white Timing & Sync. Signal Bit#29 Non-Inverted 57 NTS29 132 tan Timing & Sync. Signal Bit#29 Inverted 58 ITS29 133 black Timing & Sync. Signal Bit#30 Non-Inverted 59 NTS30 134 tan Timing & Sync. Signal Bit#30 Inverted 60 ITS30 135 brown Timing & Sync. Signal Bit#31 Non-Inverted 61 NTS31 136 tan Timing & Sync. Signal Bit#31 Inverted 62 ITS31 137 red Led Display Control Non-Inverted 63 NLDC 138 tan Led Display Control Inverted 64 ILDC 139 Ground GND 140 Ground GND J2 : FIRST LEVEL TRIGGER TIMING AND SYNCHRONIZATION BUS AND TRIGGER-ACQUISITION SYNCHRONIZATION LINK 140 PIN CONNECTOR ------------------------------------------------------------------------------ Pin Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 brown Mother-Board Address Bit#1 Non-inverted CBUS2 1 NMBA1 4 tan Mother-Board Address Bit#1 inverted CBUS2 2 IMBA1 5 red Mother-Board Address Bit#2 Non-inverted CBUS2 3 NMBA2 6 tan Mother-Board Address Bit#2 inverted CBUS2 4 IMBA2 7 orange Mother-Board Address Bit#3 Non-inverted CBUS2 5 IMBA2 8 tan Mother-Board Address Bit#3 inverted CBUS2 6 IMBA3 9 yellow Mother-Board Address Bit#4 Non-inverted CBUS2 7 NMBA4 10 tan Mother-Board Address Bit#4 inverted CBUS2 8 IMBA4 11 green Mother-Board Address Bit#5 Non-inverted CBUS2 9 NMBA5 12 tan Mother-Board Address Bit#5 inverted CBUS2 10 IMBA5 13 blue Mother-Board Address Bit#6 Non-inverted CBUS2 11 NMBA6 14 tan Mother-Board Address Bit#6 inverted CBUS2 12 IMBA6 15 violet Mother-Board Address Bit#7 Non-inverted CBUS2 13 NMBA7 16 tan Mother-Board Address Bit#7 inverted CBUS2 14 IMBA7 17 grey Mother-Board Address Bit#8 Non-inverted CBUS2 15 NMBA8 18 tan Mother-Board Address Bit#8 inverted CBUS2 16 IMBA8 19 white Card Address Bit#1 Non-inverted CBUS2 17 NCA1 20 tan Card Address Bit#1 inverted CBUS2 18 ICA1 21 black Card Address Bit#2 Non-inverted CBUS2 19 NCA2 22 tan Card Address Bit#2 inverted CBUS2 20 ICA2 23 brown Card Address Bit#3 Non-inverted CBUS2 21 NCA3 24 tan Card Address Bit#3 inverted CBUS2 22 ICA3 25 red Card Address Bit#4 Non-inverted CBUS2 23 NCA4 26 tan Card Address Bit#4 inverted CBUS2 24 ICA4 27 orange Card Address Bit#5 Non-inverted CBUS2 25 NCA5 28 tan Card Address Bit#5 inverted CBUS2 26 ICA5 29 yellow Card Address Bit#6 Non-inverted CBUS2 27 NCA6 30 tan Card Address Bit#6 inverted CBUS2 28 ICA6 31 green Function Address Bit#1 Non-inverted CBUS2 29 NFA1 32 tan Function Address Bit#1 inverted CBUS2 30 IFA1 33 blue Function Address Bit#2 Non-inverted CBUS2 31 NFA2 34 tan Function Address Bit#2 inverted CBUS2 32 IFA2 35 violet Function Address Bit#3 Non-inverted CBUS2 33 NFA3 36 tan Function Address Bit#3 inverted CBUS2 34 IFA3 37 grey Function Address Bit#4 Non-inverted CBUS2 35 NFA4 38 tan Function Address Bit#4 inverted CBUS2 36 IFA4 39 white Function Address Bit#5 Non-inverted CBUS2 37 NFA5 40 tan Function Address Bit#5 inverted CBUS2 38 IFA5 41 black Function Address Bit#6 Non-inverted CBUS2 39 NFA6 42 tan Function Address Bit#6 inverted CBUS2 40 IFA6 43 brown Function Address Bit#7 Non-inverted CBUS2 41 NFA7 44 tan Function Address Bit#7 inverted CBUS2 42 IFA7 45 red Function Address Bit#8 Non-inverted CBUS2 43 NFA8 46 tan Function Address Bit#8 inverted CBUS2 44 IFA8 47 orange Strobe Non-inverted CBUS2 45 NSTB 48 tan Strobe inverted CBUS2 46 ISTB 49 yellow Direction Non-inverted CBUS2 47 NDIR 50 tan Direction inverted CBUS2 48 IDIR 51 green Bidirectional Data Bit#1 Non-inverted CBUS2 49 NDB1 52 tan Bidirectional Data Bit#1 inverted CBUS2 50 IDB1 53 blue Bidirectional Data Bit#2 Non-inverted CBUS2 51 NDB2 54 tan Bidirectional Data Bit#2 inverted CBUS2 52 IDB2 55 violet Bidirectional Data Bit#3 Non-inverted CBUS2 53 NDB3 56 tan Bidirectional Data Bit#3 inverted CBUS2 54 IDB3 57 grey Bidirectional Data Bit#4 Non-inverted CBUS2 55 NDB4 58 tan Bidirectional Data Bit#4 inverted CBUS2 56 IDB4 59 white Bidirectional Data Bit#5 Non-inverted CBUS2 57 NDB5 60 tan Bidirectional Data Bit#5 inverted CBUS2 58 IDB5 61 black Bidirectional Data Bit#6 Non-inverted CBUS2 59 NDB6 62 tan Bidirectional Data Bit#6 inverted CBUS2 60 IDB6 63 brown Bidirectional Data Bit#7 Non-inverted CBUS2 61 NDB7 64 tan Bidirectional Data Bit#7 inverted CBUS2 62 IDB7 65 red Bidirectional Data Bit#8 Non-inverted CBUS2 63 NDB8 66 tan Bidirectional Data Bit#8 inverted CBUS2 64 IDB8 67 Ground GND 68 Ground GND 69 Power +5.0 V 70 Power +5.0 V 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown Beam crossing number Bit#0 Non-Inverted 1 NBCN0 76 tan Beam crossing number Bit#0 Inverted 2 NBCN0 77 red Beam crossing number Bit#1 Non-Inverted 3 NBCN1 78 tan Beam crossing number Bit#1 Inverted 4 NBCN1 79 orange Beam crossing number Bit#2 Non-Inverted 5 NBCN2 80 tan Beam crossing number Bit#2 Inverted 6 NBCN2 81 yellow Beam crossing number Bit#3 Non-Inverted 7 NBCN3 82 tan Beam crossing number Bit#3 Inverted 8 NBCN3 83 green Beam crossing number Bit#4 Non-Inverted 9 NBCN4 84 tan Beam crossing number Bit#4 Inverted 10 NBCN4 85 blue Beam crossing number Bit#5 Non-Inverted 11 NBCN5 86 tan Beam crossing number Bit#5 Inverted 12 NBCN5 87 violet Beam crossing number Bit#6 Non-Inverted 13 NBCN6 88 tan Beam crossing number Bit#6 Inverted 14 NBCN6 89 grey Beam crossing number Bit#7 Non-Inverted 15 NBCN7 90 tan Beam crossing number Bit#7 Inverted 16 NBCN7 91 white Beam crossing number Bit#8 Non-Inverted 17 NBCN8 92 tan Beam crossing number Bit#8 Inverted 18 NBCN8 93 black Beam crossing number Bit#9 Non-Inverted 19 NBCN9 94 tan Beam crossing number Bit#9 Inverted 20 NBCN9 95 brown Beam crossing number Bit#10 Non-Inverted 21 NBCN10 96 tan Beam crossing number Bit#10 Inverted 22 NBCN10 97 red Beam crossing number Bit#11 Non-Inverted 23 NBCN11 98 tan Beam crossing number Bit#11 Inverted 24 NBCN11 99 orange Beam crossing number Bit#12 Non-Inverted 25 NBCN12 100 tan Beam crossing number Bit#12 Inverted 26 NBCN12 101 yellow Beam crossing number Bit#13 Non-Inverted 27 NBCN13 102 tan Beam crossing number Bit#13 Inverted 28 NBCN13 103 green Beam crossing number Bit#14 Non-Inverted 29 NBCN14 104 tan Beam crossing number Bit#14 Inverted 30 NBCN14 105 blue Beam crossing number Bit#15 Non-Inverted 31 NBCN15 106 tan Beam crossing number Bit#15 Inverted 32 NBCN15 107 violet Start Digitization Command Non-Inverted 33 NSDGC 108 tan Start Digitization Command Inverted 34 ISDGC 109 grey Front-End Crate Busy Non-Inverted 35 NFECB 110 tan Front-End Crate Busy Inverted 36 IFECB 111 white Clear Most Recent Trigger Non-Inverted 37 NCLRT 112 tan Clear Most Recent Trigger Inverted 38 ICLRT 113 black Grounded 114 tan Grounded 115 brown 116 tan 117 red 118 tan _ 119 orange Read Double Buffer Half A / B Non-Inverted 120 tan Read Double Buffer Half A / B Inverted 121 yellow 122 tan 123 green 124 tan 125 blue Data Block Completed Non-Inverted 126 tan Data Block Completed Inverted rev A 127 violet VME Memory Available Non-Inverted 128 tan VME Memory Available Inverted 129 grey 130 tan 131 white 132 tan 133 black 134 tan 135 brown 136 tan 137 red 138 tan rev B after ECO 127 violet spare Non-Inverted 128 tan spare Inverted 129 grey External Clock Input Non-Inverted 130 tan External Clock Input Inverted 131 white Front-End Not Busy Non-Inverted 132 tan Front-End Not Busy Inverted 133 black Start Data Block (to write A/B) Non-Inverted 134 tan Start Data Block (output) Inverted 135 brown Clr Mst Rec Trig (to write A/B) Non-Inverted 136 tan Clr Mst Rec Trig (output) Inverted 137 red 138 tan 139 Ground GND 140 Ground GND J3: 50 PIN CONNECTOR ------------------------------------------------------------------------------ Pin DEC Name Function Mnemonic # ------------------------------------------------------------------------------ 14 B I/O 0 Function Address Bit#1 FA1 & Data Block Spy Data Bit#1 DBSD1 12 B I/O 1 Function Address Bit#2 FA2 & Data Block Spy Data Bit#2 DBSD2 13 B I/O 2 Function Address Bit#3 FA3 & Data Block Spy Data Bit#3 DBSD3 11 B I/O 3 Function Address Bit#4 FA4 & Data Block Spy Data Bit#4 DBSD4 16 B I/O 4 Function Address Bit#5 FA5 & Data Block Spy Data Bit#5 DBSD5 9 B I/O 5 Function Address Bit#6 FA6 & Data Block Spy Data Bit#6 DBSD6 15 B I/O 6 Function Address Bit#7 FA7 & Data Block Spy Data Bit#7 DBSD7 10 B I/O 7 Function Address Bit#8 FA8 & Data Block Spy Data Bit#8 DBSD8 4 B I/O 8 Card Address Bit#1 CA1 & Data Block Spy Data Bit#9 DBSD9 1 B I/O 9 Card Address Bit#2 CA2 & Data Block Spy Data Bit#10 DBSD10 7 B I/O 10 Card Address Bit#3 CA3 & Data Block Spy Data Bit#11 DBSD11 3 B I/O 11 Card Address Bit#4 CA4 & Data Block Spy Data Bit#12 DBSD12 2 B I/O 12 Card Address Bit#5 CA5 & Data Block Spy Data Bit#13 DBSD13 8 B I/O 13 Card Address Bit#6 CA6 & Data Block Spy Data Bit#14 DBSD14 5 B I/O 14 Strobe STB & Data Block Spy Data Bit#15 DBSD15 6 B I/O 15 Direction DIR & Data Block Spy Data Bit#16 DBSD16 17 GND Ground 18 USER RPLY B Data Block Spy Full Interrupt DBSFI 19 GND Ground 20 DRV11J RDY B 21 GND Ground 22 USER RDY B 23 GND Ground 24 DRV11J RPLY B Increment Data Block Spy Counter IDBSC 25 GND Ground 26 GND Ground 27 USER RPLY A Control Bus Freed Interrupt CBFI 28 GND Ground 29 DRV11J RDY A 30 GND Ground 31 USER RDY A 32 GND Ground 33 DRV11J RPLY A 34 GND Ground 37 A I/O 0 Mother-Board Address Bit#1 MBA1 39 A I/O 1 Mother-Board Address Bit#2 MBA2 38 A I/O 2 Mother-Board Address Bit#3 MBA3 40 A I/O 3 Mother-Board Address Bit#4 MBA4 35 A I/O 4 Mother-Board Address Bit#5 MBA5 42 A I/O 5 Mother-Board Address Bit#6 MBA6 36 A I/O 6 Mother-Board Address Bit#7 MBA7 41 A I/O 7 Mother-Board Address Bit#8 MBA8 47 A I/O 8 Cable CBUS2/1 Selection 50 A I/O 9 Unused 44 A I/O 10 Unused 48 A I/O 11 Unused 49 A I/O 12 Unused 43 A I/O 13 Unused 46 A I/O 14 Initialize Bar 45 A I/O 15 Initialize J4: 50 PIN CONNECTOR ------------------------------------------------------------------------------ Pin DEC Name Function Mnemonic # ------------------------------------------------------------------------------ 14 C I/O 0 Bidirec. Data Computer to System Bit#1 BDOU1 12 C I/O 1 Bidirec. Data Computer to System Bit#2 BDOU2 13 C I/O 2 Bidirec. Data Computer to System Bit#3 BDOU3 11 C I/O 3 Bidirec. Data Computer to System Bit#4 BDOU4 16 C I/O 4 Bidirec. Data Computer to System Bit#5 BDOU5 9 C I/O 5 Bidirec. Data Computer to System Bit#6 BDOU6 15 C I/O 6 Bidirec. Data Computer to System Bit#7 BDOU7 10 C I/O 7 Bidirec. Data Computer to System Bit#8 BDOU8 4 C I/O 8 Disable Data Block Builder DISDB 1 C I/O 9 Disable Trigger DISTG 7 C I/O 10 Toggle Half Double Buffer THDB 3 C I/O 11 Reading Data Block Spy RDBS 2 C I/O 12 Spy Next Data Block SNDB 8 C I/O 13 Disable Data Block Sendout DDBS 5 C I/O 14 Bus Control Request BCRQ 6 C I/O 15 Start New Data Block SNDB 17 GND Ground 18 USER RPLY C Buffer Overwriting Error Interrupt BOEI 19 GND Ground 20 DRV11J RDY C 21 GND Ground 22 USER RDY C 23 GND Ground 24 DRV11J RPLY C 25 GND Ground 26 GND Ground 27 USER RPLY D 28 GND Ground 29 DRV11J RDY D 30 GND Ground 31 USER RDY D 32 GND Ground 33 DRV11J RPLY D 34 GND Ground 37 D I/O 0 Bidirec. Data System to Computer Bit#1 BDIN1 39 D I/O 1 Bidirec. Data System to Computer Bit#2 BDIN2 38 D I/O 2 Bidirec. Data System to Computer Bit#3 BDIN3 40 D I/O 3 Bidirec. Data System to Computer Bit#4 BDIN4 35 D I/O 4 Bidirec. Data System to Computer Bit#5 BDIN5 42 D I/O 5 Bidirec. Data System to Computer Bit#6 BDIN6 36 D I/O 6 Bidirec. Data System to Computer Bit#7 BDIN7 41 D I/O 7 Bidirec. Data System to Computer Bit#8 BDIN8 47 D I/O 8 Timing & Synchronization Signal Bit# TSS 50 D I/O 9 Timing & Synchronization Signal Bit# TSS 44 D I/O 10 Half Double Buffer Written HDBW 48 D I/O 11 Half Double Buffer Read HDBR 49 D I/O 12 Control Bus Freed CBF 43 D I/O 13 Data Block Spy Full DBSFUL 46 D I/O 14 Double Buffer Full BUFFUL 45 D I/O 15 Data Blcok Builder Busy DBBB J5 : 64 PIN CONNECTOR TO THE VMX DRIVER CARD ------------------------------------------------------------------------------ Pin Color Function Mnemonic # on cable ------------------------------------------------------------------------------ 1 brown Data Block Builder Address Bit # 1 DBBA1 2 tan Ground 3 red Data Block Builder Address Bit # 2 DBBA2 4 tan Ground 5 orange Data Block Builder Address Bit # 3 DBBA3 6 tan Ground 7 yellow Data Block Builder Address Bit # 4 DBBA4 8 tan Ground 9 green Data Block Builder Address Bit # 5 DBBA5 10 tan Ground 11 blue Data Block Builder Address Bit # 6 DBBA6 12 tan Ground 13 violet Data Block Builder Address Bit # 7 DBBA7 14 tan Ground 15 grey Data Block Builder Address Bit # 8 DBBA8 16 tan Ground 17 white Data Block Builder Address Bit # 9 DBBA9 18 tan Ground 19 black Data Block Builder Address Bit # 10 DBBA10 20 tan Ground 21 brown Data Block Builder Address Bit # 11 DBBA11 22 tan Ground 23 red Data Block Builder Address Bit # 12 DBBA12 24 tan Ground 25 orange Data Block Builder not busy DBBNB 26 tan Ground 27 yellow Clock CLK 28 tan Ground 29 green 30 tan Ground 31 blue 32 tan Ground 33 violet Data Block Builder Data Bit # 1 DBBD1 34 tan Ground 35 grey Data Block Builder Data Bit # 2 DBBD2 36 tan Ground 37 white Data Block Builder Data Bit # 3 DBBD3 38 tan Ground 39 black Data Block Builder Data Bit # 4 DBBD4 40 tan Ground 41 brown Data Block Builder Data Bit # 5 DBBD5 42 tan Ground 43 red Data Block Builder Data Bit # 6 DBBD6 44 tan Ground 45 orange Data Block Builder Data Bit # 7 DBBD7 46 tan Ground 47 yellow Data Block Builder Data Bit # 8 DBBD8 48 tan Ground 49 green Data Block Builder Data Bit # 9 DBBD9 50 tan Ground 51 blue Data Block Builder Data Bit # 10 DBBD10 52 tan Ground 53 violet Data Block Builder Data Bit # 11 DBBD11 54 tan Ground 55 grey Data Block Builder Data Bit # 12 DBBD12 56 tan Ground 57 white Data Block Builder Data Bit # 13 DBBD13 58 tan Ground 59 black Data Block Builder Data Bit # 14 DBBD14 60 tan Ground 61 brown Data Block Builder Data Bit # 15 DBBD15 62 tan Ground 63 red Data Block Builder Data Bit # 16 DBBD16 64 tan Ground DRV11-J CARD TTL I/O LINES ASSIGNMENT ------------------------------------------------------------------------------ NAME OUTPUT INPUT ------------------------------------------------------------------------------ USER RPLY A CONTROL BUS FREED INTERRUPT DRV11J RPLY A DRV11J RDY A USER RDY A A I/O 15 INITIALIZE A I/O 14 INITIALIZE BAR A I/O 13 A I/O 12 A I/O 11 A I/O 10 A I/O 9 _ A I/O 8 CABLE A/B SELECT A I/O 7 MBA8 A I/O 6 MBA7 A I/O 5 MBA6 A I/O 4 MBA5 A I/O 3 MBA4 A I/O 2 MBA3 A I/O 1 MBA2 A I/O 0 MBA1 USER RPLY B DATA BLOCK SPY FULL INTERRUPT DRV11J RPLY B INCREMENT DB SPY COUNTER DRV11J RDY B USER RDY B B I/O 15 DIRECTION DBSPY16 B I/O 14 STROBE DBSPY15 B I/O 13 CA6 DBSPY14 B I/O 12 CA5 DBSPY13 B I/O 11 CA4 DBSPY12 B I/O 10 CA3 DBSPY11 B I/O 9 CA2 DBSPY10 B I/O 8 CA1 DBSPY9 B I/O 7 FA8 DBSPY8 B I/O 6 FA7 DBSPY7 B I/O 5 FA6 DBSPY6 B I/O 4 FA5 DBSPY5 B I/O 3 FA4 DBSPY4 B I/O 2 FA3 DBSPY3 B I/O 1 FA2 DBSPY2 B I/O 0 FA1 DBSPY1 USER RPLY C BUFFER OVERWRITING ERROR INTERRUPT DRV11J RPLY C DRV11J RDY C USER RDY C C I/O 15 START NEW DATA BLOCK C I/O 14 BUS CONTROL REQUEST C I/O 13 DISABLE DATA BLOCK SENDOUT C I/O 12 SPY NEXT DATA BLOCK C I/O 11 READING DATA BLOCK SPY C I/O 10 TOGGLE HALF DOUBLE BUFFER READ C I/O 9 DISABLE TRIGGER (F-E BUSY) C I/O 8 DISABLE DATA BLOCK BUILDER C I/O 7 BDOUT8 C I/O 6 BDOUT7 C I/O 5 BDOUT6 C I/O 4 BDOUT5 C I/O 3 BDOUT4 C I/O 2 BDOUT3 C I/O 1 BDOUT2 C I/O 0 BDOUT1 USER RPLY D DRV11J RPLY D DRV11J RDY D USER RDY D D I/O 15 DATA BLOCK BUILDER BUSY D I/O 14 DOUBLE BUFFER FULL (F-E BUSY) D I/O 13 DATA BLOCK SPY FULL D I/O 12 CONTROL BUS FREED D I/O 11 HALF DOUBLE BUFFER READ (T&S) D I/O 10 HALF DOUBLE BUFFER WRITTEN (T&S) D I/O 9 TIMING & SYNC # D I/O 8 NEW DATA BLOCK CYCLE REQUESTED D I/O 7 BDIN8 D I/O 6 BDIN7 D I/O 5 BDIN6 D I/O 4 BDIN5 D I/O 3 BDIN4 D I/O 2 BDIN3 D I/O 1 BDIN2 D I/O 0 BDIN1 POWER REQUIREMENTS: The COMINT uses VCC (+5V), VEE (-5.2V) and GROUND power supply connections. The calculated power consumption is: VCC: maximum ------- 74x and memory chips 3.0 A 10KH chips: 0.8 A ------- 3.8 A VEE: maximum ------- 10KH chips: 1.6 A VEE pulldown 1.8 A ------- 3.4 A