---------------------------------------------------------------- ! ! ! D0 FIRST LEVEL TRIGGER SYSTEM DIGIMEM CARD ! ! ! ---------------------------------------------------------------- Michigan State University - 12-Jun-1987 GENERAL DESCRIPTION The DIGIMEM card is used in the Trigger Framework. These cards are used to form a computer programable selection and combination matrix. DIGIMEM cards are used in two such matrix's in the Trigger Framework. One is used as a lookup memory used to generate start digitization commands from Final Specific Trigger Card outputs. The other matrix is used as a lookup memory to convert busy signals into disables for the Final Specific Trigger Decision Card. The Final Specific Trigger signals or busy signals are supplied to the DIGIMEM card from an TLM card of which there is 1 per MOTHERBOARD. A total of 16 of these cards will occupy 8 slots in the third mother board in the two racks that make up the trigger framework. One rack will contain the Final Specific Trigger matrix and one rack will contain the busy signal matrix. The DIGIMEM card receives its final specific trigger or its disable inputs as 128 differential ECL signals on two connectors J1 and J2 from the mother board. Computer input is supplied on the front of the card via 32 differential ECL signals supplied via ribbon cable from the mother board driver card. The DIGIMEM card supplies start digitization or specific trigger disable out on a 34 pin front panel connector. This output is a differential ECL signal. The DIGIMEM card has 4 I/O connectors J1 through J4. Connectors J1 and J2 are D0 Trigger Framework backplane connectors. These connectors carry power onto the board and carry the 4 groups of 32 busy or final specific trigger signals. Connector J3 is a 34 pin front panel connector. The start digitize or disable specific trigger output is carried on eight pins on this connector. The four pairs are determined by the position of the card in the rack and are selected by wire wrap jumpers on the board. Connector J4 s a 64 pin front panel connector. The computer bus (data, address, function code, and timing signals) is carried on this connector. The DIGIMEM card uses two power supplies. A power supply of+5.0 volts is used for the bulk of the logic on the board. A power supply of 5.2 volts is used for the differential ECL driver and receiver circuits in the I/O section. These supply voltages are brought on to the card through the backplane connectors J1 and J2. PROGRAMMING The DIGIMEM card has 32 eight bit programmable read/write registers. These registers are accessed with function codes 0 through 31. Each register controls 4 bits of external signal input. When power is first applied these registers contain random data and must be programmed to contain the proper data by writing appropriate data to them. As an example consider the register selected by function code 0. The 4 low order bits (bits 0-3) of this word control the sense of busy signal or final specific trigger bits 1-4. A 0 on these bits require the corresponding busy signal or final specific trigger to be a 1 to be in the matrix. A 1 on these bits require the corresponding busy signal or final specific trigger to be a 0 to be in the matrix. The 4 high order bits (bits 4-7) of this word select which bits will be used in forming an output signal. A 1 on one of these bits eliminates that bit from the matrix while a 0 on that bit select it for the matrix according to its sense bit. This information is summarized in the table below. trigger control bit trigger sense bit programmed result ---------------------------------------------------------- 0 0 must be high 0 1 must be low 1 0 not in trigger 1 1 not in trigger The following table is a map for function codes 0-31. function code bits function ---------------------------------------------------- 0 0-3 trigger sense bits 0-3 0 4-7 trigger control bits 0-3 1 0-3 trigger sense bits 4-7 1 4-7 trigger control bits 4-7 2 0-3 trigger sense bits 8-11 2 4-7 trigger control bits 8-11 3 0-3 trigger sense bits 12-15 3 4-7 trigger control bits 12-15 4 0-3 trigger sense bits 16-19 4 4-7 trigger control bits 16-19 5 0-3 trigger sense bits 20-23 5 4-7 trigger control bits 20-23 6 0-3 trigger sense bits 24-27 6 4-7 trigger control bits 24-27 7 0-3 trigger sense bits 28-31 7 4-7 trigger control bits 28-31 8 0-3 trigger sense bits 32-35 8 4-7 trigger control bits 32-35 9 0-3 trigger sense bits 36-40 9 4-7 trigger control bits 36-40 10 0-3 trigger sense bits 41-43 10 4-7 trigger control bits 41-43 11 0-3 trigger sense bits 44-47 11 4-7 trigger control bits 44-47 12 0-3 trigger sense bits 48-51 12 4-7 trigger control bits 48-51 13 0-3 trigger sense bits 52-55 13 4-7 trigger control bits 52-55 14 0-3 trigger sense bits 56-59 14 4-7 trigger control bits 56-59 15 0-3 trigger sense bits 60-63 15 4-7 trigger control bits 60-63 16 0-3 trigger sense bits 64-67 16 4-7 trigger control bits 64-67 17 0-3 trigger sense bits 68-71 17 4-7 trigger control bits 68-71 18 0-3 trigger sense bits 72-75 18 4-7 trigger control bits 72-75 19 0-3 trigger sense bits 76-79 19 4-7 trigger control bits 76-79 20 0-3 trigger sense bits 80-83 20 4-7 trigger control bits 80-83 21 0-3 trigger sense bits 84-87 21 4-7 trigger control bits 84-87 22 0-3 trigger sense bits 88-91 22 4-7 trigger control bits 88-91 23 0-3 trigger sense bits 92-95 23 4-7 trigger control bits 92-95 24 0-3 trigger sense bits 96-99 24 4-7 trigger control bits 96-99 25 0-3 trigger sense bits 100-103 25 4-7 trigger control bits 100-103 26 0-3 trigger sense bits 104-107 26 4-7 trigger control bits 104-107 27 0-3 trigger sense bits 108-111 27 4-7 trigger control bits 108-111 28 0-3 trigger sense bits 112-115 28 4-7 trigger control bits 112-115 29 0-3 trigger sense bits 116-119 29 4-7 trigger control bits 116-119 30 0-3 trigger sense bits 120-123 30 4-7 trigger control bits 120-123 31 0-3 trigger sense bits 124-127 31 4-7 trigger control bits 124-127 There is one 8 position dip switch on the board. This switch is used to set the card address. Switches 1-6 correspond to card addresses 1-6 with the switch in the on position giving a logical 0. Switches 7 and 8 are unused. There is an eight pin header J5 to which the final sum high and final sum low signals from the output of the DIGIMEM network are brought. These lines are then wire wrapped to eight pins on the 34 pin header J6. The front panel has 2 pair of LED's. Each pair is a differential pair used to indicate one signal. The signals displayed are "select" which indicates the card address matches the address set up by the DIP switch and that function codes in the appropriate range have been applied. The other led pair is used to indicate that he conditions to produce a hit in any of the four sections of the matrix as set up by the programming matrix. CONNECTORS J1 : FIRST LEVEL TRIGGER CONTROL COMPUTER BUS 140 PIN CONNECTOR ------------------------------------------------------------------------------ Plug & Pin Function Wire # Mnemonic # on cable ----------------------------------------------------------------------------- 1 Ground GND 2 Ground GND 3 Latched Data Bit#1 Non-inverted IN 1 NTL1 4 Latched Data Bit#1 Inverted IN 2 ITL1 5 Latched Data Bit#2 Non-inverted IN 1 NTL2 6 Latched Data Bit#2 Inverted IN 2 ITL2 7 Latched Data Bit#3 Non-inverted IN 1 NTL3 8 Latched Data Bit#3 Inverted IN 2 ITL3 9 Latched Data Bit#4 Non-inverted IN 1 NTL4 10 Latched Data Bit#4 Inverted IN 2 ITL4 11 Latched Data Bit#5 Non-inverted IN 1 NTL5 12 Latched Data Bit#5 Inverted IN 2 ITL5 13 Latched Data Bit#6 Non-inverted IN 1 NTL6 14 Latched Data Bit#6 Inverted IN 2 ITL6 15 Latched Data Bit#7 Non-inverted IN 1 NTL7 16 Latched Data Bit#7 Inverted IN 2 III7 17 Latched Data Bit#8 Non-inverted IN 1 NTL8 18 Latched Data Bit#8 Inverted IN 2 ITL8 19 Latched Data Bit#9 Non-inverted IN 1 NTL9 20 Latched Data Bit#9 Inverted IN 2 ITL9 21 Latched Data Bit#10 Non-inverted IN 1 NTL10 22 Latched Data Bit#10 Inverted IN 2 ITL10 23 Latched Data Bit#11 Non-inverted IN 1 NTL10 24 Latched Data Bit#11 Inverted IN 2 ITL11 25 Latched Data Bit#12 Non-inverted IN 1 NTL12 26 Latched Data Bit#12 Inverted IN 2 ITL12 27 Latched Data Bit#13 Non-inverted IN 1 NTL13 28 Latched Data Bit#13 Inverted IN 2 ITL13 29 Latched Data Bit#14 Non-inverted IN 1 NTL14 30 Latched Data Bit#14 Inverted IN 2 ITL14 31 Latched Data Bit#15 Non-inverted IN 1 NTL15 32 Latched Data Bit#15 Inverted IN 2 ITL15 33 Latched Data Bit#16 Non-inverted IN 1 NTL16 34 Latched Data Bit#16 Inverted IN 2 ITL16 35 Latched Data Bit#17 Non-inverted IN 1 NTL17 36 Latched Data Bit#17 Inverted IN 2 ITL17 37 Latched Data Bit#18 Non-inverted IN 1 NTL18 38 Latched Data Bit#18 Inverted IN 2 ITL18 39 Latched Data Bit#19 Non-inverted IN 1 NTL19 40 Latched Data Bit#19 Inverted IN 2 ITL19 41 Latched Data Bit#20 Non-inverted IN 1 NTL20 42 Latched Data Bit#20 Inverted IN 2 ITL20 43 Latched Data Bit#21 Non-inverted IN 1 NTL21 44 Latched Data Bit#21 Inverted IN 2 ITL21 45 Latched Data Bit#22 Non-inverted IN 1 NTL22 46 Latched Data Bit#22 Inverted IN 2 ITL22 47 Latched Data Bit#23 Non-inverted IN 1 NTL23 48 Latched Data Bit#23 Inverted IN 2 ITL23 49 Latched Data Bit#24 Non-inverted IN 1 NTL24 50 Latched Data Bit#24 Inverted IN 2 ITL24 51 Latched Data Bit#25 Non-inverted IN 1 NTL25 52 Latched Data Bit#25 Inverted IN 2 ITL25 53 Latched Data Bit#26 Non-inverted IN 1 NTL26 54 Latched Data Bit#26 Inverted IN 2 ITL26 55 Latched Data Bit#27 Non-inverted IN 1 NTL27 56 Latched Data Bit#27 Inverted IN 2 ITL27 57 Latched Data Bit#28 Non-inverted IN 1 NTL28 58 Latched Data Bit#28 Inverted IN 2 ITL28 59 Latched Data Bit#29 Non-inverted IN 1 NTL29 60 Latched Data Bit#29 Inverted IN 2 ITL29 61 Latched Data Bit#30 Non-inverted IN 1 NTL30 62 Latched Data Bit#30 Inverted IN 2 ITL30 63 Latched Data Bit#31 Non-inverted IN 1 NTL31 64 Latched Data Bit#31 Inverted IN 2 ITL31 65 Latched Data Bit#32 Non-inverted IN 1 NTL32 66 Latched Data Bit#32 Inverted IN 2 ITL32 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.0 V VEE 72 Power -5.0 V VEE 73 Ground GND 74 Ground GND 75 Latched Data Bit#1 Non-inverted IN 1 NTL1 76 Latched Data Bit#1 Inverted IN 2 ITL1 77 Latched Data Bit#2 Non-inverted IN 1 NTL2 78 Latched Data Bit#2 Inverted IN 2 ITL2 79 Latched Data Bit#3 Non-inverted IN 1 NTL3 80 Latched Data Bit#3 Inverted IN 2 ITL3 81 Latched Data Bit#4 Non-inverted IN 1 NTL4 82 Latched Data Bit#4 Inverted IN 2 ITL4 83 Latched Data Bit#5 Non-inverted IN 1 NTL5 84 Latched Data Bit#5 Inverted IN 2 ITL5 85 Latched Data Bit#6 Non-inverted IN 1 NTL6 86 Latched Data Bit#6 Inverted IN 2 ITL6 87 Latched Data Bit#7 Non-inverted IN 1 NTL7 88 Latched Data Bit#7 Inverted IN 2 ITL7 89 Latched Data Bit#8 Non-inverted IN 1 NTL8 90 Latched Data Bit#8 Inverted IN 2 ITL8 91 Latched Data Bit#9 Non-inverted IN 1 NTL9 92 Latched Data Bit#9 Inverted IN 2 ITL9 93 Latched Data Bit#10 Non-inverted IN 1 NTL10 94 Latched Data Bit#10 Inverted IN 2 ITL10 95 Latched Data Bit#11 Non-inverted IN 1 NTL11 96 Latched Data Bit#11 Inverted IN 2 ITL11 97 Latched Data Bit#12 Non-inverted IN 1 NTL12 98 Latched Data Bit#12 Inverted IN 2 ITL12 99 Latched Data Bit#13 Non-inverted IN 1 NTL13 100 Latched Data Bit#13 Inverted IN 2 ITL13 101 Latched Data Bit#14 Non-inverted IN 1 NTL14 102 Latched Data Bit#14 Inverted IN 2 ITL14 103 Latched Data Bit#15 Non-inverted IN 1 NTL15 104 Latched Data Bit#15 Inverted IN 2 ITL15 105 Latched Data Bit#16 Non-inverted IN 1 NTL16 106 Latched Data Bit#16 Inverted IN 2 ITL16 107 Latched Data Bit#17 Non-inverted IN 1 NTL17 108 Latched Data Bit#17 Inverted IN 2 ITL17 109 Latched Data Bit#18 Non-inverted IN 1 NTL18 110 Latched Data Bit#18 Inverted IN 2 ITL18 111 Latched Data Bit#19 Non-inverted IN 1 NTL19 112 Latched Data Bit#19 Inverted IN 2 ITL19 113 Latched Data Bit#20 Non-inverted IN 1 NTL20 114 Latched Data Bit#20 Inverted IN 2 ITL20 115 Latched Data Bit#21 Non-inverted IN 1 NTL21 116 Latched Data Bit#21 Inverted IN 2 ITL21 117 Latched Data Bit#22 Non-inverted IN 1 NTL22 118 Latched Data Bit#22 Inverted IN 2 ITL22 119 Latched Data Bit#23 Non-inverted IN 1 NTL23 120 Latched Data Bit#23 Inverted IN 2 ITL23 121 Latched Data Bit#24 Non-inverted IN 1 NTL24 122 Latched Data Bit#24 Inverted IN 2 ITL24 123 Latched Data Bit#25 Non-inverted IN 1 NTL25 124 Latched Data Bit#25 Inverted IN 2 ITL25 125 Latched Data Bit#26 Non-inverted IN 1 NTL26 126 Latched Data Bit#26 Inverted IN 2 ITL26 127 Latched Data Bit#27 Non-inverted IN 1 NTL27 128 Latched Data Bit#27 Inverted IN 2 ITL27 129 Latched Data Bit#28 Non-inverted IN 1 NTL28 130 Latched Data Bit#28 Inverted IN 2 ITL28 131 Latched Data Bit#29 Non-inverted IN 1 NTL29 132 Latched Data Bit#29 Inverted IN 2 ITL29 133 Latched Data Bit#30 Non-inverted IN 1 NTL30 134 Latched Data Bit#30 Inverted IN 2 ITL30 135 Latched Data Bit#31 Non-inverted IN 1 NTL31 136 Latched Data Bit#31 Inverted IN 2 ITL31 137 Latched Data Bit#32 Non-inverted IN 1 NTL32 138 Latched Data Bit#32 Inverted IN 2 ITL32 139 Ground GND 140 Ground GND ----------------------------------------------------------------------------- J2 : FIRST LEVEL TRIGGER CONTROL COMPUTER BUS 140 PIN CONNECTOR ------------------------------------------------------------------------------ Plug & Pin Function Wire # Mnemonic # on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 Latched Data Bit#1 Non-inverted IN 1 NTL1 4 Latched Data Bit#1 Inverted IN 2 ITL1 5 Latched Data Bit#2 Non-inverted IN 1 NTL2 6 Latched Data Bit#2 Inverted IN 2 ITL2 7 Latched Data Bit#3 Non-inverted IN 1 NTL3 8 Latched Data Bit#3 Inverted IN 2 ITL3 9 Latched Data Bit#4 Non-inverted IN 1 NTL4 10 Latched Data Bit#4 Inverted IN 2 ITL4 11 Latched Data Bit#5 Non-inverted IN 1 NTL5 12 Latched Data Bit#5 Inverted IN 2 ITL5 13 Latched Data Bit#6 Non-inverted IN 1 NTL6 14 Latched Data Bit#6 Inverted IN 2 ITL6 15 Latched Data Bit#7 Non-inverted IN 1 NTL7 16 Latched Data Bit#7 Inverted IN 2 III7 17 Latched Data Bit#8 Non-inverted IN 1 NTL8 18 Latched Data Bit#8 Inverted IN 2 ITL8 19 Latched Data Bit#9 Non-inverted IN 1 NTL9 20 Latched Data Bit#9 Inverted IN 2 ITL9 21 Latched Data Bit#10 Non-inverted IN 1 NTL10 22 Latched Data Bit#10 Inverted IN 2 ITL10 23 Latched Data Bit#11 Non-inverted IN 1 NTL10 24 Latched Data Bit#11 Inverted IN 2 ITL11 25 Latched Data Bit#12 Non-inverted IN 1 NTL12 26 Latched Data Bit#12 Inverted IN 2 ITL12 27 Latched Data Bit#13 Non-inverted IN 1 NTL13 28 Latched Data Bit#13 Inverted IN 2 ITL13 29 Latched Data Bit#14 Non-inverted IN 1 NTL14 30 Latched Data Bit#14 Inverted IN 2 ITL14 31 Latched Data Bit#15 Non-inverted IN 1 NTL15 32 Latched Data Bit#15 Inverted IN 2 ITL15 33 Latched Data Bit#16 Non-inverted IN 1 NTL16 34 Latched Data Bit#16 Inverted IN 2 ITL16 35 Latched Data Bit#17 Non-inverted IN 1 NTL17 36 Latched Data Bit#17 Inverted IN 2 ITL17 37 Latched Data Bit#18 Non-inverted IN 1 NTL18 38 Latched Data Bit#18 Inverted IN 2 ITL18 39 Latched Data Bit#19 Non-inverted IN 1 NTL19 40 Latched Data Bit#19 Inverted IN 2 ITL19 41 Latched Data Bit#20 Non-inverted IN 1 NTL20 42 Latched Data Bit#20 Inverted IN 2 ITL20 43 Latched Data Bit#21 Non-inverted IN 1 NTL21 44 Latched Data Bit#21 Inverted IN 2 ITL21 45 Latched Data Bit#22 Non-inverted IN 1 NTL22 46 Latched Data Bit#22 Inverted IN 2 ITL22 47 Latched Data Bit#23 Non-inverted IN 1 NTL23 48 Latched Data Bit#23 Inverted IN 2 ITL23 49 Latched Data Bit#24 Non-inverted IN 1 NTL24 50 Latched Data Bit#24 Inverted IN 2 ITL24 51 Latched Data Bit#25 Non-inverted IN 1 NTL25 52 Latched Data Bit#25 Inverted IN 2 ITL25 53 Latched Data Bit#26 Non-inverted IN 1 NTL26 54 Latched Data Bit#26 Inverted IN 2 ITL26 55 Latched Data Bit#27 Non-inverted IN 1 NTL27 56 Latched Data Bit#27 Inverted IN 2 ITL27 57 Latched Data Bit#28 Non-inverted IN 1 NTL28 58 Latched Data Bit#28 Inverted IN 2 ITL28 59 Latched Data Bit#29 Non-inverted IN 1 NTL29 60 Latched Data Bit#29 Inverted IN 2 ITL29 61 Latched Data Bit#30 Non-inverted IN 1 NTL30 62 Latched Data Bit#30 Inverted IN 2 ITL30 63 Latched Data Bit#31 Non-inverted IN 1 NTL31 64 Latched Data Bit#31 Inverted IN 2 ITL31 65 Latched Data Bit#32 Non-inverted IN 1 NTL32 66 Latched Data Bit#32 Inverted IN 2 ITL32 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.0 V VEE 72 Power -5.0 V VEE 73 Ground GND 74 Ground GND 75 Latched Data Bit#1 Non-inverted IN 1 NTL1 76 Latched Data Bit#1 Inverted IN 2 ITL1 77 Latched Data Bit#2 Non-inverted IN 1 NTL2 78 Latched Data Bit#2 Inverted IN 2 ITL2 79 Latched Data Bit#3 Non-inverted IN 1 NTL3 80 Latched Data Bit#3 Inverted IN 2 ITL3 81 Latched Data Bit#4 Non-inverted IN 1 NTL4 82 Latched Data Bit#4 Inverted IN 2 ITL4 83 Latched Data Bit#5 Non-inverted IN 1 NTL5 84 Latched Data Bit#5 Inverted IN 2 ITL5 85 Latched Data Bit#6 Non-inverted IN 1 NTL6 86 Latched Data Bit#6 Inverted IN 2 ITL6 87 Latched Data Bit#7 Non-inverted IN 1 NTL7 88 Latched Data Bit#7 Inverted IN 2 ITL7 89 Latched Data Bit#8 Non-inverted IN 1 NTL8 90 Latched Data Bit#8 Inverted IN 2 ITL8 91 Latched Data Bit#9 Non-inverted IN 1 NTL9 92 Latched Data Bit#9 Inverted IN 2 ITL9 93 Latched Data Bit#10 Non-inverted IN 1 NTL10 94 Latched Data Bit#10 Inverted IN 2 ITL10 95 Latched Data Bit#11 Non-inverted IN 1 NTL11 96 Latched Data Bit#11 Inverted IN 2 ITL11 97 Latched Data Bit#12 Non-inverted IN 1 NTL12 98 Latched Data Bit#12 Inverted IN 2 ITL12 99 Latched Data Bit#13 Non-inverted IN 1 NTL13 100 Latched Data Bit#13 Inverted IN 2 ITL13 101 Latched Data Bit#14 Non-inverted IN 1 NTL14 102 Latched Data Bit#14 Inverted IN 2 ITL14 103 Latched Data Bit#15 Non-inverted IN 1 NTL15 104 Latched Data Bit#15 Inverted IN 2 ITL15 105 Latched Data Bit#16 Non-inverted IN 1 NTL16 106 Latched Data Bit#16 Inverted IN 2 ITL16 107 Latched Data Bit#17 Non-inverted IN 1 NTL17 108 Latched Data Bit#17 Inverted IN 2 ITL17 109 Latched Data Bit#18 Non-inverted IN 1 NTL18 110 Latched Data Bit#18 Inverted IN 2 ITL18 111 Latched Data Bit#19 Non-inverted IN 1 NTL19 112 Latched Data Bit#19 Inverted IN 2 ITL19 113 Latched Data Bit#20 Non-inverted IN 1 NTL20 114 Latched Data Bit#20 Inverted IN 2 ITL20 115 Latched Data Bit#21 Non-inverted IN 1 NTL21 116 Latched Data Bit#21 Inverted IN 2 ITL21 117 Latched Data Bit#22 Non-inverted IN 1 NTL22 118 Latched Data Bit#22 Inverted IN 2 ITL22 119 Latched Data Bit#23 Non-inverted IN 1 NTL23 120 Latched Data Bit#23 Inverted IN 2 ITL23 121 Latched Data Bit#24 Non-inverted IN 1 NTL24 122 Latched Data Bit#24 Inverted IN 2 ITL24 123 Latched Data Bit#25 Non-inverted IN 1 NTL25 124 Latched Data Bit#25 Inverted IN 2 ITL25 125 Latched Data Bit#26 Non-inverted IN 1 NTL26 126 Latched Data Bit#26 Inverted IN 2 ITL26 127 Latched Data Bit#27 Non-inverted IN 1 NTL27 128 Latched Data Bit#27 Inverted IN 2 ITL27 129 Latched Data Bit#28 Non-inverted IN 1 NTL28 130 Latched Data Bit#28 Inverted IN 2 ITL28 131 Latched Data Bit#29 Non-inverted IN 1 NTL29 132 Latched Data Bit#29 Inverted IN 2 ITL29 133 Latched Data Bit#30 Non-inverted IN 1 NTL30 134 Latched Data Bit#30 Inverted IN 2 ITL30 135 Latched Data Bit#31 Non-inverted IN 1 NTL31 136 Latched Data Bit#31 Inverted IN 2 ITL31 137 Latched Data Bit#32 Non-inverted IN 1 NTL32 138 Latched Data Bit#32 Inverted IN 2 ITL32 139 Ground GND 140 Ground GND ---------------------------------------------------------------------------- J4 : COMPUTER BUS CONNECTOR ---------------------------------------------------------------------------- Pin # Color on on cable Function Mnemonic Cable ---------------------------------------------------------------------------- 1 Brown Bidirectional Data Bit#8 Non-inverted NDB8 2 Tan Bidirectional Data Bit#8 Inverted IDB8 3 Red Bidirectional Data Bit#7 Non-inverted NDB7 4 Tan Bidirectional Data Bit#7 Inverted IDB7 5 Orange Bidirectional Data Bit#6 Non-inverted NDB6 6 Tan Bidirectional Data Bit#6 Inverted IDB6 7 Yellow Bidirectional Data Bit#5 Non-inverted NDB5 8 Tan Bidirectional Data Bit#5 Inverted IDB5 9 Green Bidirectional Data Bit#4 Non-inverted NDB4 0 Tan Bidirectional Data Bit#4 Inverted IDB4 11 Blue Bidirectional Data Bit#3 Non-inverted NDB3 12 Tan Bidirectional Data Bit#3 Inverted IDB3 13 Violet Bidirectional Data Bit#2 Non-inverted NDB2 14 Tan Bidirectional Data Bit#2 Inverted IDB2 15 Grey Bidirectional Data Bit#1 Non-inverted NDB1 16 Tan Bidirectional Data Bit#1 Inverted IDB1 17 White Direction Non-inverted NDIR 18 Tan Direction Inverted IDIR 19 Black Strobe Non-inverted NSTB 20 Tan Strobe Inverted ISTB 21 Brown Function Address Bit#8 Non-inverted NAF8 22 Tan Function Address Bit#8 Inverted IAF8 23 Red Function Address Bit#7 Non-inverted NAF7 24 Tan Function Address Bit#7 Inverted IAF7 25 Orange Function Address Bit#6 Non-inverted NAF6 26 Tan Function Address Bit#6 Inverted IAF6 27 Yellow Function Address Bit#5 Non-inverted NAF5 28 Tan Function Address Bit#5 Inverted IAF5 29 Green Function Address Bit#4 Non-inverted NAF4 30 Tan Function Address Bit#4 Inverted IAF4 31 Blue Function Address Bit#3 Non-inverted NAF3 32 Tan Function Address Bit#3 Inverted NAF3 33 Violet Function Address Bit#2 Non-inverted NAF2 34 Tan Function Address Bit#2 Inverted IAF2 35 Grey Function Address Bit#1 Non-inverted NAF1 36 Tan Function Address Bit#1 Inverted IAF1 37 White Card Address Bit#6 Non-inverted NAC6 38 Tan Card Address Bit#6 Inverted IAC6 33 Black Card Address Bit#5 Non-inverted NAC5 40 Tan Card Address Bit#5 Inverted IAC5 41 Brown Card Address Bit#4 Non-inverted NAC4 42 Tan Card Address Bit#4 Inverted IAC4 43 Red Card Address Bit#3 Non-inverted NAC3 44 Tan Card Address Bit#3 Inverted IAC3 45 Orange Card Address Bit#2 Non-inverted NAC2 46 Tan Card Address Bit#2 Inverted IAC2 47 Yellow Card Address Bit#1 Non-inverted NAC1 48 Tan Card Address Bit#1 Inverted IAC1 49 Green Timing & Sync. Signal H Non-inverted NTSH 50 Tan Timing & Sync. Signal H Inverted ITSH 51 Blue Timing & Sync. Signal G Non-inverted NTSG 52 Tan Timing & Sync. Signal G Inverted ITSG 53 Violet Timing & Sync. Signal F Non-inverted NTSF 54 Tan Timing & Sync. Signal F Inverted ITSF 55 Grey Timing & Sync. Signal E Non-inverted NTSE 56 Tan Timing & Sync. Signal E Inverted ITSE 57 White Timing & Sync. Signal D Non-inverted NTSD 58 Tan Timing & Sync. Signal D Inverted ITSD 59 Black Timing & Sync. Signal C Non-inverted NTSC 60 Tan Timing & Sync. Signal C Inverted ITSC 61 Brown Timing & Sync. Signal B Non-inverted NTSB 62 Tan Timing & Sync. Signal B Inverted ITSB 63 Red Timing & Sync. Signal A Non-inverted NTSA 64 Tan Timing & Sync. Signal A Inverted ITSA ----------------------------------------------------------------------------- J3 : DIGIMEM HIT CONNECTOR ----------------------------------------------------------------------------- Pin # Color on on cable Function Mnemonic Cable ---------------------------------------------------------------------------- 1 Brown Digimem Hit Bit#1 Non-inverted NHT1 2 Tan Digimem Hit Bit#1 Inverted IHT1 3 Red Digimem Hit Bit#2 Non-inverted NHT2 4 Tan Digimem Hit Bit#2 Inverted IHT2 5 Orange Digimem Hit Bit#3 Non-inverted NHT3 6 Tan Digimem Hit Bit#3 Inverted IHT3 7 Yellow Digimem Hit Bit#4 Non-inverted NHT4 8 Tan Digimem Hit Bit#4 Inverted IHT4 9 Green Digimem Hit Bit#5 Non-inverted NHT5 0 Tan Digimem Hit Bit#5 Inverted IHT5 11 Blue Digimem Hit Bit#6 Non-inverted NHT6 12 Tan Digimem Hit Bit#6 Inverted IHT6 13 Violet Digimem Hit Bit#7 Non-inverted NHT7 14 Tan Digimem Hit Bit#7 Inverted IHT7 15 Grey Digimem Hit Bit#8 Non-inverted NHT8 16 Tan Digimem Hit Bit#8 Inverted IHT8 17 White Digimem Hit Bit#9 Non-inverted NHT9 18 Tan Digimem Hit Bit#9 Inverted IHT9 19 Black Digimem Hit Bit#10 Non-inverted NHT10 20 Tan Digimem Hit Bit#10 Inverted IHT10 21 Brown Digimem Hit Bit#11 Non-inverted NHT11 22 Tan Digimem Hit Bit#11 Inverted IHT11 23 Red Digimem Hit Bit#12 Non-inverted NHT12 24 Tan Digimem Hit Bit#12 Inverted IHT12 25 Orange Digimem Hit Bit#13 Non-inverted NHT13 26 Tan Digimem Hit Bit#13 Inverted IHT13 27 Yellow Digimem Hit Bit#14 Non-inverted NHT14 28 Tan Digimem Hit Bit#14 Inverted IHT14 29 Green Digimem Hit Bit#15 Non-inverted NHT15 30 Tan Digimem Hit Bit#15 Inverted IHT15 31 Blue Digimem Hit Bit#16 Non-inverted NHT16 32 Tan Digimem Hit Bit#16 Inverted NHT16 33 Violet unused 34 Tan unused ----------------------------------------------------------------------------- DRAWINGS - List of all the drawings produced with drawing numbers. List of every paper written about this board. BOARD HISTORY - the revision history of the First Level Trigger ANDOR CARD is : REVISION A - Number of printed circuit boards ordered & Date - list of the serial numbers of the card built for this revision. - List of all the Engineering Changes Order (ECO) valid for this revision. - Special assembly recommendations and handling precautions. - Parts used : TYPE QUANTITY -------------------------------- 10H101 1 10H115 1 10H124 3 10H125 38 10H188 3 74ALS02 5 74ALS138 8 74AS139 1 74ALS245 4 74ALS30 17 74ALS32 32 74ALS520 1 74ALS541 33 74ALS574 32 74ALS86 32 RBM140 2 EBY64 1 DIALCO2001 4 MONOCAP 252 MSP08 8 SWDIP 1 3MR4 1 34 PIN POST 1 8 PIN POST 1 REVISION B