FINAL SPECIFIC TRIGGER DECISION CARD -------------------------------------- 16-MAR-89 CARD NAME: FINAL SPECIFIC TRIGGER DECISION FSTD BOARD DESCRIPTION: The Final Specific Trigger Decision Card provides the logic to make the final trigger decision for 4 Specific Triggers. The operations involved in the final trigger decision are the following: 1. The output signals ("hit" signal) from up to 4 AND-OR Cards are combined in an overall AND gate. The resulting signal will become active only when all of the connected AND-OR Cards have found a hit. Normally there will be two AND-OR Cards connected to each channel of the FSTD. 2. Next this overall AND signal is combined with a Timing and Sync Signal Number G. In the logic of the FSTD Card the Timing & Sync Signal G is called the AND-OR Strobe Signal. The resulting signal, called the AND-OR Fired Signal, can only be in the active state during the period that the AND-OR Strobe Signal is in the High state. The AND-OR Strobe Signal will only go High after a long enough delay for all of the logic on the AND-OR Cards to have settled. Thus the AND-OR Strobe Signal validates the output from the AND-OR Cards. The AND-OR Fired Signal goes three places. First, it is combined with further logic to make the specific trigger fired signal. Second it is an input to an AM29520 double buffered memory register so that the state of this AND-OR Fired Signal may be read out for both the current and the previous beam crossings. Third this signal goes through a driver and off the card so that it may be connected to other logic e.g. some special trigger logic. 3. The next step in the logic of the FSTD Card is to combine the AND-OR Fired Signal with the Specific Trigger Enable Signal to make the Specific Trigger Fired Signal. The Specific Trigger Fired Signal can only become active when the Specific Trigger Enable Signal is active. The Specific Trigger Fired Signal is sent through driver circuits and then off card by two separate paths. One path is for connecting the Specific Trigger Fired Signal to the Trigger Latch Module. The other path is for connecting the Specific Trigger Fired Signal to a Double Buffered Scaler Card. 4. The Specific Trigger Enable Signal is made by a combination of the following signals: Level 1.5 Disable Signal, Level 2.0 Disable Signal, Auxiliary 1 Disable Signal, Auxiliary 2 Disable Signal, Auxiliary 3 Disable Signal, the Auto-Disable Signal, and the Prescaler Disable Signals. Note that Auxiliary 3 Disable is tied high. Before anyone of these disable signals can actually force the Specific Trigger Enabled Signal to a Low state (thus disabling this Specific Trigger) a corresponding bit in the Disable Source Control Register must be set High. The function of the Disable Source Control Register is to enable or disable the various disable signals i.e. to allow or not allow the various trigger vetoes. The result of the combination of the various Disable Signals and the Disable Source Control Register is the input signal to a D type flip-flop. The clock for this filp-flop is called the Trigger Enable Clock and it comes from Trigger and Sync. Signal #E. In this way the Specific Trigger Enable Signal is updated at about 2.8 microsec. after each beam crossing. The Specific Trigger Enable Signal will be low (thus disableing this Specific Trigger) only if one of the disable signals is active (High) and the corresponding bit in the Disable Source Control Register is a one. The Specific Trigger Enable Signal goes three places. It is anded with the AND-OR Fired Signal to make the Specific Trigger Fired Signal which is sent off card through two drives. The Specific Trigger Enable Signal itself is sent through a driver and off card to act as a gate signal for a channel of Double Buffered Scaler. The Double Buffered Scaler counts the number of beam crossings for which this Specific Trigger was sensitive. The Specific Trigger Enable Signal is also the input to an AM29520 double buffered memory register. The double buffered memory register may be read and thus the state of the Specific Trigger Enable Signal determined for both the current and the previous beam crossings. 5. The Specific Trigger Pre-Scaler works in the following way. The Specific Trigger Pre-Scaler must first be loaded by the control computer with the ratio that it should use. The control computer must also program the FSTD channel to allow the Pre-Scaler Disable Signal to force the Specific Trigger Enable Signal to its inactive state. The Pre-Scaler Ratio indicates the number of beam crossings that must have a True AND-OR Fired Signal before the Specific Trigger Enable Signal will enable the generation of a Specific Trigger Fired Signal on the next occurrence of the True AND-OR Fired Signal. This process then repeats. Thus if the Pre-Scaler Ratio were 67 then only every 67 occurrence of the AND-OR Fired Signal could result in a Specific Trigger Fired Signal. 6. The Specific Trigger Auto-Disable Flip-Flop works in the following way. The control computer must first program the FSTD Channel to enable the Auto-Disable Trigger Disable Signal to force the Specific Trigger Enable Signal to its inactive state. Then on the next (first) occurrence of the Specific Trigger Fired Signal the Auto-Disable Flip Flop will change states and begin to generate the Auto-Disable Trigger Disable Signal which will block any further Specific Trigger Fired Signals. When the acquisition system is ready for another event from this Specific Trigger the control computer can reset the Auto-Disable Flip Flop so that it is not generating the Auto-Disable Trigger Disable Signal. Then when the Spicific Trigger fires again the Auto-Disable Flip Flop will once again change states so that it generates the Auto-Disable Trigger Disable Signal and blocks and more Specific Trigger Fired Signal from this channel of the FSTD Card. The FSTD Card uses the following Timing and Synchronization Signals from the Specific Mother-Board Bus: Timing & Sync. A is used to control which section of the 29520's are written into. When Timing and Sync. Signal A is high then the A half of the 29520's is selected for writting into, and when the Timing and Sync. Signal A is low than the B half of the 29520's is selected for writing scaler data into. Timing & Sync. B is used to LATCH & SHIFT the data in the 29520's. The data is LATCH & SHIFTED on the rising positive edge of the Timing & Sync. Signal B. Timing & Sync. Signal C is used to select which section of the AM29520 is read. When Timing & Sync. Signal C is assereted then the A-half of the AM29520 is read. When the signal is negated then the B-half of the buffer is selected. Function Address bit 8 is used to select either the input-half (current beam crossing) or the output-half (previous beam crossing) of the AM29520 to be read. Function Address bit 8 High => current beam crossing information and Function Address bit 8 Low => previous beam crossing information. The Double Buffer Scaler Card may be read using the C-BUS Fast Read Cycle. PROGRAMING: ----------- There are three types of registers that must be programmed in order to control and readout the FSTD card. These types of registers are: the 4 Specific Trigger Pre-Scaler Ratio Registers, the 4 Disable Source Control Registers, and the 1 Double Buffered Memory Register. PRE-SCALER RATIO REGISTERS The Specific Trigger Pre-Scaler uses an LS7066 24 bit counter in the Up Count Divide By N Mode. The CY signal (pin 16) will go Low once per every N times that the LS7066 is clocked. It is assumed the the B Input (pin 7) is tied High, that the ABGT/RCTR Input (pin 4) is tied High, and the the LCTR/LLTC Input (pin 3) is also tied High. The LS7066 is programmed by loading 5 registers on the chip. The register that is loaded is controlled by the C/D signal and by the two high order bits of the data being loaded. Data bits are counted D1 through D8. C/D LS7066 SIGNAL REGISTER LEVEL D7 D8 ---------- ------ -- -- MASTER CONTROL REGISTER MCR 1 0 0 INPUT CONTROL REGISTER ICR 1 1 0 OUTPUT/COUNTER CONTROL REGISTER OCCR 1 0 1 QUADRATURE REGISTER QR 1 1 1 PRESET REGISTER PR, PR0, PR1, PR2 0 X X OUTPUT LATCH OL, OL0, OL1, OL2 0 X X The CBUS Function Addresses of the LS7066 for each of the Specific Triggers is the following: FSTD C/D CBUS CHANNEL SIGNAL FUNCTION NUMBER LEVEL ADDRESS ------ ------ ------- 1 0 0 1 1 1 2 0 2 2 1 3 3 0 4 3 1 5 4 0 6 4 1 7 LOADING THE LS7066 PROGRAMMING EXAMPLE ------------------------------------------ To Reset, Set Up for Divide By N, Load N (the Pre-Scale Ratio), and Enable the LS7066 to count do the following (this example is for FSTD Channel Number 1). Optional lines are for reading back the Pre-Scale Ratio fron the Preset register in the LS7066. CBUS LS7066 LS7066 D D LS7066 FUNCTION CBUS ACTION "DATA" 7 8 C/D ADDRESS DATA ---------------- ------ ---- ------ ------- ---- LOAD MASTER CONTROL REG. CLEAR THE MCR 0 0 0 1 1 0 MASTER RESET, PR-OL ADDR RESET 33 0 0 1 1 33 CLEAR THE MCR 0 0 0 1 1 0 LOAD THE PRESET REGISTER LOAD LOW BYTE OF PRE-SCALE X X 0 0 LOW N LOAD MID BYTE OF PRE-SCALE X X 0 0 MID N LOAD HI BYTE OF PRE-SCALE X X 0 0 HI N LOAD MASTER CONTROL REG. LOAD THE CNTR WITH PRESET VALUE 8 0 0 1 1 8 LOAD THE OL WITH THE CNTR DATA 2 0 0 1 1 2 ----------------------------------------------------------------------------- | OPTIONAL LINES TO READ BACK THE PRE-SCALE RATIO FROM THE PRESET REGISTER | | | | LOAD MASTER CONTROL REG. | | PR-OL ADDRESS COUNTER RESET 1 0 0 1 1 1 | | CLEAR THE MCR 0 0 0 1 1 0 | | | | READ THE OUTPUT LATCH (PRE-SCALE VALUE) | | READ LOW BYTE OF PRE-SCALE X X 0 0 LOW N | | TOGGLE DIRECTION TO WRITE AND READ AGAIN | | READ MID BYTE OF PRE-SCALE X X 0 0 MID N | | TOGGLE DIRECTION TO WRITE AND READ AGAIN | | READ HI BYTE OF PRE-SCALE X X 0 0 HI N | | | ----------------------------------------------------------------------------- LOAD OUTPUT/CNTR CONTROL REG. SELECT DIVIDE BY N MODE AND 4 0 1 1 1 132 ACTIVE LOW CARRY ON CY LOAD THE INPUT CONTROL REG. ENABLE "A" CLK FOR COUNT UP 8 1 0 1 1 72 LOAD MASTER CONTROL REG. PR-OL ADDRESS COUNTER RESET 1 0 0 1 1 1 CLEAR THE MCR 0 0 0 1 1 0 NOTE: The value loaded into the preset register should be 16,777,215 minus the value of the prescale ratio (it is an up counter). READING THE LS7066 PROGRAMMING EXAMPLE ---------------------------------------- To READ the Pre-Scale Ratio that has been loaded into the LS7066 do the following steps (this example is for FSTD Channel Number 1). This routine will cause the Pre-Scaler to pause while it is being read and it will leave the Pre-Scaler "initialized" at the begining of a Pre-Scale cycle: CBUS LS7066 LS7066 D D LS7066 FUNCTION CBUS ACTION "DATA" 7 8 C/D ADDRESS DATA ---------------- ------ ---- ------ ------- ---- LOAD THE INPUT CONTROL REG. DISABLE CLOCK INPUTS 0 1 0 1 1 64 LOAD MASTER CONTROL REG. CLEAR THE MCR 0 0 0 1 1 0 LOAD THE CNTR WITH PRESET VALUE 8 0 0 1 1 8 LOAD THE OL WITH THE CNTR DATA 2 0 0 1 1 2 PR-OL ADDRESS COUNTER RESET 1 0 0 1 1 1 CLEAR THE MCR 0 0 0 1 1 0 READ THE OUTPUT LATCH (PRE-SCALE VALUE) READ LOW BYTE OF PRE-SCALE X X 0 0 LOW N TOGGLE DIRECTION TO WRITE AND READ AGAIN READ MID BYTE OF PRE-SCALE X X 0 0 MID N TOGGLE DIRECTION TO WRITE AND READ AGAIN READ HI BYTE OF PRE-SCALE X X 0 0 HI N LOAD MASTER CONTROL REG. PR-OL ADDRESS COUNTER RESET 1 0 0 1 1 1 CLEAR THE MCR 0 0 0 1 1 0 LOAD THE INPUT CONTROL REG. ENABLE "A" CLK FOR COUNT UP 8 1 0 1 1 72 DISABLE SOURCE CONTROL REGISTERS The four Disable Source Control Registers on the FSTD Card are read-write registers and are located at the folloing Function Addresses. FSTD CARD CHANNEL NUMBER FUNCTION ADDRESS -------------- ---------------- 1 8 2 9 3 10 4 11 Bits numbers 1 through 7 in the byte loaded at each of these Function Addresses are used to control the various sources of disable signals for each Specific Trigger. When a given bit in this control register is a one then the corresponding disable signal is allowed to disable (veto) the Specific Trigger. In this condition the Specific Trigger will be disabled when the disable signal is active (high). When a given bit in this control register is a zero then the corresponding disable signal can not disable the Specific Trigger. Bit number 8 in the byte loaded at these Function Addresses is used to reset the Auto-Disable Flip-Flop. The normal condition for using the Auto-Disable Flip-Flop is for this bit to be a zero. When bit number 8 is a one then it forces a reset of the Auto-Disable Flip-Flop. BIT NUMBER FUNCTION ---------- --------------- 1 (LSB) A One => Enable the Pre-Scaler to disable the Specific Trigger 2 A One => Enable the Level 1.5 Disable Signal to disable the Specific Trigger 3 A One => Enable the Level 2.0 Disable Signal to disable the Specific Trigger 4 A One => Enable the Auxiliary #1 Disable Signal to disable the Specific Trigger 5 A One => Enable the Auxiliary #2 Disable Signal to disable the Specific Trigger 6 A One => Enable the Auxiliary #3 Disable Signal to disable the Specific Trigger 7 A One => Enable the Auto-Disable Flip-Flop to disable the Specific Trigger 8 (MSB) A One => Reset the Auto-Disable Flip-Flop When using the Auto-Disable Flip-Flop the typical sequence of loading the disable register and triggering would be the following: When ready for a trigger then: Load Data 64 ! Enable the Auto-Disable to Disable the Trigger Load Data 192 ! Enable the Auto-Disable to Disable the Trigger and Reset the Auto-Disable Flip-Flop Wait for a Trigger Trigger ! Now this Specific Trigger is Disabled When ready for the next trigger then: Load Data 64 ! Enable the Auto-Disable to Disable the Trigger Load Data 192 ! Enable the Auto-Disable to Disable the Trigger and Reset the Auto-Disable Flip-Flop Wait for a Trigger Trigger ! Now this Specific Trigger is Disabled DOUBLE BUFFERED MEMORY REGISTER The Double Buffered Memory Register on the FSTD Card is read using the following Function Address. This is a read only Function Addresses. FUNCTION ADDRESS PREVIOUS CROSSING CURRENT CROSSING ----------------- ---------------- 12 140 The bits in the Double Buffered Menory Register carry the following information: Double Buffered Memory Register Bit Number Information --------------- ------------- 1 (LSB) A ONE => Specific Trigger Number 1 is ENABLED 2 A ONE => Specific Trigger Number 2 is ENABLED 3 A ONE => Specific Trigger Number 3 is ENABLED 4 A ONE => Specific Trigger Number 4 is ENABLED 5 A ONE => Specific Trigger Number 1 AND-OR Signals are High 6 A ONE => Specific Trigger Number 2 AND-OR Signals are High 7 A ONE => Specific Trigger Number 3 AND-OR Signals are High 8 (MSB) A ONE => Specific Trigger Number 4 AND-OR Signals are High INPUT-OUTPUT CONNECTIONS: ------------------------- FINAL SPECIFIC TRIGGER DECISION CARD CONNECTORS ----------------------------------------------- BACK PLANE -------------------------------- : ---------- ----------- : : : J1 : : J2 : : : ---------- ----------- : : : : : : FSTD CARD : : : : : : -------- -------- : : : J3 : : J4 : : : -------- -------- : -------------------------------- FRONT CONNECTOR J1 THIS CONNECTOR SERVICES: THE 20 DISABLE INPUTS ------------- AND THE 32 OUTPUTS TO THE SINCLE BUFFERED SCALERS ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 brown 1.5 Disable Input Channel #1 Non-inverted IN 1 ND151 4 tan 1.5 Disable Input Channel #1 inverted IN 2 ID141 5 red 1.5 Disable Input Channel #2 Non-inverted IN 3 ND152 6 tan 1.5 Disable Input Channel #2 inverted IN 4 ID152 7 orange 1.5 Disable Input Channel #3 Non-inverted IN 5 ND153 8 tan 1.5 Disable Input Channel #3 inverted IN 6 ID153 9 yellow 1.5 Disable Input Channel #4 Non-inverted IN 7 ND154 10 tan 1.5 Disable Input Channel #4 inverted IN 8 ID154 11 green 2.0 Disable Input Channel #1 Non-inverted IN 9 ND201 12 tan 2.0 Disable Input Channel #1 inverted IN 10 ID201 13 blue 2.0 Disable Input Channel #2 Non-inverted IN 11 ND202 14 tan 2.0 Disable Input Channel #2 inverted IN 12 ID202 15 violet 2.0 Disable Input Channel #3 Non-inverted IN 13 ND203 16 tan 2.0 Disable Input Channel #3 inverted IN 14 ID203 17 grey 2.0 Disable Input Channel #4 Non-inverted IN 15 ND204 18 tan 2.0 Disable Input Channel #4 inverted IN 16 ID204 19 white Aux 1 Disable Input Chnl #1 Non-inverted IN 17 NA1D1 20 tan Aux 1 Disable Input Chnl #1 inverted IN 18 IA1D1 21 black Aux 1 Disable Input Chnl #2 Non-inverted IN 19 NA1D2 22 tan Aux 1 Disable Input Chnl #2 inverted IN 20 IA1D2 23 brown Aux 1 Disable Input Chnl #3 Non-inverted IN 21 NA1D3 24 tan Aux 1 Disable Input Chnl #3 inverted IN 22 IA1D3 25 red Aux 1 Disable Input Chnl #4 Non-inverted IN 23 NA1D4 26 tan Aux 1 Disable Input Chnl #4 inverted IN 24 IA1D4 27 orange Aux 2 Disable Input Chnl #1 Non-inverted IN 25 NA2D1 28 tan Aux 2 Disable Input Chnl #1 inverted IN 26 IA2D1 29 yellow Aux 2 Disable Input Chnl #2 Non-inverted IN 27 NA2D2 30 tan Aux 2 Disable Input Chnl #2 inverted IN 28 IA2D2 31 green Aux 2 Disable Input Chnl #3 Non-inverted IN 29 NA2D3 32 tan Aux 2 Disable Input Chnl #3 inverted IN 30 IA2D3 33 blue Aux 2 Disable Input Chnl #4 Non-inverted IN 31 NA2D4 34 tan Aux 2 Disable Input Chnl #4 inverted IN 32 IA2D4 35 violet Aux 3 Disable Input Chnl #1 Non-inverted IN 33 NA3D1 36 tan Aux 3 Disable Input Chnl #1 inverted IN 34 IA3D1 37 grey Aux 3 Disable Input Chnl #2 Non-inverted IN 35 NA3D2 38 tan Aux 3 Disable Input Chnl #2 inverted IN 36 IA3D2 39 white Aux 3 Disable Input Chnl #3 Non-inverted IN 37 NA3D3 40 tan Aux 3 Disable Input Chnl #3 inverted IN 38 IA3D3 41 black Aux 3 Disable Input Chnl #4 Non-inverted IN 39 NA3D4 42 tan Aux 3 Disable Input Chnl #4 inverted IN 40 IA3D4 43 brown NO CONNECTION Non-inverted IN 41 NSPARE 44 tan NO CONNECTION inverted IN 42 ISPARE 45 red NO CONNECTION Non-inverted IN 43 NSPARE 46 tan NO CONNECTION inverted IN 44 ISPARE 47 orange NO CONNECTION Non-inverted IN 45 NSPARE 48 tan NO CONNECTION inverted IN 46 ISPARE 49 yellow NO CONNECTION Non-inverted IN 47 NSPARE 50 tan NO CONNECTION inverted IN 48 ISPARE 51 green NO CONNECTION Non-inverted IN 49 NSPARE 52 tan NO CONNECTION inverted IN 50 ISPARE 53 blue NO CONNECTION Non-inverted IN 51 NSPARE 54 tan NO CONNECTION inverted IN 52 ISPARE 55 violet NO CONNECTION Non-inverted IN 53 NSPARE 56 tan NO CONNECTION inverted IN 54 ISPARE 57 grey NO CONNECTION Non-inverted IN 55 NSPARE 58 tan NO CONNECTION inverted IN 56 ISPARE 59 white NO CONNECTION Non-inverted IN 57 NSPARE 60 tan NO CONNECTION inverted IN 58 ISPARE 61 black NO CONNECTION Non-inverted IN 59 NSPARE 62 tan NO CONNECTION inverted IN 60 ISPARE 63 brown NO CONNECTION Non-inverted IN 61 NSPARE 64 tan NO CONNECTION inverted IN 62 ISPARE 65 red NO CONNECTION Non-inverted IN 63 NSPARE 66 tan NO CONNECTION inverted IN 64 ISPARE 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown SBSC CH#1 PRE-SCL DS FSTD#1 Non-inverted OUT 1 NSBC1 76 tan SBSC CH#1 PRE-SCL DS FSTD#1 Inverted OUT 2 ISBC1 77 red SBSC CH#2 LEVEL 1.5 FSTD#1 Non-inverted OUT 3 NSBC2 78 tan SBSC CH#2 LEVEL 1.5 FSTD#1 Inverted OUT 4 ISBC2 79 orange SBSC CH#3 LEVEL 2.0 FSTD#1 Non-inverted OUT 5 NSBC3 80 tan SBSC CH#3 LEVEL 2.0 FSTD#1 Inverted OUT 6 ISBC3 81 yellow SBSC CH#4 AUX 1 DSB FSTD#1 Non-inverted OUT 7 NSBC4 82 tan SBSC CH#4 AUX 1 DSB FSTD#1 Inverted OUT 8 ISBC4 83 green SBSC CH#5 AUX 2 DSB FSTD#1 Non-inverted OUT 9 NSBC5 84 tan SBSC CH#5 AUX 2 DSB FSTD#1 Inverted OUT 10 ISBC5 85 blue SBSC CH#6 AUX 3 DSB FSTD#1 Non-inverted OUT 11 NSBC6 86 tan SBSC CH#6 AUX 3 DSB FSTD#1 Inverted OUT 12 ISBC6 87 violet SBSC CH#7 AUTO-DSBL FSTD#1 Non-inverted OUT 13 NSBC7 88 tan SBSC CH#7 AUTO-DSBL FSTD#1 Inverted OUT 14 ISBC7 89 grey SBSC CH#8 AND-OR HIT FSTD#1 Non-inverted OUT 15 NSBC8 90 tan SBSC CH#8 AND-OR HIT FSTD#1 Inverted OUT 16 ISBC8 91 white SBSC CH#9 PRE-SCL DS FSTD#2 Non-inverted OUT 17 NSBC9 92 tan SBSC CH#9 PRE-SCL DS FSTD#2 Inverted OUT 18 ISBC9 93 black SBSC CH#10 LEVEL 1.5 FSTD#2 Non-inverted OUT 19 NSBC10 94 tan SBSC CH#10 LEVEL 1.5 FSTD#2 Inverted OUT 20 ISBC10 95 brown SBSC CH#11 LEVEL 2.0 FSTD#2 Non-inverted OUT 21 NSBC11 96 tan SBSC CH#11 LEVEL 2.0 FSTD#2 Inverted OUT 22 ISBC11 97 red SBSC CH#12 AUX 1 DSB FSTD#2 Non-inverted OUT 23 NSBC12 98 tan SBSC CH#12 AUX 1 DSB FSTD#2 Inverted OUT 24 ISBC12 99 orange SBSC CH#13 AUX 2 DSB FSTD#2 Non-inverted OUT 25 NSBC13 100 tan SBSC CH#13 AUX 2 DSB FSTD#2 Inverted OUT 26 ISBC13 101 yellow SBSC CH#14 AUX 3 DSB FSTD#2 Non-inverted OUT 27 NSBC14 102 tan SBSC CH#14 AUX 3 DSB FSTD#2 Inverted OUT 28 ISBC14 103 green SBSC CH#15 AUTO-DSBL FSTD#2 Non-inverted OUT 29 NSBC15 104 tan SBSC CH#15 AUTO-DSBL FSTD#2 Inverted OUT 30 ISBC15 105 blue SBSC CH#16 AND-OR HIT FSTD#2 Non-inverted OUT 31 NSBC16 106 tan SBSC CH#16 AND-OR HIT FSTD#2 Inverted OUT 32 ISBC16 107 violet SBSC CH#17 PRE-SCL DS FSTD#3 Non-inverted OUT 33 NSBC17 108 tan SBSC CH#17 PRE-SCL DS FSTD#3 Inverted OUT 34 ISBC17 109 grey SBSC CH#18 LEVEL 1.5 FSTD#3 Non-inverted OUT 35 NSBC18 110 tan SBSC CH#18 LEVEL 1.5 FSTD#3 Inverted OUT 36 ISBC18 111 white SBSC CH#19 LEVEL 2.0 FSTD#3 Non-inverted OUT 37 NSBC19 112 tan SBSC CH#19 LEVEL 2.0 FSTD#3 Inverted OUT 38 ISBC19 113 black SBSC CH#20 AUX 1 DSB FSTD#3 Non-inverted OUT 39 NSBC20 114 tan SBSC CH#20 AUX 1 DSB FSTD#3 Inverted OUT 40 ISBC20 115 brown SBSC CH#21 AUX 2 DSB FSTD#3 Non-inverted OUT 41 NSBC21 116 tan SBSC CH#21 AUX 2 DSB FSTD#3 Inverted OUT 42 ISBC21 117 red SBSC CH#22 AUX 3 DSB FSTD#3 Non-inverted OUT 43 NSBC22 118 tan SBSC CH#22 AUX 3 DSB FSTD#3 Inverted OUT 44 ISBC22 119 orange SBSC CH#23 AUTO-DSBL FSTD#3 Non-inverted OUT 45 NSBC23 120 tan SBSC CH#23 AUTO-DSBL FSTD#3 Inverted OUT 46 ISBC23 121 yellow SBSC CH#24 AND-OR HIT FSTD#3 Non-inverted OUT 47 NSBC24 122 tan SBSC CH#24 AND-OR HIT FSTD#3 Inverted OUT 48 ISBC24 123 green SBSC CH#25 PRE-SCL DS FSTD#4 Non-inverted OUT 49 NSBC25 124 tan SBSC CH#25 PRE-SCL DS FSTD#4 Inverted OUT 50 ISBC25 125 blue SBSC CH#26 LEVEL 1.5 FSTD#4 Non-inverted OUT 51 NSBC26 126 tan SBSC CH#26 LEVEL 1.5 FSTD#4 Inverted OUT 52 ISBC26 127 violet SBSC CH#27 LEVEL 2.0 FSTD#4 Non-inverted OUT 53 NSBC27 128 tan SBSC CH#27 LEVEL 2.0 FSTD#4 Inverted OUT 54 ISBC27 129 grey SBSC CH#28 AUX 1 DSB FSTD#4 Non-inverted OUT 55 NSBC28 130 tan SBSC CH#28 AUX 1 DSB FSTD#4 Inverted OUT 56 ISBC28 131 white SBSC CH#29 AUX 2 DSB FSTD#4 Non-inverted OUT 57 NSBC29 132 tan SBSC CH#29 AUX 2 DSB FSTD#4 Inverted OUT 58 ISBC29 133 black SBSC CH#30 AUX 3 DSB FSTD#4 Non-inverted OUT 59 NSBC30 134 tan SBSC CH#30 AUX 3 DSB FSTD#4 Inverted OUT 60 ISBC30 135 brown SBSC CH#31 AUTO-DSBL FSTD#4 Non-inverted OUT 61 NSBC31 136 tan SBSC CH#31 AUTO-DSBL FSTD#4 Inverted OUT 62 ISBC31 137 red SBSC CH#32 AND-OR HIT FSTD#4 Non-inverted OUT 63 NSBC32 138 tan SBSC CH#32 AND-OR HIT FSTD#4 Inverted OUT 64 ISBC32 139 Ground GND 140 Ground GND CONNECTOR J2 THE SPECIFIC BACKPLANE BUS CONNECTOR ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 Ground GND 2 Ground GND 3 FSTD CH#1 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF1 4 FSTD CH#1 FIRED GATE SIGNAL TO DBSC Inverted ISTF1 5 NO CONNECTION Non-Inverted NSPARE 6 NO CONNECTION Inverted ISPARE 7 NO CONNECTION Non-Inverted NSPARE 8 NO CONNECTION Inverted ISPARE 9 FSTD CH#2 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF2 10 FSTD CH#2 FIRED GATE SIGNAL TO DBSC Inverted ISTF2 11 NO CONNECTION Non-Inverted NSPARE 12 NO CONNECTION Inverted ISPARE 13 NO CONNECTION Non-Inverted NSPARE 14 NO CONNECTION Inverted ISPARE 15 FSTD CH#3 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF3 16 FSTD CH#3 FIRED GATE SIGNAL TO DBSC Inverted ISTF3 17 NO CONNECTION Non-Inverted NSPARE 18 NO CONNECTION Inverted ISPARE 19 NO CONNECTION Non-Inverted NSPARE 20 NO CONNECTION Inverted ISPARE 21 FSTD CH#4 FIRED GATE SIGNAL TO DBSC Non-Inverted NSTF4 22 FSTD CH#4 FIRED GATE SIGNAL TO DBSC Inverted ISTF4 23 NO CONNECTION Non-Inverted NSPARE 24 NO CONNECTION Inverted ISPARE 25 NO CONNECTION Non-Inverted NSPARE 26 NO CONNECTION Inverted ISPARE 27 FSTD CH#1 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE1 28 FSTD CH#1 ENABLED GATE SIGNAL TO DBSC Inverted ISTE1 29 NO CONNECTION Non-Inverted NSPARE 30 NO CONNECTION Inverted ISPARE 31 NO CONNECTION Non-Inverted NSPARE 32 NO CONNECTION Inverted ISPARE 33 FSTD CH#2 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE2 34 FSTD CH#2 ENABLED GATE SIGNAL TO DBSC Inverted ISTE2 35 NO CONNECTION Non-Inverted NSPARE 36 NO CONNECTION Inverted ISPARE 37 NO CONNECTION Non-Inverted NSPARE 38 NO CONNECTION Inverted ISPARE 39 FSTD CH#3 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE3 40 FSTD CH#3 ENABLED GATE SIGNAL TO DBSC Inverted ISTE3 41 NO CONNECTION Non-Inverted NSPARE 42 NO CONNECTION Inverted ISPARE 43 NO CONNECTION Non-Inverted NSPARE 44 NO CONNECTION Inverted ISPARE 45 FSTD CH#4 ENABLED GATE SIGNAL TO DBSC Non-Inverted NSTE4 46 FSTD CH#4 ENABLED GATE SIGNAL TO DBSC Inverted ISTE4 47 NO CONNECTION Non-Inverted NSPARE 48 NO CONNECTION Inverted ISPARE 49 NO CONNECTION Non-Inverted NSPARE 50 NO CONNECTION Inverted ISPARE 51 NOT USED . . . . . . . . . 66 NOT USED 67 Ground GND 68 Ground GND 69 Power +5.0 V VCC 70 Power +5.0 V VCC 71 Power -5.2 V VEE 72 Power -5.2 V VEE 73 Ground GND 74 Ground GND 75 brown TSS-A SELECT WRITE A/B Non-inverted IN 1 NTSA 76 tan TSS-A SELECT WRITE A/B Inverted IN 2 ITSA 77 red TSS-B LATCH/SHIFT Non-inverted IN 3 NTSB 78 tan TSS-B LATCH/SHIFT Inverted IN 4 ITSB 79 orange TSS-C SELECT READ A/B Non-inverted IN 5 NTSC 80 tan TSS-C SELECT READ A/B Inverted IN 6 ITSC 81 yellow Timing & Sync. Signal D Non-inverted IN 7 NTSD 82 tan Timing & Sync. Signal D Inverted IN 8 ITSD 83 green Timing & Sync. Signal E Non-inverted IN 9 NTSE 84 tan Timing & Sync. Signal E Inverted IN 10 ITSE 85 blue FSTD DISABLE CLOCK SIGNAL Non-inverted IN 11 NFDC 86 tan FSTD DISABLE CLOCK SIGNAL Inverted IN 12 IFDC 87 violet FSTD AND-OR STROBE SIGNAL Non-inverted IN 13 NFAS 88 tan FSTD AND-OR STROBE SIGNAL Inverted IN 14 IFAS 89 grey TSS-H LED's OFF Non-inverted IN 15 NTSH 90 tan TSS-H LED's OFF Inverted IN 16 ITSH 91 white Card Address Bit#1 Non-inverted IN 17 NAC1 92 tan Card Address Bit#1 Inverted IN 18 IAC1 93 black Card Address Bit#2 Non-inverted IN 19 NAC2 94 tan Card Address Bit#2 Inverted IN 20 IAC2 95 brown Card Address Bit#3 Non-inverted IN 21 NAC3 96 tan Card Address Bit#3 Inverted IN 22 IAC3 97 red Card Address Bit#4 Non-inverted IN 23 NAC4 98 tan Card Address Bit#4 Inverted IN 24 IAC4 99 orange Card Address Bit#5 Non-inverted IN 25 NAC5 100 tan Card Address Bit#5 Inverted IN 26 IAC5 101 yellow Card Address Bit#6 Non-inverted IN 27 NAC6 102 tan Card Address Bit#6 Inverted IN 28 IAC6 103 green Function Address Bit#1 Non-inverted IN 29 NAF1 104 tan Function Address Bit#1 Inverted IN 30 IAF1 105 blue Function Address Bit#2 Non-inverted IN 31 NAF2 106 tan Function Address Bit#2 Inverted IN 32 IAF2 107 violet Function Address Bit#3 Non-inverted IN 33 NAF3 108 tan Function Address Bit#3 Inverted IN 34 IAF3 109 grey Function Address Bit#4 Non-inverted IN 35 NAF4 110 tan Function Address Bit#4 Inverted IN 36 IAF4 111 white Function Address Bit#5 Non-inverted IN 37 NAF5 112 tan Function Address Bit#5 Inverted IN 38 IAF5 113 black Function Address Bit#6 Non-inverted IN 39 NAF6 114 tan Function Address Bit#6 Inverted IN 40 IAF6 115 brown Function Address Bit#7 Non-inverted IN 41 NAF7 116 tan Function Address Bit#7 Inverted IN 42 IAF7 117 red Function Address Bit#8 Non-inverted IN 43 NAF8 118 tan Function Address Bit#8 Inverted IN 44 IAF8 119 orange Strobe Non-inverted IN 45 NSTB 120 tan Strobe Inverted IN 46 ISTB 121 yellow Direction Non-inverted IN 47 NDIR 122 tan Direction Inverted IN 48 IDIR 123 green Bidirectional Data Bit#1 Non-inverted IN 49 NDB1 124 tan Bidirectional Data Bit#1 Inverted IN 50 IDB1 125 blue Bidirectional Data Bit#2 Non-inverted IN 51 NDB2 126 tan Bidirectional Data Bit#2 Inverted IN 52 IDB2 127 violet Bidirectional Data Bit#3 Non-inverted IN 53 NDB3 128 tan Bidirectional Data Bit#3 Inverted IN 54 IDB3 129 grey Bidirectional Data Bit#4 Non-inverted IN 55 NDB4 130 tan Bidirectional Data Bit#4 Inverted IN 56 IDB4 131 white Bidirectional Data Bit#5 Non-inverted IN 57 NDB5 132 tan Bidirectional Data Bit#5 Inverted IN 58 IDB5 133 black Bidirectional Data Bit#6 Non-inverted IN 59 NDB6 134 tan Bidirectional Data Bit#6 Inverted IN 60 IDB6 135 brown Bidirectional Data Bit#7 Non-inverted IN 61 NDB7 136 tan Bidirectional Data Bit#7 Inverted IN 62 IDB7 137 red Bidirectional Data Bit#8 Non-inverted IN 63 NDB8 138 tan Bidirectional Data Bit#8 Inverted IN 64 IDB8 139 Ground GND 140 Ground GND CONNECTOR J3 CONNECTOR TO RECEIVE THE SIGNALS FROM THE AND-OR CARDS ------------- ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 blue AND-OR #4 FSTD CHANNEL #4 Non-inverted IN 31 NA4F4 2 tan AND-OR #4 FSTD CHANNEL #4 inverted IN 32 IA4F4 3 green AND-OR #3 FSTD CHANNEL #4 Non-inverted IN 29 NA3F4 4 tan AND-OR #3 FSTD CHANNEL #4 inverted IN 30 IA3F4 5 yellow AND-OR #2 FSTD CHANNEL #4 Non-inverted IN 27 NA2F4 6 tan AND-OR #2 FSTD CHANNEL #4 inverted IN 28 IA2F4 7 orange AND-OR #1 FSTD CHANNEL #4 Non-inverted IN 25 NA1F4 8 tan AND-OR #1 FSTD CHANNEL #4 inverted IN 26 IA1F4 9 red AND-OR #4 FSTD CHANNEL #3 Non-inverted IN 23 NA4F3 10 tan AND-OR #4 FSTD CHANNEL #3 inverted IN 24 IA4F3 11 brown AND-OR #3 FSTD CHANNEL #3 Non-inverted IN 21 NA3F3 12 tan AND-OR #3 FSTD CHANNEL #3 inverted IN 22 IA3F3 13 black AND-OR #2 FSTD CHANNEL #3 Non-inverted IN 19 NA2F3 14 tan AND-OR #2 FSTD CHANNEL #3 inverted IN 20 IA2F3 15 white AND-OR #1 FSTD CHANNEL #3 Non-inverted IN 17 NA1F3 16 tan AND-OR #1 FSTD CHANNEL #3 inverted IN 18 IA1F3 17 grey AND-OR #4 FSTD CHANNEL #2 Non-inverted IN 15 NA4F2 18 tan AND-OR #4 FSTD CHANNEL #2 inverted IN 16 IA4F2 19 violet AND-OR #3 FSTD CHANNEL #2 Non-inverted IN 13 NA3F2 20 tan AND-OR #3 FSTD CHANNEL #2 inverted IN 14 IA3F2 21 blue AND-OR #2 FSTD CHANNEL #2 Non-inverted IN 11 NA2F2 22 tan AND-OR #2 FSTD CHANNEL #2 inverted IN 12 IA2F2 23 green AND-OR #1 FSTD CHANNEL #2 Non-inverted IN 9 NA1F2 24 tan AND-OR #1 FSTD CHANNEL #2 inverted IN 10 IA1F2 25 yellow AND-OR #4 FSTD CHANNEL #1 Non-inverted IN 7 NA4F1 26 tan AND-OR #5 FSTD CHANNEL #1 inverted IN 8 IA4F1 27 orange AND-OR #3 FSTD CHANNEL #1 Non-inverted IN 5 NA3F1 28 tan AND-OR #3 FSTD CHANNEL #1 inverted IN 6 IA3F1 29 red AND-OR #2 FSTD CHANNEL #1 Non-inverted IN 3 NA2F1 30 tan AND-OR #2 FSTD CHANNEL #1 inverted IN 4 IA2F1 31 brown AND-OR #1 FSTD CHANNEL #1 Non-inverted IN 1 NA1F1 32 tan AND-OR #1 FSTD CHANNEL #1 inverted IN 2 IA1F1 33 violet NOT CONNECTED Non-inverted IN 33 NSPARE 34 tan NOT CONNECTED inverted IN 34 ISPARE CONNECTOR J4 CONNECTOR TO OUTPUT THE SPECIFIC TRIGGER FIRED SIGNALS ------------- AND THE AND-OR FIRED SIGNALS ------------------------------------------------------------------------------ Plug & PIN Color Function Wire # Mnemonic # on cable on cable ------------------------------------------------------------------------------ 1 brown FSTD CHANNEL #1 FIRED Non-inverted OUT 1 NFT1F 2 tan FSTD CHANNEL #1 FIRED inverted OUT 2 IFT1F 3 red FSTD CHANNEL #2 FIRED Non-inverted OUT 3 NFT2F 4 tan FSTD CHANNEL #2 FIRED inverted OUT 4 IFT2F 5 orange FSTD CHANNEL #3 FIRED Non-inverted OUT 5 NFT3F 6 tan FSTD CHANNEL #3 FIRED inverted OUT 6 IFT3F 7 yellow FSTD CHANNEL #4 FIRED Non-inverted OUT 7 NFT4F 8 tan FSTD CHANNEL #4 FIRED inverted OUT 8 IFT4F 9 green FSTD CHANNEL #1 AND-OR FIRED Non-inverted OUT 9 NAO1F 10 tan FSTD CHANNEL #1 AND-OR FIRED inverted OUT 10 IAO1F 11 blue FSTD CHANNEL #1 AND-OR FIRED Non-inverted OUT 11 NAO2F 12 tan FSTD CHANNEL #1 AND-OR FIRED inverted OUT 12 IAO2F 13 violet FSTD CHANNEL #1 AND-OR FIRED Non-inverted OUT 13 NAO3F 14 tan FSTD CHANNEL #1 AND-OR FIRED inverted OUT 14 IAO3F 15 grey FSTD CHANNEL #1 AND-OR FIRED Non-inverted OUT 15 NAO4F 16 tan FSTD CHANNEL #1 AND-OR FIRED inverted OUT 16 IAO4F 17 white SPARE Non-inverted IN 17 NSPARE 18 tan SPARE inverted IN 18 ISPARE 19 black SPARE Non-inverted IN 19 NSPARE 20 tan SPARE inverted IN 20 ISPARE 21 brown SPARE Non-inverted IN 21 NSPARE 22 tan SPARE inverted IN 22 ISPARE 23 red SPARE Non-inverted IN 23 NSPARE 24 tan SPARE inverted IN 24 ISPARE 25 orange SPARE Non-inverted IN 25 NSPARE 26 tan SPARE inverted IN 26 ISPARE 27 yellow SPARE Non-inverted IN 27 NSPARE 28 tan SPARE inverted IN 28 ISPARE 29 green SPARE Non-inverted IN 29 NSPARE 30 tan SPARE inverted IN 30 ISPARE 31 blue SPARE Non-inverted IN 31 NSPARE 32 tan SPARE inverted IN 32 ISPARE 33 violet SPARE Non-inverted IN 33 NSPARE 34 tan SPARE inverted IN 34 ISPARE LED INDICATORS -------------- The FSTD Card has 16 LED indicators near the front of the card. These are used to show the status of the following signals: ENABLE FSTD CHANNEL 1, LED ON ==> CHANNEL IS ENABLED TO SEND A TRIGGER ENABLE FSTD CHANNEL 2, LED ON ==> CHANNEL IS ENABLED TO SEND A TRIGGER ENABLE FSTD CHANNEL 3, LED ON ==> CHANNEL IS ENABLED TO SEND A TRIGGER ENABLE FSTD CHANNEL 4, LED ON ==> CHANNEL IS ENABLED TO SEND A TRIGGER AND-OR FIRED CHANNEL 1, LED ON ==> THE AND-OR CARDS ARE SENDING A HI AND-OR FIRED CHANNEL 2, LED ON ==> THE AND-OR CARDS ARE SENDING A HI AND-OR FIRED CHANNEL 3, LED ON ==> THE AND-OR CARDS ARE SENDING A HI AND-OR FIRED CHANNEL 4, LED ON ==> THE AND-OR CARDS ARE SENDING A HI READ, WAKE UP, WRITE A, WRITE B, CURRENT/PREVIOUS, BUFFER READ, 29520 SELECT, LATCH/SHIFT SWITCH U85 CARDS ADDRESS SELECTOR SWITCH ---------- This switch controls the Card Address at which this card will wake up. When a switch is closed the coresponding bit in the Card Address is a 0 and when a switch is open then the corresponding bit is a 1. ADDRESS SWITCH SECTION CARD ADDRESS BIT BIT VALUE ---------------- ------------------ ----------- 1 6 32 2 5 16 3 4 8 4 3 4 5 2 2 6 1 1 7 ALWAYS CLOSED 8 ALWAYS CLOSED BOARD ORDERS HISTORY: 2 BOARDS ORDERED APRIL 1987 16 BOARDS ORDERED JULY 1987 ETCH REVISION HISTORY: REVISION A APRIL 1987 REVISION B JULY 1987 ECO HISTORY: SEE BELOW POWER REQUIREMENTS: VCC +5.0 Volts at ? Amps VEE -5.2 Volts at ? Amps PARTS LIST: QUANTITY ITEM -------- ------ 1 74 ALS 04 4 74 ALS 08 4 74 ALS 30 8 74 ALS 74 6 74 ALS 138 1 74 ALS 245 1 74 ALS 520 2 74 ALS 540 1 74 ALS 541 3 10 H 101 4 10 H 109 4 10 H 115 13 10 H 124 15 10 H 125 3 10 H 188 4 7066 LSI 1 AM29520 8 PAL16R4A 4 7902 16 LED 1 8 POSITION DIP SWITCH 12 56 OHM 10 PIN SIP 5 110 OHM 16 PIN DIP 8 ISOLATED RESISTORS 4 470 OHM 6 PIN SIP 3 470 OHM 8 PIN SIP 2 470 OHM 10 PIN SIP 1 10k OHM 8 PIN SIP 2 34 PIN RIGHT ANGLE HEADER SOLDER TAIL 2 140 pin connectors right angle 112 MONOCAP 0.1 uFD 25 V 8 1uFD 35 Volt TANT. MODIFICATIONS TO REVISION A: ------------------------------ All Revision A: boards are obsolete. MODIFICATIONS TO REVISION B: ------------------------------ To the default state resistors near J3, R29 pin 1 and R30 pin 1 need to be connected to the wide Vee trace near the receiver chips. The wirewrap pins labeled LD GT B should be labeled B LD GT. All wire wraps should be on. Because the READ signal to the 7066's is not strobe like we will need a special type of C-BUS read cycle to read the 7066 Output Latch Data. To allow for a global software disable signal, Aux 3 Disable must be tied high in the following way: Connect U5 pin 9 to R3 pin 9 Place a 10Kohm, 8-pin SIP resistor pack in the R3 socket, with pin 1 of the SIP in pin 9 of the socket. 30-JUN-1988